f1837377d2
On 32-bit MIPS, 64-bit atomic ops are achieved through locks. So allow the test to fail for atomic_intmax_t on 32-bit MIPS. Change-Id: I78e7807e50f899a0fea0d5b388d9ebb53228aaa0
171 lines
5.4 KiB
C++
171 lines
5.4 KiB
C++
/*
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* Copyright (C) 2014 The Android Open Source Project
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include <gtest/gtest.h>
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#if !defined(__GLIBC__) /* TODO: fix our prebuilt toolchains! */
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#include <stdatomic.h>
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TEST(stdatomic, LOCK_FREE) {
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ASSERT_TRUE(ATOMIC_BOOL_LOCK_FREE);
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ASSERT_TRUE(ATOMIC_CHAR16_T_LOCK_FREE);
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ASSERT_TRUE(ATOMIC_CHAR32_T_LOCK_FREE);
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ASSERT_TRUE(ATOMIC_CHAR_LOCK_FREE);
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ASSERT_TRUE(ATOMIC_INT_LOCK_FREE);
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ASSERT_TRUE(ATOMIC_LLONG_LOCK_FREE);
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ASSERT_TRUE(ATOMIC_LONG_LOCK_FREE);
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ASSERT_TRUE(ATOMIC_POINTER_LOCK_FREE);
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ASSERT_TRUE(ATOMIC_SHORT_LOCK_FREE);
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ASSERT_TRUE(ATOMIC_WCHAR_T_LOCK_FREE);
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}
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TEST(stdatomic, init) {
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atomic_int v = ATOMIC_VAR_INIT(123);
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ASSERT_EQ(123, atomic_load(&v));
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atomic_init(&v, 456);
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ASSERT_EQ(456, atomic_load(&v));
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atomic_flag f = ATOMIC_FLAG_INIT;
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ASSERT_FALSE(atomic_flag_test_and_set(&f));
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}
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TEST(stdatomic, atomic_thread_fence) {
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atomic_thread_fence(memory_order_relaxed);
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atomic_thread_fence(memory_order_consume);
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atomic_thread_fence(memory_order_acquire);
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atomic_thread_fence(memory_order_release);
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atomic_thread_fence(memory_order_acq_rel);
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atomic_thread_fence(memory_order_seq_cst);
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}
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TEST(stdatomic, atomic_signal_fence) {
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atomic_signal_fence(memory_order_relaxed);
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atomic_signal_fence(memory_order_consume);
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atomic_signal_fence(memory_order_acquire);
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atomic_signal_fence(memory_order_release);
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atomic_signal_fence(memory_order_acq_rel);
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atomic_signal_fence(memory_order_seq_cst);
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}
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TEST(stdatomic, atomic_is_lock_free) {
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atomic_char small;
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atomic_intmax_t big;
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ASSERT_TRUE(atomic_is_lock_free(&small));
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// atomic_intmax_t(size = 64) is not lock free on mips32.
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#if defined(__mips__) && !defined(__LP64__)
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ASSERT_FALSE(atomic_is_lock_free(&big));
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#else
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ASSERT_TRUE(atomic_is_lock_free(&big));
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#endif
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}
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TEST(stdatomic, atomic_flag) {
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atomic_flag f = ATOMIC_FLAG_INIT;
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ASSERT_FALSE(atomic_flag_test_and_set(&f));
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ASSERT_TRUE(atomic_flag_test_and_set(&f));
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atomic_flag_clear(&f);
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ASSERT_FALSE(atomic_flag_test_and_set_explicit(&f, memory_order_relaxed));
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ASSERT_TRUE(atomic_flag_test_and_set_explicit(&f, memory_order_relaxed));
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atomic_flag_clear_explicit(&f, memory_order_relaxed);
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ASSERT_FALSE(atomic_flag_test_and_set_explicit(&f, memory_order_relaxed));
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}
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TEST(stdatomic, atomic_store) {
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atomic_int i;
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atomic_store(&i, 123);
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ASSERT_EQ(123, atomic_load(&i));
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atomic_store_explicit(&i, 123, memory_order_relaxed);
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ASSERT_EQ(123, atomic_load_explicit(&i, memory_order_relaxed));
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}
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TEST(stdatomic, atomic_exchange) {
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atomic_int i;
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atomic_store(&i, 123);
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ASSERT_EQ(123, atomic_exchange(&i, 456));
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ASSERT_EQ(456, atomic_exchange_explicit(&i, 123, memory_order_relaxed));
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}
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TEST(stdatomic, atomic_compare_exchange) {
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atomic_int i;
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int expected;
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atomic_store(&i, 123);
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expected = 123;
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ASSERT_TRUE(atomic_compare_exchange_strong(&i, &expected, 456));
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ASSERT_FALSE(atomic_compare_exchange_strong(&i, &expected, 456));
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ASSERT_EQ(456, expected);
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atomic_store(&i, 123);
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expected = 123;
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ASSERT_TRUE(atomic_compare_exchange_strong_explicit(&i, &expected, 456, memory_order_relaxed, memory_order_relaxed));
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ASSERT_FALSE(atomic_compare_exchange_strong_explicit(&i, &expected, 456, memory_order_relaxed, memory_order_relaxed));
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ASSERT_EQ(456, expected);
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atomic_store(&i, 123);
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expected = 123;
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ASSERT_TRUE(atomic_compare_exchange_weak(&i, &expected, 456));
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ASSERT_FALSE(atomic_compare_exchange_weak(&i, &expected, 456));
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ASSERT_EQ(456, expected);
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atomic_store(&i, 123);
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expected = 123;
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ASSERT_TRUE(atomic_compare_exchange_weak_explicit(&i, &expected, 456, memory_order_relaxed, memory_order_relaxed));
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ASSERT_FALSE(atomic_compare_exchange_weak_explicit(&i, &expected, 456, memory_order_relaxed, memory_order_relaxed));
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ASSERT_EQ(456, expected);
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}
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TEST(stdatomic, atomic_fetch_add) {
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atomic_int i = ATOMIC_VAR_INIT(123);
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ASSERT_EQ(123, atomic_fetch_add(&i, 1));
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ASSERT_EQ(124, atomic_fetch_add_explicit(&i, 1, memory_order_relaxed));
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ASSERT_EQ(125, atomic_load(&i));
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}
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TEST(stdatomic, atomic_fetch_sub) {
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atomic_int i = ATOMIC_VAR_INIT(123);
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ASSERT_EQ(123, atomic_fetch_sub(&i, 1));
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ASSERT_EQ(122, atomic_fetch_sub_explicit(&i, 1, memory_order_relaxed));
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ASSERT_EQ(121, atomic_load(&i));
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}
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TEST(stdatomic, atomic_fetch_or) {
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atomic_int i = ATOMIC_VAR_INIT(0x100);
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ASSERT_EQ(0x100, atomic_fetch_or(&i, 0x020));
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ASSERT_EQ(0x120, atomic_fetch_or_explicit(&i, 0x003, memory_order_relaxed));
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ASSERT_EQ(0x123, atomic_load(&i));
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}
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TEST(stdatomic, atomic_fetch_xor) {
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atomic_int i = ATOMIC_VAR_INIT(0x100);
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ASSERT_EQ(0x100, atomic_fetch_xor(&i, 0x120));
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ASSERT_EQ(0x020, atomic_fetch_xor_explicit(&i, 0x103, memory_order_relaxed));
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ASSERT_EQ(0x123, atomic_load(&i));
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}
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TEST(stdatomic, atomic_fetch_and) {
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atomic_int i = ATOMIC_VAR_INIT(0x123);
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ASSERT_EQ(0x123, atomic_fetch_and(&i, 0x00f));
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ASSERT_EQ(0x003, atomic_fetch_and_explicit(&i, 0x2, memory_order_relaxed));
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ASSERT_EQ(0x002, atomic_load(&i));
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}
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#endif
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