0acb15ead6
This corrects an issue with mips32 Art on mips64r6 Android, where
Java ran slowly due to unintended use of kernel-trap emulation of
single-precision floating point registers. This also regressed all
Art tests due to an extra logcat line
WARNING: linker: Using FRE=1 mode to run "..."
When targeting mips32r6, Art generates modeless or FR=1 floating point
code, same as Android's own native mips32r6 modules. So the trapping was
unneeded. Linker was confusing Art-generated modules with those from
old NDK compilers, which do need that trapping mode.
This linker filename check may become unnecessary, if Art learns how to
generate .MIPS.abiflags segments in its generated elf-like codefiles.
Change-Id: I18069d1234960c680c5df739514da09015a7fdb6
348 lines
13 KiB
C++
348 lines
13 KiB
C++
/*
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* Copyright (C) 2015 The Android Open Source Project
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#if !defined(__LP64__) && __mips_isa_rev >= 5
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#include <sys/prctl.h>
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#if defined(PR_SET_FP_MODE)
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#error "remove following defs when avail in Android's kernel headers"
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#else
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#define PR_SET_FP_MODE 45
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#define PR_GET_FP_MODE 46
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#define PR_FP_MODE_FR (1 << 0)
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#define PR_FP_MODE_FRE (1 << 1)
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#endif
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#endif
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#include "linker.h"
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#include "linker_debug.h"
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#include "linker_phdr.h"
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#include "linker_relocs.h"
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#include "linker_reloc_iterators.h"
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#include "linker_sleb128.h"
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template bool soinfo::relocate<plain_reloc_iterator>(const VersionTracker& version_tracker,
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plain_reloc_iterator&& rel_iterator,
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const soinfo_list_t& global_group,
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const soinfo_list_t& local_group);
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template bool soinfo::relocate<packed_reloc_iterator<sleb128_decoder>>(
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const VersionTracker& version_tracker,
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packed_reloc_iterator<sleb128_decoder>&& rel_iterator,
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const soinfo_list_t& global_group,
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const soinfo_list_t& local_group);
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template <typename ElfRelIteratorT>
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bool soinfo::relocate(const VersionTracker& version_tracker,
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ElfRelIteratorT&& rel_iterator,
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const soinfo_list_t& global_group,
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const soinfo_list_t& local_group) {
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for (size_t idx = 0; rel_iterator.has_next(); ++idx) {
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const auto rel = rel_iterator.next();
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if (rel == nullptr) {
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return false;
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}
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ElfW(Word) type = ELFW(R_TYPE)(rel->r_info);
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ElfW(Word) sym = ELFW(R_SYM)(rel->r_info);
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ElfW(Addr) reloc = static_cast<ElfW(Addr)>(rel->r_offset + load_bias);
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ElfW(Addr) sym_addr = 0;
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const char* sym_name = nullptr;
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DEBUG("Processing '%s' relocation at index %zd", get_realpath(), idx);
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if (type == R_GENERIC_NONE) {
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continue;
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}
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const ElfW(Sym)* s = nullptr;
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soinfo* lsi = nullptr;
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if (sym != 0) {
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sym_name = get_string(symtab_[sym].st_name);
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const version_info* vi = nullptr;
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if (!lookup_version_info(version_tracker, sym, sym_name, &vi)) {
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return false;
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}
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if (!soinfo_do_lookup(this, sym_name, vi, &lsi, global_group, local_group, &s)) {
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return false;
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}
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if (s == nullptr) {
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// mips does not support relocation with weak-undefined symbols
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DL_ERR("cannot locate symbol \"%s\" referenced by \"%s\"...",
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sym_name, get_realpath());
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return false;
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} else {
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// We got a definition.
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sym_addr = lsi->resolve_symbol_address(s);
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}
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count_relocation(kRelocSymbol);
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}
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switch (type) {
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case R_MIPS_REL32:
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#if defined(__LP64__)
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// MIPS Elf64_Rel entries contain compound relocations
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// We only handle the R_MIPS_NONE|R_MIPS_64|R_MIPS_REL32 case
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if (ELF64_R_TYPE2(rel->r_info) != R_MIPS_64 ||
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ELF64_R_TYPE3(rel->r_info) != R_MIPS_NONE) {
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DL_ERR("Unexpected compound relocation type:%d type2:%d type3:%d @ %p (%zu)",
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type, static_cast<unsigned>(ELF64_R_TYPE2(rel->r_info)),
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static_cast<unsigned>(ELF64_R_TYPE3(rel->r_info)), rel, idx);
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return false;
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}
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#endif
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count_relocation(s == nullptr ? kRelocAbsolute : kRelocRelative);
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MARK(rel->r_offset);
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TRACE_TYPE(RELO, "RELO REL32 %08zx <- %08zx %s", static_cast<size_t>(reloc),
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static_cast<size_t>(sym_addr), sym_name ? sym_name : "*SECTIONHDR*");
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if (s != nullptr) {
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*reinterpret_cast<ElfW(Addr)*>(reloc) += sym_addr;
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} else {
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*reinterpret_cast<ElfW(Addr)*>(reloc) += load_bias;
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}
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break;
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default:
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DL_ERR("unknown reloc type %d @ %p (%zu)", type, rel, idx);
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return false;
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}
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}
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return true;
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}
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bool soinfo::mips_relocate_got(const VersionTracker& version_tracker,
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const soinfo_list_t& global_group,
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const soinfo_list_t& local_group) {
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ElfW(Addr)** got = plt_got_;
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if (got == nullptr) {
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return true;
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}
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// got[0] is the address of the lazy resolver function.
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// got[1] may be used for a GNU extension.
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// Set it to a recognizable address in case someone calls it (should be _rtld_bind_start).
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// FIXME: maybe this should be in a separate routine?
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if ((flags_ & FLAG_LINKER) == 0) {
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size_t g = 0;
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got[g++] = reinterpret_cast<ElfW(Addr)*>(0xdeadbeef);
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if (reinterpret_cast<intptr_t>(got[g]) < 0) {
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got[g++] = reinterpret_cast<ElfW(Addr)*>(0xdeadfeed);
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}
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// Relocate the local GOT entries.
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for (; g < mips_local_gotno_; g++) {
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got[g] = reinterpret_cast<ElfW(Addr)*>(reinterpret_cast<uintptr_t>(got[g]) + load_bias);
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}
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}
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// Now for the global GOT entries...
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got = plt_got_ + mips_local_gotno_;
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for (ElfW(Word) sym = mips_gotsym_; sym < mips_symtabno_; sym++, got++) {
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// This is an undefined reference... try to locate it.
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const ElfW(Sym)* local_sym = symtab_ + sym;
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const char* sym_name = get_string(local_sym->st_name);
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soinfo* lsi = nullptr;
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const ElfW(Sym)* s = nullptr;
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ElfW(Word) st_visibility = (local_sym->st_other & 0x3);
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if (st_visibility == STV_DEFAULT) {
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const version_info* vi = nullptr;
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if (!lookup_version_info(version_tracker, sym, sym_name, &vi)) {
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return false;
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}
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if (!soinfo_do_lookup(this, sym_name, vi, &lsi, global_group, local_group, &s)) {
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return false;
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}
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} else if (st_visibility == STV_PROTECTED) {
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if (local_sym->st_value == 0) {
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DL_ERR("%s: invalid symbol \"%s\" (PROTECTED/UNDEFINED) ",
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get_realpath(), sym_name);
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return false;
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}
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s = local_sym;
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lsi = this;
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} else {
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DL_ERR("%s: invalid symbol \"%s\" visibility: 0x%x",
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get_realpath(), sym_name, st_visibility);
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return false;
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}
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if (s == nullptr) {
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// We only allow an undefined symbol if this is a weak reference.
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if (ELF_ST_BIND(local_sym->st_info) != STB_WEAK) {
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DL_ERR("%s: cannot locate \"%s\"...", get_realpath(), sym_name);
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return false;
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}
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*got = 0;
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} else {
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// FIXME: is this sufficient?
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// For reference see NetBSD link loader
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// http://cvsweb.netbsd.org/bsdweb.cgi/src/libexec/ld.elf_so/arch/mips/mips_reloc.c?rev=1.53&content-type=text/x-cvsweb-markup
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*got = reinterpret_cast<ElfW(Addr)*>(lsi->resolve_symbol_address(s));
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}
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}
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return true;
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}
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#if !defined(__LP64__)
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// Checks for mips32's various floating point abis.
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// (Mips64 Android has a single floating point abi and doesn't need any checks)
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// Linux kernel has declarations similar to the following
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// in <linux>/arch/mips/include/asm/elf.h,
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// but that non-uapi internal header file will never be imported
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// into bionic's kernel headers.
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#define PT_MIPS_ABIFLAGS 0x70000003 // is .MIPS.abiflags segment
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struct mips_elf_abiflags_v0 {
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uint16_t version; // version of this structure
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uint8_t isa_level, isa_rev, gpr_size, cpr1_size, cpr2_size;
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uint8_t fp_abi; // mips32 ABI variants for floating point
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uint16_t isa_ext, ases, flags1, flags2;
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};
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// Bits of flags1:
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#define MIPS_AFL_FLAGS1_ODDSPREG 1 // Uses odd-numbered single-prec fp regs
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// Some values of fp_abi: via compiler flag:
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#define MIPS_ABI_FP_DOUBLE 1 // -mdouble-float
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#define MIPS_ABI_FP_XX 5 // -mfpxx
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#define MIPS_ABI_FP_64A 7 // -mips32r* -mfp64 -mno-odd-spreg
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#if __mips_isa_rev >= 5
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static bool mips_fre_mode_on = false; // have set FRE=1 mode for process
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#endif
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bool soinfo::mips_check_and_adjust_fp_modes() {
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mips_elf_abiflags_v0* abiflags = nullptr;
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int mips_fpabi;
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// Find soinfo's optional .MIPS.abiflags segment
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for (size_t i = 0; i<phnum; ++i) {
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const ElfW(Phdr)& ph = phdr[i];
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if (ph.p_type == PT_MIPS_ABIFLAGS) {
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if (ph.p_filesz < sizeof (mips_elf_abiflags_v0)) {
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DL_ERR("Corrupt PT_MIPS_ABIFLAGS header found \"%s\"", get_realpath());
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return false;
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}
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abiflags = reinterpret_cast<mips_elf_abiflags_v0*>(ph.p_vaddr + load_bias);
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break;
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}
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}
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// FP ABI-variant compatibility checks for MIPS o32 ABI
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if (abiflags == nullptr) {
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// Old compilers and some translators don't emit the new abiflags section.
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const char* filename = get_realpath();
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size_t len = strlen(filename);
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if (len > 4 && (strcmp(filename+len-4, ".dex") == 0 ||
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strcmp(filename+len-4, ".oat") == 0 )) {
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// Assume dex2oat is compatible with target
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mips_fpabi = MIPS_ABI_FP_XX;
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} else {
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// Old Android compilers used -mfp32 -mdouble-float -modd-spreg defaults,
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// ie FP32 aka DOUBLE, using FR=0 mode fpregs & odd single-prec fpregs
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mips_fpabi = MIPS_ABI_FP_DOUBLE;
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}
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} else {
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mips_fpabi = abiflags->fp_abi;
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if ( (abiflags->flags1 & MIPS_AFL_FLAGS1_ODDSPREG)
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&& (mips_fpabi == MIPS_ABI_FP_XX ||
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mips_fpabi == MIPS_ABI_FP_64A ) ) {
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// Android supports fewer cases than Linux
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DL_ERR("Unsupported odd-single-prec FloatPt reg uses in \"%s\"",
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get_realpath());
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return false;
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}
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}
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if (!(mips_fpabi == MIPS_ABI_FP_DOUBLE ||
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#if __mips_isa_rev >= 5
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mips_fpabi == MIPS_ABI_FP_64A ||
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#endif
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mips_fpabi == MIPS_ABI_FP_XX )) {
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DL_ERR("Unsupported MIPS32 FloatPt ABI %d found in \"%s\"",
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mips_fpabi, get_realpath());
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return false;
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}
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#if __mips_isa_rev >= 5
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// Adjust process's FR Emulation mode, if needed
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//
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// On Mips R5 & R6, Android runs continuously in FR=1 64bit-fpreg mode.
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// NDK mips32 apps compiled with old compilers generate FP32 code
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// which expects FR=0 32-bit fp registers.
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// NDK mips32 apps compiled with newer compilers generate modeless
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// FPXX code which runs on both FR=0 and FR=1 modes.
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// Android itself is compiled in FP64A which requires FR=1 mode.
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// FP32, FPXX, and FP64A all interlink okay, without dynamic FR mode
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// changes during calls. For details, see
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// http://dmz-portal.mips.com/wiki/MIPS_O32_ABI_-_FR0_and_FR1_Interlinking
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// Processes containing FR32 FR=0 code are run via kernel software assist,
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// which maps all odd-numbered single-precision reg refs onto the
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// upper half of the paired even-numbered double-precision reg.
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// FRE=1 triggers traps to the kernel's emulator on every single-precision
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// fp op (for both odd and even-numbered registers).
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// Turning on FRE=1 traps is done at most once per process, simultanously
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// for all threads of that process, when dlopen discovers FP32 code.
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// The kernel repacks threads' registers when FRE mode is turn on or off.
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// These asynchronous adjustments are wrong if any thread was executing
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// FPXX code using odd-numbered single-precision regs.
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// Current Android compilers default to the -mno-oddspreg option,
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// and this requirement is checked by Android's dlopen.
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// So FRE can always be safely turned on for FP32, anytime.
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// Deferred enhancement: Allow loading of odd-spreg FPXX modules.
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if (mips_fpabi == MIPS_ABI_FP_DOUBLE && !mips_fre_mode_on) {
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// Turn on FRE mode, which emulates mode-sensitive FR=0 code on FR=1
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// register files, by trapping to kernel on refs to single-precision regs
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if (prctl(PR_SET_FP_MODE, PR_FP_MODE_FR|PR_FP_MODE_FRE)) {
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DL_ERR("Kernel or cpu failed to set FRE mode required for running \"%s\"",
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get_realpath());
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return false;
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}
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DL_WARN("Using FRE=1 mode to run \"%s\"", get_realpath());
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mips_fre_mode_on = true; // Avoid future redundant mode-switch calls
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// FRE mode is never turned back off.
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// Deferred enhancement:
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// Reset FRE mode when dlclose() removes all FP32 modules
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}
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#else
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// Android runs continuously in FR=0 32bit-fpreg mode.
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#endif // __mips_isa_rev
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return true;
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}
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#endif // __LP64___
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