1924a5c92e
This patch adds support for AArch64 atomic operations. Some of the stubs use the lightweight store/load exclusive. Change-Id: Iaf704d048b2dc15bf08cf8e4f0c3ea9f2052fe13 Signed-off-by: Serban Constantinescu <serban.constantinescu@arm.com>
73 lines
2.3 KiB
C
73 lines
2.3 KiB
C
/*
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* Copyright (C) 2013 The Android Open Source Project
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef BIONIC_ATOMIC_AARCH64_H
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#define BIONIC_ATOMIC_AARCH64_H
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/* For ARMv8, we can use the 'dmb' instruction directly */
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__ATOMIC_INLINE__ void __bionic_memory_barrier(void) {
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__asm__ __volatile__ ( "dmb ish" : : : "memory" );
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}
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/* Compare-and-swap, without any explicit barriers. Note that this function
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* returns 0 on success, and 1 on failure. The opposite convention is typically
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* used on other platforms.
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*/
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__ATOMIC_INLINE__ int __bionic_cmpxchg(int32_t old_value, int32_t new_value, volatile int32_t* ptr) {
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int32_t tmp, oldval;
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__asm__ __volatile__ (
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"// atomic_cmpxchg\n"
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"1: ldaxr %w1, [%3]\n"
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" cmp %w1, %w4\n"
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" b.ne 2f\n"
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" stlxr %w0, %w5, [%3]\n"
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" cbnz %w0, 1b\n"
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"2:"
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: "=&r" (tmp), "=&r" (oldval), "+o"(*ptr)
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: "r" (ptr), "Ir" (old_value), "r" (new_value)
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: "cc");
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return oldval != old_value;
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}
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/* Swap, without any explicit barriers. */
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__ATOMIC_INLINE__ int32_t __bionic_swap(int32_t new_value, volatile int32_t* ptr) {
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int32_t prev, status;
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__asm__ __volatile__ (
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"// atomic_swap\n"
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"1: ldxr %w0, [%3]\n"
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" stxr %w1, %w4, [%3]\n"
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" cbnz %w1, 1b\n"
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: "=&r" (prev), "=&r" (status), "+o" (*ptr)
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: "r" (ptr), "r" (new_value)
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: "cc");
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return prev;
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}
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/* Atomic decrement, without explicit barriers. */
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__ATOMIC_INLINE__ int32_t __bionic_atomic_dec(volatile int32_t* ptr) {
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int32_t prev, tmp, status;
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__asm__ __volatile__ (
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"1: ldxr %w0, [%4]\n"
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" sub %w1, %w0, #1\n"
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" stxr %w2, %w1, [%4]\n"
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" cbnz %w2, 1b"
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: "=&r" (prev), "=&r" (tmp), "=&r" (status), "+m"(*ptr)
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: "r" (ptr)
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: "cc");
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return prev;
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}
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#endif /* BIONIC_ATOMICS_AARCH64_H */
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