Duane Sand dd37251c47 [MIPSR6] setjmp supports mips32r6 and FP64A/FPXX reg models ... Save and restore floating point registers via 64-bit load/stores when possible. Use assembler's builtin macro ops to generate pairs of 32-bit load/stores on Mips I cpus. Some cpus or FR modes have only 16 even-numbered dp fp regs. This is exposed by _MIPS_FPSET, defined by existing compilers. Change-Id: I7f617a3ffea8da41c402ef3a68ab32c91d3d7622		2014-07-23 13:57:30 -07:00
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bionic	[MIPSR6] setjmp supports mips32r6 and FP64A/FPXX reg models	2014-07-23 13:57:30 -07:00
include/machine	Clean up <machine/ieee.h>.	2014-04-16 16:31:17 -07:00
string	Unify our assembler macros.	2014-02-20 13:51:26 -08:00
syscalls	Add splice, tee, and vmsplice.	2014-06-24 19:03:31 -07:00
mips64.mk	Remove __memcmp16 from bionic.	2014-06-12 15:35:22 -07:00