c95eb57405
And fix the scripts so they stop letting trailing whitespace through. Change-Id: Ie109fbe1f63321e565ba0fa60fee8e9cf3a61cfc
99 lines
3.7 KiB
C
99 lines
3.7 KiB
C
/****************************************************************************
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****************************************************************************
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***
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*** This header was automatically generated from a Linux kernel header
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*** of the same name, to make information necessary for userspace to
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*** call into the kernel available to libc. It contains only constants,
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*** structures, and macros generated from the original header, and thus,
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*** contains no copyrightable information.
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***
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*** To edit the content of this header, modify the corresponding
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*** source file (e.g. under external/kernel-headers/original/) then
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*** run bionic/libc/kernel/tools/update_all.py
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***
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*** Any manual change here will be lost the next time this script will
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*** be run. You've been warned!
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***
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****************************************************************************
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****************************************************************************/
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#ifndef _ASM_DMA_H
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#define _ASM_DMA_H
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#include <linux/spinlock.h>
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#include <asm/io.h>
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#include <linux/delay.h>
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#ifdef HAVE_REALLY_SLOW_DMA_CONTROLLER
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#define dma_outb outb_p
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#else
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define dma_outb outb
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#endif
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#define dma_inb inb
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#define MAX_DMA_CHANNELS 8
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define MAX_DMA_ADDRESS (PAGE_OFFSET+0x1000000)
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#define IO_DMA1_BASE 0x00
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#define IO_DMA2_BASE 0xC0
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#define DMA1_CMD_REG 0x08
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define DMA1_STAT_REG 0x08
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#define DMA1_REQ_REG 0x09
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#define DMA1_MASK_REG 0x0A
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#define DMA1_MODE_REG 0x0B
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define DMA1_CLEAR_FF_REG 0x0C
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#define DMA1_TEMP_REG 0x0D
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#define DMA1_RESET_REG 0x0D
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#define DMA1_CLR_MASK_REG 0x0E
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define DMA1_MASK_ALL_REG 0x0F
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#define DMA2_CMD_REG 0xD0
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#define DMA2_STAT_REG 0xD0
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#define DMA2_REQ_REG 0xD2
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define DMA2_MASK_REG 0xD4
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#define DMA2_MODE_REG 0xD6
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#define DMA2_CLEAR_FF_REG 0xD8
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#define DMA2_TEMP_REG 0xDA
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define DMA2_RESET_REG 0xDA
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#define DMA2_CLR_MASK_REG 0xDC
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#define DMA2_MASK_ALL_REG 0xDE
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#define DMA_ADDR_0 0x00
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define DMA_ADDR_1 0x02
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#define DMA_ADDR_2 0x04
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#define DMA_ADDR_3 0x06
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#define DMA_ADDR_4 0xC0
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define DMA_ADDR_5 0xC4
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#define DMA_ADDR_6 0xC8
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#define DMA_ADDR_7 0xCC
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#define DMA_CNT_0 0x01
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define DMA_CNT_1 0x03
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#define DMA_CNT_2 0x05
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#define DMA_CNT_3 0x07
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#define DMA_CNT_4 0xC2
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define DMA_CNT_5 0xC6
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#define DMA_CNT_6 0xCA
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#define DMA_CNT_7 0xCE
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#define DMA_PAGE_0 0x87
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define DMA_PAGE_1 0x83
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#define DMA_PAGE_2 0x81
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#define DMA_PAGE_3 0x82
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#define DMA_PAGE_5 0x8B
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define DMA_PAGE_6 0x89
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#define DMA_PAGE_7 0x8A
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#define DMA_MODE_READ 0x44
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#define DMA_MODE_WRITE 0x48
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define DMA_MODE_CASCADE 0xC0
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#define DMA_AUTOINIT 0x10
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#define isa_dma_bridge_buggy (0)
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#endif
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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