82fa43febc
libc/kernel/tools/update_all.py script. This patch ignores any changes to libc/kernel directory not related to MIPS architecture. Change-Id: I2c9e461dccb7c33eb4420be2db1a562f45137c8d Signed-off-by: Raghu Gandham <raghu@mips.com> Signed-off-by: Chris Dearman <chris@mips.com>
62 lines
3.3 KiB
C
62 lines
3.3 KiB
C
/****************************************************************************
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****************************************************************************
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***
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*** This header was automatically generated from a Linux kernel header
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*** of the same name, to make information necessary for userspace to
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*** call into the kernel available to libc. It contains only constants,
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*** structures, and macros generated from the original header, and thus,
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*** contains no copyrightable information.
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***
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*** To edit the content of this header, modify the corresponding
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*** source file (e.g. under external/kernel-headers/original/) then
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*** run bionic/libc/kernel/tools/update_all.py
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***
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*** Any manual change here will be lost the next time this script will
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*** be run. You've been warned!
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***
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****************************************************************************
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****************************************************************************/
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#ifndef _ASM_IRQ_GT641XX_H
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#define _ASM_IRQ_GT641XX_H
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#ifndef GT641XX_IRQ_BASE
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#define GT641XX_IRQ_BASE 8
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#endif
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#define GT641XX_MEMORY_OUT_OF_RANGE_IRQ (GT641XX_IRQ_BASE + 1)
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#define GT641XX_DMA_OUT_OF_RANGE_IRQ (GT641XX_IRQ_BASE + 2)
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#define GT641XX_CPU_ACCESS_OUT_OF_RANGE_IRQ (GT641XX_IRQ_BASE + 3)
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define GT641XX_DMA0_IRQ (GT641XX_IRQ_BASE + 4)
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#define GT641XX_DMA1_IRQ (GT641XX_IRQ_BASE + 5)
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#define GT641XX_DMA2_IRQ (GT641XX_IRQ_BASE + 6)
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#define GT641XX_DMA3_IRQ (GT641XX_IRQ_BASE + 7)
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define GT641XX_TIMER0_IRQ (GT641XX_IRQ_BASE + 8)
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#define GT641XX_TIMER1_IRQ (GT641XX_IRQ_BASE + 9)
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#define GT641XX_TIMER2_IRQ (GT641XX_IRQ_BASE + 10)
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#define GT641XX_TIMER3_IRQ (GT641XX_IRQ_BASE + 11)
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define GT641XX_PCI_0_MASTER_READ_ERROR_IRQ (GT641XX_IRQ_BASE + 12)
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#define GT641XX_PCI_0_SLAVE_WRITE_ERROR_IRQ (GT641XX_IRQ_BASE + 13)
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#define GT641XX_PCI_0_MASTER_WRITE_ERROR_IRQ (GT641XX_IRQ_BASE + 14)
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#define GT641XX_PCI_0_SLAVE_READ_ERROR_IRQ (GT641XX_IRQ_BASE + 15)
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define GT641XX_PCI_0_ADDRESS_ERROR_IRQ (GT641XX_IRQ_BASE + 16)
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#define GT641XX_MEMORY_ERROR_IRQ (GT641XX_IRQ_BASE + 17)
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#define GT641XX_PCI_0_MASTER_ABORT_IRQ (GT641XX_IRQ_BASE + 18)
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#define GT641XX_PCI_0_TARGET_ABORT_IRQ (GT641XX_IRQ_BASE + 19)
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define GT641XX_PCI_0_RETRY_TIMEOUT_IRQ (GT641XX_IRQ_BASE + 20)
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#define GT641XX_CPU_INT0_IRQ (GT641XX_IRQ_BASE + 21)
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#define GT641XX_CPU_INT1_IRQ (GT641XX_IRQ_BASE + 22)
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#define GT641XX_CPU_INT2_IRQ (GT641XX_IRQ_BASE + 23)
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define GT641XX_CPU_INT3_IRQ (GT641XX_IRQ_BASE + 24)
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#define GT641XX_CPU_INT4_IRQ (GT641XX_IRQ_BASE + 25)
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#define GT641XX_PCI_INT0_IRQ (GT641XX_IRQ_BASE + 26)
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#define GT641XX_PCI_INT1_IRQ (GT641XX_IRQ_BASE + 27)
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define GT641XX_PCI_INT2_IRQ (GT641XX_IRQ_BASE + 28)
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#define GT641XX_PCI_INT3_IRQ (GT641XX_IRQ_BASE + 29)
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#endif
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