d7db594b8d
Replace the tokenizer in cpp.py with libclang. Bug: 18937958 Change-Id: I27630904c6d2849418cd5ca3d3c612ec3078686d
186 lines
8.5 KiB
C
186 lines
8.5 KiB
C
/****************************************************************************
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****************************************************************************
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***
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*** This header was automatically generated from a Linux kernel header
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*** of the same name, to make information necessary for userspace to
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*** call into the kernel available to libc. It contains only constants,
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*** structures, and macros generated from the original header, and thus,
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*** contains no copyrightable information.
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***
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*** To edit the content of this header, modify the corresponding
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*** source file (e.g. under external/kernel-headers/original/) then
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*** run bionic/libc/kernel/tools/update_all.py
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***
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*** Any manual change here will be lost the next time this script will
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*** be run. You've been warned!
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***
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****************************************************************************
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****************************************************************************/
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#ifndef __ARM_KVM_H__
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#define __ARM_KVM_H__
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#include <linux/types.h>
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#include <linux/psci.h>
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#include <asm/ptrace.h>
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#define __KVM_HAVE_GUEST_DEBUG
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#define __KVM_HAVE_IRQ_LINE
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#define __KVM_HAVE_READONLY_MEM
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define KVM_REG_SIZE(id) (1U << (((id) & KVM_REG_SIZE_MASK) >> KVM_REG_SIZE_SHIFT))
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#define KVM_ARM_SVC_sp svc_regs[0]
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#define KVM_ARM_SVC_lr svc_regs[1]
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#define KVM_ARM_SVC_spsr svc_regs[2]
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define KVM_ARM_ABT_sp abt_regs[0]
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#define KVM_ARM_ABT_lr abt_regs[1]
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#define KVM_ARM_ABT_spsr abt_regs[2]
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#define KVM_ARM_UND_sp und_regs[0]
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define KVM_ARM_UND_lr und_regs[1]
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#define KVM_ARM_UND_spsr und_regs[2]
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#define KVM_ARM_IRQ_sp irq_regs[0]
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#define KVM_ARM_IRQ_lr irq_regs[1]
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define KVM_ARM_IRQ_spsr irq_regs[2]
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#define KVM_ARM_FIQ_r8 fiq_regs[0]
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#define KVM_ARM_FIQ_r9 fiq_regs[1]
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#define KVM_ARM_FIQ_r10 fiq_regs[2]
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define KVM_ARM_FIQ_fp fiq_regs[3]
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#define KVM_ARM_FIQ_ip fiq_regs[4]
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#define KVM_ARM_FIQ_sp fiq_regs[5]
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#define KVM_ARM_FIQ_lr fiq_regs[6]
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define KVM_ARM_FIQ_spsr fiq_regs[7]
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struct kvm_regs {
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struct pt_regs usr_regs;
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unsigned long svc_regs[3];
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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unsigned long abt_regs[3];
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unsigned long und_regs[3];
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unsigned long irq_regs[3];
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unsigned long fiq_regs[8];
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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};
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#define KVM_ARM_TARGET_CORTEX_A15 0
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#define KVM_ARM_TARGET_CORTEX_A7 1
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#define KVM_ARM_NUM_TARGETS 2
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define KVM_ARM_DEVICE_TYPE_SHIFT 0
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#define KVM_ARM_DEVICE_TYPE_MASK (0xffff << KVM_ARM_DEVICE_TYPE_SHIFT)
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#define KVM_ARM_DEVICE_ID_SHIFT 16
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#define KVM_ARM_DEVICE_ID_MASK (0xffff << KVM_ARM_DEVICE_ID_SHIFT)
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define KVM_ARM_DEVICE_VGIC_V2 0
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#define KVM_VGIC_V2_ADDR_TYPE_DIST 0
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#define KVM_VGIC_V2_ADDR_TYPE_CPU 1
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#define KVM_VGIC_V2_DIST_SIZE 0x1000
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define KVM_VGIC_V2_CPU_SIZE 0x2000
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#define KVM_ARM_VCPU_POWER_OFF 0
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#define KVM_ARM_VCPU_PSCI_0_2 1
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struct kvm_vcpu_init {
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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__u32 target;
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__u32 features[7];
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};
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struct kvm_sregs {
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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};
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struct kvm_fpu {
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};
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struct kvm_guest_debug_arch {
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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};
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struct kvm_debug_exit_arch {
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};
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struct kvm_sync_regs {
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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};
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struct kvm_arch_memory_slot {
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};
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#define KVM_REG_ARM_COPROC_MASK 0x000000000FFF0000
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define KVM_REG_ARM_COPROC_SHIFT 16
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#define KVM_REG_ARM_32_OPC2_MASK 0x0000000000000007
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#define KVM_REG_ARM_32_OPC2_SHIFT 0
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#define KVM_REG_ARM_OPC1_MASK 0x0000000000000078
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define KVM_REG_ARM_OPC1_SHIFT 3
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#define KVM_REG_ARM_CRM_MASK 0x0000000000000780
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#define KVM_REG_ARM_CRM_SHIFT 7
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#define KVM_REG_ARM_32_CRN_MASK 0x0000000000007800
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define KVM_REG_ARM_32_CRN_SHIFT 11
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#define ARM_CP15_REG_SHIFT_MASK(x,n) (((x) << KVM_REG_ARM_ ##n ##_SHIFT) & KVM_REG_ARM_ ##n ##_MASK)
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#define __ARM_CP15_REG(op1,crn,crm,op2) (KVM_REG_ARM | (15 << KVM_REG_ARM_COPROC_SHIFT) | ARM_CP15_REG_SHIFT_MASK(op1, OPC1) | ARM_CP15_REG_SHIFT_MASK(crn, 32_CRN) | ARM_CP15_REG_SHIFT_MASK(crm, CRM) | ARM_CP15_REG_SHIFT_MASK(op2, 32_OPC2))
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#define ARM_CP15_REG32(...) (__ARM_CP15_REG(__VA_ARGS__) | KVM_REG_SIZE_U32)
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define __ARM_CP15_REG64(op1,crm) (__ARM_CP15_REG(op1, 0, crm, 0) | KVM_REG_SIZE_U64)
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#define ARM_CP15_REG64(...) __ARM_CP15_REG64(__VA_ARGS__)
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#define KVM_REG_ARM_TIMER_CTL ARM_CP15_REG32(0, 14, 3, 1)
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#define KVM_REG_ARM_TIMER_CNT ARM_CP15_REG64(1, 14)
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define KVM_REG_ARM_TIMER_CVAL ARM_CP15_REG64(3, 14)
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#define KVM_REG_ARM_CORE (0x0010 << KVM_REG_ARM_COPROC_SHIFT)
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#define KVM_REG_ARM_CORE_REG(name) (offsetof(struct kvm_regs, name) / 4)
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#define KVM_REG_ARM_DEMUX (0x0011 << KVM_REG_ARM_COPROC_SHIFT)
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define KVM_REG_ARM_DEMUX_ID_MASK 0x000000000000FF00
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#define KVM_REG_ARM_DEMUX_ID_SHIFT 8
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#define KVM_REG_ARM_DEMUX_ID_CCSIDR (0x00 << KVM_REG_ARM_DEMUX_ID_SHIFT)
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#define KVM_REG_ARM_DEMUX_VAL_MASK 0x00000000000000FF
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define KVM_REG_ARM_DEMUX_VAL_SHIFT 0
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#define KVM_REG_ARM_VFP (0x0012 << KVM_REG_ARM_COPROC_SHIFT)
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#define KVM_REG_ARM_VFP_MASK 0x000000000000FFFF
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#define KVM_REG_ARM_VFP_BASE_REG 0x0
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define KVM_REG_ARM_VFP_FPSID 0x1000
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#define KVM_REG_ARM_VFP_FPSCR 0x1001
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#define KVM_REG_ARM_VFP_MVFR1 0x1006
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#define KVM_REG_ARM_VFP_MVFR0 0x1007
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define KVM_REG_ARM_VFP_FPEXC 0x1008
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#define KVM_REG_ARM_VFP_FPINST 0x1009
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#define KVM_REG_ARM_VFP_FPINST2 0x100A
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#define KVM_DEV_ARM_VGIC_GRP_ADDR 0
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define KVM_DEV_ARM_VGIC_GRP_DIST_REGS 1
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#define KVM_DEV_ARM_VGIC_GRP_CPU_REGS 2
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#define KVM_DEV_ARM_VGIC_CPUID_SHIFT 32
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#define KVM_DEV_ARM_VGIC_CPUID_MASK (0xffULL << KVM_DEV_ARM_VGIC_CPUID_SHIFT)
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define KVM_DEV_ARM_VGIC_OFFSET_SHIFT 0
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#define KVM_DEV_ARM_VGIC_OFFSET_MASK (0xffffffffULL << KVM_DEV_ARM_VGIC_OFFSET_SHIFT)
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#define KVM_DEV_ARM_VGIC_GRP_NR_IRQS 3
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#define KVM_ARM_IRQ_TYPE_SHIFT 24
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define KVM_ARM_IRQ_TYPE_MASK 0xff
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#define KVM_ARM_IRQ_VCPU_SHIFT 16
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#define KVM_ARM_IRQ_VCPU_MASK 0xff
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#define KVM_ARM_IRQ_NUM_SHIFT 0
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define KVM_ARM_IRQ_NUM_MASK 0xffff
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#define KVM_ARM_IRQ_TYPE_CPU 0
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#define KVM_ARM_IRQ_TYPE_SPI 1
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#define KVM_ARM_IRQ_TYPE_PPI 2
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define KVM_ARM_IRQ_CPU_IRQ 0
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#define KVM_ARM_IRQ_CPU_FIQ 1
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#define KVM_ARM_IRQ_GIC_MAX 127
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#define KVM_PSCI_FN_BASE 0x95c1ba5e
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define KVM_PSCI_FN(n) (KVM_PSCI_FN_BASE + (n))
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#define KVM_PSCI_FN_CPU_SUSPEND KVM_PSCI_FN(0)
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#define KVM_PSCI_FN_CPU_OFF KVM_PSCI_FN(1)
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#define KVM_PSCI_FN_CPU_ON KVM_PSCI_FN(2)
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define KVM_PSCI_FN_MIGRATE KVM_PSCI_FN(3)
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#define KVM_PSCI_RET_SUCCESS PSCI_RET_SUCCESS
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#define KVM_PSCI_RET_NI PSCI_RET_NOT_SUPPORTED
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#define KVM_PSCI_RET_INVAL PSCI_RET_INVALID_PARAMS
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define KVM_PSCI_RET_DENIED PSCI_RET_DENIED
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#endif
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