e210488e0d
This is the first patch out of a series of patches that add support for
AArch64, the new 64bit execution state of the ARMv8 Architecture. The
patches add support for LP64 programming model.
The patch adds:
* "arch-aarch64" to the architecture directories.
* "arch-aarch64/include" - headers used by libc
* "arch-aarch64/bionic":
- crtbegin, crtend support;
- aarch64 specific syscall stubs;
- setjmp, clone, vfork assembly files.
Change-Id: If72b859f81928d03ad05d4ccfcb54c2f5dbf99a5
Signed-off-by: Serban Constantinescu <serban.constantinescu@arm.com>
192 lines
5.5 KiB
C
192 lines
5.5 KiB
C
/* $OpenBSD: ieee.h,v 1.1 2004/02/01 05:09:49 drahn Exp $ */
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/* $NetBSD: ieee.h,v 1.2 2001/02/21 17:43:50 bjh21 Exp $ */
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/*
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* Copyright (c) 1992, 1993
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* The Regents of the University of California. All rights reserved.
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*
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* This software was developed by the Computer Systems Engineering group
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* at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
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* contributed to Berkeley.
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*
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* All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Lawrence Berkeley Laboratory.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @(#)ieee.h 8.1 (Berkeley) 6/11/93
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*/
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/*
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* ieee.h defines the machine-dependent layout of the machine's IEEE
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* floating point.
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*/
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/*
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* Define the number of bits in each fraction and exponent.
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*
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* k k+1
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* Note that 1.0 x 2 == 0.1 x 2 and that denorms are represented
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*
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* (-exp_bias+1)
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* as fractions that look like 0.fffff x 2 . This means that
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*
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* -126
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* the number 0.10000 x 2 , for instance, is the same as the normalized
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*
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* -127 -128
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* float 1.0 x 2 . Thus, to represent 2 , we need one leading zero
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*
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* -129
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* in the fraction; to represent 2 , we need two, and so on. This
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*
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* (-exp_bias-fracbits+1)
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* implies that the smallest denormalized number is 2
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*
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* for whichever format we are talking about: for single precision, for
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*
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* -126 -149
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* instance, we get .00000000000000000000001 x 2 , or 1.0 x 2 , and
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*
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* -149 == -127 - 23 + 1.
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*/
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/*
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* The ARM has two sets of FP data formats. The FPA supports 32-bit, 64-bit
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* and 96-bit IEEE formats, with the words in big-endian order. VFP supports
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* 32-bin and 64-bit IEEE formats with the words in the CPU's native byte
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* order.
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*
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* The FPA also has two packed decimal formats, but we ignore them here.
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*/
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#define SNG_EXPBITS 8
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#define SNG_FRACBITS 23
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#define DBL_EXPBITS 11
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#define DBL_FRACBITS 52
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#ifndef __VFP_FP__
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#define E80_EXPBITS 15
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#define E80_FRACBITS 64
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#define EXT_EXPBITS 15
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#define EXT_FRACBITS 112
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#endif
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struct ieee_single {
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u_int sng_frac:23;
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u_int sng_exponent:8;
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u_int sng_sign:1;
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};
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#ifdef __VFP_FP__
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struct ieee_double {
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#ifdef __AARCH64EB__
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u_int dbl_sign:1;
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u_int dbl_exp:11;
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u_int dbl_frach:20;
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u_int dbl_fracl;
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#else /* !__AARCH64EB__ */
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u_int dbl_fracl;
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u_int dbl_frach:20;
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u_int dbl_exp:11;
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u_int dbl_sign:1;
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#endif /* !__AARCH64EB__ */
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};
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#else /* !__VFP_FP__ */
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struct ieee_double {
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u_int dbl_frach:20;
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u_int dbl_exp:11;
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u_int dbl_sign:1;
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u_int dbl_fracl;
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};
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union ieee_double_u {
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double dblu_d;
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struct ieee_double dblu_dbl;
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};
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struct ieee_e80 {
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u_int e80_exp:15;
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u_int e80_zero:16;
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u_int e80_sign:1;
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u_int e80_frach:31;
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u_int e80_j:1;
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u_int e80_fracl;
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};
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struct ieee_ext {
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u_int ext_frach:16;
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u_int ext_exp:15;
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u_int ext_sign:1;
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u_int ext_frachm;
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u_int ext_fraclm;
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u_int ext_fracl;
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};
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#endif /* !__VFP_FP__ */
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/*
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* Floats whose exponent is in [1..INFNAN) (of whatever type) are
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* `normal'. Floats whose exponent is INFNAN are either Inf or NaN.
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* Floats whose exponent is zero are either zero (iff all fraction
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* bits are zero) or subnormal values.
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*
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* A NaN is a `signalling NaN' if its QUIETNAN bit is clear in its
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* high fraction; if the bit is set, it is a `quiet NaN'.
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*/
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#define SNG_EXP_INFNAN 255
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#define DBL_EXP_INFNAN 2047
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#ifndef __VFP_FP__
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#define E80_EXP_INFNAN 32767
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#define EXT_EXP_INFNAN 32767
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#endif /* !__VFP_FP__ */
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#if 0
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#define SNG_QUIETNAN (1 << 22)
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#define DBL_QUIETNAN (1 << 19)
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#ifndef __VFP_FP__
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#define E80_QUIETNAN (1 << 15)
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#define EXT_QUIETNAN (1 << 15)
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#endif /* !__VFP_FP__ */
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#endif
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/*
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* Exponent biases.
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*/
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#define SNG_EXP_BIAS 127
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#define DBL_EXP_BIAS 1023
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#ifndef __VFP_FP__
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#define E80_EXP_BIAS 16383
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#define EXT_EXP_BIAS 16383
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#endif /* !__VFP_FP__ */
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