e210488e0d
This is the first patch out of a series of patches that add support for
AArch64, the new 64bit execution state of the ARMv8 Architecture. The
patches add support for LP64 programming model.
The patch adds:
* "arch-aarch64" to the architecture directories.
* "arch-aarch64/include" - headers used by libc
* "arch-aarch64/bionic":
- crtbegin, crtend support;
- aarch64 specific syscall stubs;
- setjmp, clone, vfork assembly files.
Change-Id: If72b859f81928d03ad05d4ccfcb54c2f5dbf99a5
Signed-off-by: Serban Constantinescu <serban.constantinescu@arm.com>
74 lines
2.9 KiB
C
74 lines
2.9 KiB
C
/*
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* Copyright (C) 2013 The Android Open Source Project
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* machine/setjmp.h: machine dependent setjmp-related information.
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*/
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/* _JBLEN is the size of a jmp_buf in longs(64bit on AArch64) */
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#define _JBLEN 32
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/* According to AARCH64 PCS document we need to save the following
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* registers:
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*
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* Core x19 - x30, sp (see section 5.1.1)
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* VFP d8 - d15 (see section 5.1.2)
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*
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* NOTE: All the registers saved here will have 64bit vales (except FPSR).
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* AAPCS mandates that the higher part of q registers does not need to
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* be saveved by the callee.
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*/
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/* The structure of jmp_buf for AArch64:
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*
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* NOTE: _JBLEN is the size of jmp_buf in longs(64bit on AArch64)! The table
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* below computes the offsets in words(32bit).
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*
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* word name description
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* 0 magic magic number
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* 1 sigmask signal mask (not used with _setjmp / _longjmp)
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* 2 core_base base of core registers (x19-x30, sp)
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* 28 float_base base of float registers (d8-d15)
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* 44 reserved reserved entries (room to grow)
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* 64
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*
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*
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* NOTE: The instructions that load/store core/vfp registers expect 8-byte
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* alignment. Contrary to the previous setjmp header for ARM we do not
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* need to save status/control registers for VFP (it is not a
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* requirement for setjmp).
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*/
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#define _JB_MAGIC 0
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#define _JB_SIGMASK (_JB_MAGIC+1)
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#define _JB_CORE_BASE (_JB_SIGMASK+1)
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#define _JB_FLOAT_BASE (_JB_CORE_BASE + (31-19+1)*2)
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#define _JB_MAGIC__SETJMP 0x53657200
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#define _JB_MAGIC_SETJMP 0x53657201
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