4b29af0a1b
This reverts commit 94a85f6636
There is a smoke test failure for Prime but Crespo/Stingray are fine. Will revert the change for now until further investigation is made.
108 lines
4.5 KiB
C
108 lines
4.5 KiB
C
/****************************************************************************
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****************************************************************************
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***
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*** This header was automatically generated from a Linux kernel header
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*** of the same name, to make information necessary for userspace to
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*** call into the kernel available to libc. It contains only constants,
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*** structures, and macros generated from the original header, and thus,
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*** contains no copyrightable information.
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***
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****************************************************************************
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****************************************************************************/
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#ifndef _ASMARM_CACHEFLUSH_H
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#define _ASMARM_CACHEFLUSH_H
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#include <linux/sched.h>
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#include <linux/mm.h>
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#include <asm/glue.h>
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#include <asm/shmparam.h>
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#define CACHE_COLOUR(vaddr) ((vaddr & (SHMLBA - 1)) >> PAGE_SHIFT)
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#undef _CACHE
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#undef MULTI_CACHE
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#if !defined(_CACHE) && !defined(MULTI_CACHE)
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#error Unknown cache maintainence model
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#endif
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#define PG_dcache_dirty PG_arch_1
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struct cpu_cache_fns {
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void (*flush_kern_all)(void);
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void (*flush_user_all)(void);
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void (*flush_user_range)(unsigned long, unsigned long, unsigned int);
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void (*coherent_kern_range)(unsigned long, unsigned long);
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void (*coherent_user_range)(unsigned long, unsigned long);
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void (*flush_kern_dcache_page)(void *);
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void (*dma_inv_range)(unsigned long, unsigned long);
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void (*dma_clean_range)(unsigned long, unsigned long);
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void (*dma_flush_range)(unsigned long, unsigned long);
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};
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#ifdef MULTI_CACHE
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#define __cpuc_flush_kern_all cpu_cache.flush_kern_all
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#define __cpuc_flush_user_all cpu_cache.flush_user_all
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#define __cpuc_flush_user_range cpu_cache.flush_user_range
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#define __cpuc_coherent_kern_range cpu_cache.coherent_kern_range
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#define __cpuc_coherent_user_range cpu_cache.coherent_user_range
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#define __cpuc_flush_dcache_page cpu_cache.flush_kern_dcache_page
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#define dmac_inv_range cpu_cache.dma_inv_range
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#define dmac_clean_range cpu_cache.dma_clean_range
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#define dmac_flush_range cpu_cache.dma_flush_range
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#else
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#define __cpuc_flush_kern_all __glue(_CACHE,_flush_kern_cache_all)
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#define __cpuc_flush_user_all __glue(_CACHE,_flush_user_cache_all)
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#define __cpuc_flush_user_range __glue(_CACHE,_flush_user_cache_range)
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#define __cpuc_coherent_kern_range __glue(_CACHE,_coherent_kern_range)
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#define __cpuc_coherent_user_range __glue(_CACHE,_coherent_user_range)
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#define __cpuc_flush_dcache_page __glue(_CACHE,_flush_kern_dcache_page)
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#define dmac_inv_range __glue(_CACHE,_dma_inv_range)
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#define dmac_clean_range __glue(_CACHE,_dma_clean_range)
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#define dmac_flush_range __glue(_CACHE,_dma_flush_range)
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#endif
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#define flush_cache_vmap(start, end) flush_cache_all()
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#define flush_cache_vunmap(start, end) flush_cache_all()
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#define copy_to_user_page(vma, page, vaddr, dst, src, len) do { memcpy(dst, src, len); flush_ptrace_access(vma, page, vaddr, dst, len, 1); } while (0)
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#define copy_from_user_page(vma, page, vaddr, dst, src, len) do { memcpy(dst, src, len); } while (0)
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#define flush_cache_all() __cpuc_flush_kern_all()
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#define flush_cache_user_range(vma,start,end) __cpuc_coherent_user_range((start) & PAGE_MASK, PAGE_ALIGN(end))
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#define flush_icache_range(s,e) __cpuc_coherent_kern_range(s,e)
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#define clean_dcache_area(start,size) cpu_dcache_clean_area(start, size)
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#define flush_dcache_mmap_lock(mapping) write_lock_irq(&(mapping)->tree_lock)
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#define flush_dcache_mmap_unlock(mapping) write_unlock_irq(&(mapping)->tree_lock)
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#define flush_icache_user_range(vma,page,addr,len) flush_dcache_page(page)
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#define flush_icache_page(vma,page) do { } while (0)
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#define __cacheid_present(val) (val != read_cpuid(CPUID_ID))
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#define __cacheid_vivt(val) ((val & (15 << 25)) != (14 << 25))
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#define __cacheid_vipt(val) ((val & (15 << 25)) == (14 << 25))
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#define __cacheid_vipt_nonaliasing(val) ((val & (15 << 25 | 1 << 23)) == (14 << 25))
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#define __cacheid_vipt_aliasing(val) ((val & (15 << 25 | 1 << 23)) == (14 << 25 | 1 << 23))
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#define cache_is_vivt() ({ unsigned int __val = read_cpuid(CPUID_CACHETYPE); (!__cacheid_present(__val)) || __cacheid_vivt(__val); })
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#define cache_is_vipt() ({ unsigned int __val = read_cpuid(CPUID_CACHETYPE); __cacheid_present(__val) && __cacheid_vipt(__val); })
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#define cache_is_vipt_nonaliasing() ({ unsigned int __val = read_cpuid(CPUID_CACHETYPE); __cacheid_present(__val) && __cacheid_vipt_nonaliasing(__val); })
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#define cache_is_vipt_aliasing() ({ unsigned int __val = read_cpuid(CPUID_CACHETYPE); __cacheid_present(__val) && __cacheid_vipt_aliasing(__val); })
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#endif
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