392 lines
7.2 KiB
C
392 lines
7.2 KiB
C
/****************************************************************************
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****************************************************************************
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***
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*** This header was automatically generated from a Linux kernel header
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*** of the same name, to make information necessary for userspace to
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*** call into the kernel available to libc. It contains only constants,
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*** structures, and macros generated from the original header, and thus,
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*** contains no copyrightable information.
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***
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****************************************************************************
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****************************************************************************/
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#ifndef __ASM_ARCH_MUX_H
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#define __ASM_ARCH_MUX_H
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#define PU_PD_SEL_NA 0
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#define PULL_DWN_CTRL_NA 0
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#define MUX_REG(reg, mode_offset, mode) .mux_reg = FUNC_MUX_CTRL_##reg, .mask_offset = mode_offset, .mask = mode,
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#define PULL_REG(reg, bit, status) .pull_reg = PULL_DWN_CTRL_##reg, .pull_bit = bit, .pull_val = status,
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#define PU_PD_REG(reg, status) .pu_pd_reg = PU_PD_SEL_##reg, .pu_pd_val = status,
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#define MUX_REG_730(reg, mode_offset, mode) .mux_reg = OMAP730_IO_CONF_##reg, .mask_offset = mode_offset, .mask = mode,
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#define PULL_REG_730(reg, bit, status) .pull_reg = OMAP730_IO_CONF_##reg, .pull_bit = bit, .pull_val = status,
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#define MUX_CFG(desc, mux_reg, mode_offset, mode, pull_reg, pull_bit, pull_status, pu_pd_reg, pu_pd_status, debug_status) { .name = desc, .debug = debug_status, MUX_REG(mux_reg, mode_offset, mode) PULL_REG(pull_reg, pull_bit, !pull_status) PU_PD_REG(pu_pd_reg, pu_pd_status) },
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#define MUX_CFG_730(desc, mux_reg, mode_offset, mode, pull_bit, pull_status, debug_status) { .name = desc, .debug = debug_status, MUX_REG_730(mux_reg, mode_offset, mode) PULL_REG_730(mux_reg, pull_bit, pull_status) PU_PD_REG(NA, 0) },
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#define MUX_CFG_24XX(desc, reg_offset, mode, pull_en, pull_mode, dbg) { .name = desc, .debug = dbg, .mux_reg = reg_offset, .mask = mode, .pull_val = pull_en, .pu_pd_val = pull_mode, },
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#define PULL_DISABLED 0
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#define PULL_ENABLED 1
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#define PULL_DOWN 0
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#define PULL_UP 1
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struct pin_config {
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char *name;
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unsigned char busy;
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unsigned char debug;
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const char *mux_reg_name;
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const unsigned int mux_reg;
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const unsigned char mask_offset;
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const unsigned char mask;
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const char *pull_name;
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const unsigned int pull_reg;
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const unsigned char pull_val;
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const unsigned char pull_bit;
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const char *pu_pd_name;
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const unsigned int pu_pd_reg;
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const unsigned char pu_pd_val;
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};
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enum omap730_index {
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E2_730_KBR0,
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J7_730_KBR1,
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E1_730_KBR2,
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F3_730_KBR3,
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D2_730_KBR4,
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AA20_730_KBR5,
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V17_730_KBR6,
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C2_730_KBC0,
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D3_730_KBC1,
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E4_730_KBC2,
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F4_730_KBC3,
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E3_730_KBC4,
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AA17_730_USB_DM,
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W16_730_USB_PU_EN,
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W17_730_USB_VBUSI,
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V19_730_GPIO_15,
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M19_730_GPIO_77,
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C21_730_GPIO_121_122,
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K19_730_GPIO_126,
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K15_730_GPIO_127,
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P15_730_GPIO_16_17,
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M15_730_GPIO_83,
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N20_730_GPIO_82,
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N18_730_GPIO_81,
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N19_730_GPIO_80,
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L15_730_GPIO_76,
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UART1_CTS_RTS,
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OMAP_730_GPIOS_42_43,
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UART1_TX_RX,
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OMAP_730_GPIOS_40_41,
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UART1_USB_RX_TX,
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UART1_USB_RTS,
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UART1_USB_CTS
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};
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enum omap1xxx_index {
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UART1_TX = 0,
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UART1_RTS,
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UART2_TX,
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UART2_RX,
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UART2_CTS,
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UART2_RTS,
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UART3_TX,
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UART3_RX,
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UART3_CTS,
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UART3_RTS,
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UART3_CLKREQ,
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UART3_BCLK,
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Y15_1610_UART3_RTS,
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PWT,
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PWL,
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R18_USB_VBUS,
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R18_1510_USB_GPIO0,
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W4_USB_PUEN,
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W4_USB_CLKO,
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W4_USB_HIGHZ,
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W4_GPIO58,
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USB1_SUSP,
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USB1_SEO,
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W13_1610_USB1_SE0,
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USB1_TXEN,
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USB1_TXD,
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USB1_VP,
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USB1_VM,
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USB1_RCV,
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USB1_SPEED,
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R13_1610_USB1_SPEED,
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R13_1710_USB1_SE0,
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USB2_SUSP,
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USB2_VP,
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USB2_TXEN,
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USB2_VM,
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USB2_RCV,
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USB2_SEO,
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USB2_TXD,
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R18_1510_GPIO0,
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R19_1510_GPIO1,
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M14_1510_GPIO2,
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P18_1610_GPIO3,
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Y15_1610_GPIO17,
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R18_1710_GPIO0,
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V2_1710_GPIO10,
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N21_1710_GPIO14,
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W15_1710_GPIO40,
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MPUIO2,
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N15_1610_MPUIO2,
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MPUIO4,
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MPUIO5,
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T20_1610_MPUIO5,
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W11_1610_MPUIO6,
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V10_1610_MPUIO7,
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W11_1610_MPUIO9,
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V10_1610_MPUIO10,
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W10_1610_MPUIO11,
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E20_1610_MPUIO13,
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U20_1610_MPUIO14,
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E19_1610_MPUIO15,
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MCBSP2_CLKR,
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MCBSP2_CLKX,
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MCBSP2_DR,
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MCBSP2_DX,
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MCBSP2_FSR,
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MCBSP2_FSX,
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MCBSP3_CLKX,
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BALLOUT_V8_ARMIO3,
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N20_HDQ,
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W8_1610_MMC2_DAT0,
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V8_1610_MMC2_DAT1,
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W15_1610_MMC2_DAT2,
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R10_1610_MMC2_DAT3,
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Y10_1610_MMC2_CLK,
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Y8_1610_MMC2_CMD,
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V9_1610_MMC2_CMDDIR,
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V5_1610_MMC2_DATDIR0,
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W19_1610_MMC2_DATDIR1,
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R18_1610_MMC2_CLKIN,
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M19_1610_ETM_PSTAT0,
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L15_1610_ETM_PSTAT1,
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L18_1610_ETM_PSTAT2,
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L19_1610_ETM_D0,
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J19_1610_ETM_D6,
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J18_1610_ETM_D7,
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P20_1610_GPIO4,
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V9_1610_GPIO7,
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W8_1610_GPIO9,
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N20_1610_GPIO11,
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N19_1610_GPIO13,
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P10_1610_GPIO22,
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V5_1610_GPIO24,
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AA20_1610_GPIO_41,
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W19_1610_GPIO48,
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M7_1610_GPIO62,
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V14_16XX_GPIO37,
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R9_16XX_GPIO18,
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L14_16XX_GPIO49,
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V19_1610_UWIRE_SCLK,
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U18_1610_UWIRE_SDI,
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W21_1610_UWIRE_SDO,
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N14_1610_UWIRE_CS0,
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P15_1610_UWIRE_CS3,
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N15_1610_UWIRE_CS1,
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U19_1610_SPIF_SCK,
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U18_1610_SPIF_DIN,
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P20_1610_SPIF_DIN,
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W21_1610_SPIF_DOUT,
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R18_1610_SPIF_DOUT,
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N14_1610_SPIF_CS0,
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N15_1610_SPIF_CS1,
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T19_1610_SPIF_CS2,
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P15_1610_SPIF_CS3,
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L3_1610_FLASH_CS2B_OE,
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M8_1610_FLASH_CS2B_WE,
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MMC_CMD,
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MMC_DAT1,
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MMC_DAT2,
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MMC_DAT0,
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MMC_CLK,
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MMC_DAT3,
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M15_1710_MMC_CLKI,
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P19_1710_MMC_CMDDIR,
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P20_1710_MMC_DATDIR0,
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W9_USB0_TXEN,
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AA9_USB0_VP,
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Y5_USB0_RCV,
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R9_USB0_VM,
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V6_USB0_TXD,
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W5_USB0_SE0,
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V9_USB0_SPEED,
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V9_USB0_SUSP,
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W9_USB2_TXEN,
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AA9_USB2_VP,
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Y5_USB2_RCV,
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R9_USB2_VM,
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V6_USB2_TXD,
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W5_USB2_SE0,
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R13_1610_UART1_TX,
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V14_16XX_UART1_RX,
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R14_1610_UART1_CTS,
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AA15_1610_UART1_RTS,
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R9_16XX_UART2_RX,
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L14_16XX_UART3_RX,
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I2C_SCL,
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I2C_SDA,
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F18_1610_KBC0,
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D20_1610_KBC1,
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D19_1610_KBC2,
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E18_1610_KBC3,
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C21_1610_KBC4,
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G18_1610_KBR0,
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F19_1610_KBR1,
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H14_1610_KBR2,
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E20_1610_KBR3,
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E19_1610_KBR4,
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N19_1610_KBR5,
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T20_1610_LOW_PWR,
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V5_1710_MCLK_ON,
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V5_1710_MCLK_OFF,
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R10_1610_MCLK_ON,
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R10_1610_MCLK_OFF,
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P11_1610_CF_CD2,
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R11_1610_CF_IOIS16,
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V10_1610_CF_IREQ,
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W10_1610_CF_RESET,
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W11_1610_CF_CD1,
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};
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enum omap24xx_index {
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M19_24XX_I2C1_SCL,
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L15_24XX_I2C1_SDA,
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J15_24XX_I2C2_SCL,
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H19_24XX_I2C2_SDA,
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W19_24XX_SYS_NIRQ,
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W14_24XX_SYS_CLKOUT,
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L3_GPMC_WAIT0,
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N7_GPMC_WAIT1,
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M1_GPMC_WAIT2,
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P1_GPMC_WAIT3,
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Y15_24XX_MCBSP2_CLKX,
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R14_24XX_MCBSP2_FSX,
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W15_24XX_MCBSP2_DR,
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V15_24XX_MCBSP2_DX,
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M21_242X_GPIO11,
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AA10_242X_GPIO13,
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AA6_242X_GPIO14,
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AA4_242X_GPIO15,
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Y11_242X_GPIO16,
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AA12_242X_GPIO17,
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AA8_242X_GPIO58,
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Y20_24XX_GPIO60,
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W4__24XX_GPIO74,
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M15_24XX_GPIO92,
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V14_24XX_GPIO117,
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V4_242X_GPIO49,
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W2_242X_GPIO50,
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U4_242X_GPIO51,
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V3_242X_GPIO52,
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V2_242X_GPIO53,
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V6_242X_GPIO53,
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T4_242X_GPIO54,
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Y4_242X_GPIO54,
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T3_242X_GPIO55,
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U2_242X_GPIO56,
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AA10_242X_DMAREQ0,
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AA6_242X_DMAREQ1,
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E4_242X_DMAREQ2,
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G4_242X_DMAREQ3,
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D3_242X_DMAREQ4,
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E3_242X_DMAREQ5,
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P20_24XX_TSC_IRQ,
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K15_24XX_UART3_TX,
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K14_24XX_UART3_RX,
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G19_24XX_MMC_CLKO,
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H18_24XX_MMC_CMD,
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F20_24XX_MMC_DAT0,
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H14_24XX_MMC_DAT1,
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E19_24XX_MMC_DAT2,
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D19_24XX_MMC_DAT3,
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F19_24XX_MMC_DAT_DIR0,
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E20_24XX_MMC_DAT_DIR1,
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F18_24XX_MMC_DAT_DIR2,
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E18_24XX_MMC_DAT_DIR3,
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G18_24XX_MMC_CMD_DIR,
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H15_24XX_MMC_CLKI,
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T19_24XX_KBR0,
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R19_24XX_KBR1,
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V18_24XX_KBR2,
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M21_24XX_KBR3,
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E5__24XX_KBR4,
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M18_24XX_KBR5,
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R20_24XX_KBC0,
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M14_24XX_KBC1,
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H19_24XX_KBC2,
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V17_24XX_KBC3,
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P21_24XX_KBC4,
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L14_24XX_KBC5,
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N19_24XX_KBC6,
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B3__24XX_KBR5,
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AA4_24XX_KBC2,
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B13_24XX_KBC6,
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};
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#endif
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