d7db594b8d
Replace the tokenizer in cpp.py with libclang. Bug: 18937958 Change-Id: I27630904c6d2849418cd5ca3d3c612ec3078686d
725 lines
30 KiB
C
725 lines
30 KiB
C
/****************************************************************************
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****************************************************************************
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***
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*** This header was automatically generated from a Linux kernel header
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*** of the same name, to make information necessary for userspace to
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*** call into the kernel available to libc. It contains only constants,
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*** structures, and macros generated from the original header, and thus,
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*** contains no copyrightable information.
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***
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*** To edit the content of this header, modify the corresponding
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*** source file (e.g. under external/kernel-headers/original/) then
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*** run bionic/libc/kernel/tools/update_all.py
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***
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*** Any manual change here will be lost the next time this script will
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*** be run. You've been warned!
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***
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****************************************************************************
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****************************************************************************/
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#ifndef _UAPI_I915_DRM_H_
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#define _UAPI_I915_DRM_H_
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#include <drm/drm.h>
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#define I915_L3_PARITY_UEVENT "L3_PARITY_ERROR"
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define I915_ERROR_UEVENT "ERROR"
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#define I915_RESET_UEVENT "RESET"
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#define I915_NR_TEX_REGIONS 255
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#define I915_LOG_MIN_TEX_REGION_SIZE 14
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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typedef struct _drm_i915_init {
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enum {
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I915_INIT_DMA = 0x01,
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I915_CLEANUP_DMA = 0x02,
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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I915_RESUME_DMA = 0x03
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} func;
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unsigned int mmio_offset;
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int sarea_priv_offset;
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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unsigned int ring_start;
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unsigned int ring_end;
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unsigned int ring_size;
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unsigned int front_offset;
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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unsigned int back_offset;
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unsigned int depth_offset;
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unsigned int w;
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unsigned int h;
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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unsigned int pitch;
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unsigned int pitch_bits;
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unsigned int back_pitch;
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unsigned int depth_pitch;
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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unsigned int cpp;
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unsigned int chipset;
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} drm_i915_init_t;
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typedef struct _drm_i915_sarea {
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1];
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int last_upload;
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int last_enqueue;
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int last_dispatch;
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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int ctxOwner;
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int texAge;
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int pf_enabled;
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int pf_active;
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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int pf_current_page;
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int perf_boxes;
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int width, height;
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drm_handle_t front_handle;
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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int front_offset;
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int front_size;
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drm_handle_t back_handle;
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int back_offset;
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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int back_size;
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drm_handle_t depth_handle;
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int depth_offset;
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int depth_size;
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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drm_handle_t tex_handle;
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int tex_offset;
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int tex_size;
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int log_tex_granularity;
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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int pitch;
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int rotation;
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int rotated_offset;
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int rotated_size;
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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int rotated_pitch;
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int virtualX, virtualY;
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unsigned int front_tiled;
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unsigned int back_tiled;
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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unsigned int depth_tiled;
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unsigned int rotated_tiled;
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unsigned int rotated2_tiled;
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int pipeA_x;
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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int pipeA_y;
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int pipeA_w;
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int pipeA_h;
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int pipeB_x;
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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int pipeB_y;
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int pipeB_w;
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int pipeB_h;
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drm_handle_t unused_handle;
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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__u32 unused1, unused2, unused3;
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__u32 front_bo_handle;
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__u32 back_bo_handle;
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__u32 unused_bo_handle;
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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__u32 depth_bo_handle;
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} drm_i915_sarea_t;
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#define planeA_x pipeA_x
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#define planeA_y pipeA_y
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define planeA_w pipeA_w
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#define planeA_h pipeA_h
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#define planeB_x pipeB_x
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#define planeB_y pipeB_y
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define planeB_w pipeB_w
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#define planeB_h pipeB_h
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#define I915_BOX_RING_EMPTY 0x1
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#define I915_BOX_FLIP 0x2
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define I915_BOX_WAIT 0x4
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#define I915_BOX_TEXTURE_LOAD 0x8
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#define I915_BOX_LOST_CONTEXT 0x10
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#define DRM_I915_INIT 0x00
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define DRM_I915_FLUSH 0x01
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#define DRM_I915_FLIP 0x02
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#define DRM_I915_BATCHBUFFER 0x03
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#define DRM_I915_IRQ_EMIT 0x04
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define DRM_I915_IRQ_WAIT 0x05
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#define DRM_I915_GETPARAM 0x06
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#define DRM_I915_SETPARAM 0x07
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#define DRM_I915_ALLOC 0x08
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define DRM_I915_FREE 0x09
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#define DRM_I915_INIT_HEAP 0x0a
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#define DRM_I915_CMDBUFFER 0x0b
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#define DRM_I915_DESTROY_HEAP 0x0c
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define DRM_I915_SET_VBLANK_PIPE 0x0d
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#define DRM_I915_GET_VBLANK_PIPE 0x0e
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#define DRM_I915_VBLANK_SWAP 0x0f
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#define DRM_I915_HWS_ADDR 0x11
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define DRM_I915_GEM_INIT 0x13
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#define DRM_I915_GEM_EXECBUFFER 0x14
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#define DRM_I915_GEM_PIN 0x15
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#define DRM_I915_GEM_UNPIN 0x16
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define DRM_I915_GEM_BUSY 0x17
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#define DRM_I915_GEM_THROTTLE 0x18
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#define DRM_I915_GEM_ENTERVT 0x19
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#define DRM_I915_GEM_LEAVEVT 0x1a
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define DRM_I915_GEM_CREATE 0x1b
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#define DRM_I915_GEM_PREAD 0x1c
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#define DRM_I915_GEM_PWRITE 0x1d
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#define DRM_I915_GEM_MMAP 0x1e
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define DRM_I915_GEM_SET_DOMAIN 0x1f
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#define DRM_I915_GEM_SW_FINISH 0x20
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#define DRM_I915_GEM_SET_TILING 0x21
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#define DRM_I915_GEM_GET_TILING 0x22
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define DRM_I915_GEM_GET_APERTURE 0x23
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#define DRM_I915_GEM_MMAP_GTT 0x24
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#define DRM_I915_GET_PIPE_FROM_CRTC_ID 0x25
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#define DRM_I915_GEM_MADVISE 0x26
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define DRM_I915_OVERLAY_PUT_IMAGE 0x27
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#define DRM_I915_OVERLAY_ATTRS 0x28
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#define DRM_I915_GEM_EXECBUFFER2 0x29
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#define DRM_I915_GET_SPRITE_COLORKEY 0x2a
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define DRM_I915_SET_SPRITE_COLORKEY 0x2b
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#define DRM_I915_GEM_WAIT 0x2c
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#define DRM_I915_GEM_CONTEXT_CREATE 0x2d
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#define DRM_I915_GEM_CONTEXT_DESTROY 0x2e
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define DRM_I915_GEM_SET_CACHING 0x2f
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#define DRM_I915_GEM_GET_CACHING 0x30
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#define DRM_I915_REG_READ 0x31
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#define DRM_I915_GET_RESET_STATS 0x32
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define DRM_I915_GEM_USERPTR 0x33
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#define DRM_IOCTL_I915_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
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#define DRM_IOCTL_I915_FLUSH DRM_IO(DRM_COMMAND_BASE + DRM_I915_FLUSH)
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#define DRM_IOCTL_I915_FLIP DRM_IO(DRM_COMMAND_BASE + DRM_I915_FLIP)
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t)
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#define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t)
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#define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t)
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#define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t)
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define DRM_IOCTL_I915_SETPARAM DRM_IOW(DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t)
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#define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t)
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#define DRM_IOCTL_I915_FREE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t)
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#define DRM_IOCTL_I915_INIT_HEAP DRM_IOW(DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t)
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define DRM_IOCTL_I915_CMDBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t)
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#define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW(DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t)
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#define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
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#define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR(DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t)
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#define DRM_IOCTL_I915_HWS_ADDR DRM_IOW(DRM_COMMAND_BASE + DRM_I915_HWS_ADDR, struct drm_i915_gem_init)
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#define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init)
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#define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer)
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define DRM_IOCTL_I915_GEM_EXECBUFFER2 DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2)
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#define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin)
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#define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin)
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#define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy)
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define DRM_IOCTL_I915_GEM_SET_CACHING DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SET_CACHING, struct drm_i915_gem_caching)
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#define DRM_IOCTL_I915_GEM_GET_CACHING DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_CACHING, struct drm_i915_gem_caching)
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#define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE)
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#define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT)
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT)
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#define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create)
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#define DRM_IOCTL_I915_GEM_PREAD DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread)
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#define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite)
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap)
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#define DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt)
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#define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain)
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#define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish)
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling)
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#define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling)
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#define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture)
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#define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id)
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define DRM_IOCTL_I915_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise)
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#define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_OVERLAY_PUT_IMAGE, struct drm_intel_overlay_put_image)
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#define DRM_IOCTL_I915_OVERLAY_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs)
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#define DRM_IOCTL_I915_SET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)
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#define DRM_IOCTL_I915_GEM_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait)
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#define DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create)
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#define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy)
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define DRM_IOCTL_I915_REG_READ DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read)
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#define DRM_IOCTL_I915_GET_RESET_STATS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_RESET_STATS, struct drm_i915_reset_stats)
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#define DRM_IOCTL_I915_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_USERPTR, struct drm_i915_gem_userptr)
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typedef struct drm_i915_batchbuffer {
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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int start;
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int used;
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int DR1;
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int DR4;
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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int num_cliprects;
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struct drm_clip_rect __user * cliprects;
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} drm_i915_batchbuffer_t;
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typedef struct _drm_i915_cmdbuffer {
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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char __user * buf;
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int sz;
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int DR1;
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int DR4;
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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int num_cliprects;
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struct drm_clip_rect __user * cliprects;
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} drm_i915_cmdbuffer_t;
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typedef struct drm_i915_irq_emit {
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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int __user * irq_seq;
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} drm_i915_irq_emit_t;
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typedef struct drm_i915_irq_wait {
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int irq_seq;
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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} drm_i915_irq_wait_t;
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#define I915_PARAM_IRQ_ACTIVE 1
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#define I915_PARAM_ALLOW_BATCHBUFFER 2
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#define I915_PARAM_LAST_DISPATCH 3
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define I915_PARAM_CHIPSET_ID 4
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#define I915_PARAM_HAS_GEM 5
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#define I915_PARAM_NUM_FENCES_AVAIL 6
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#define I915_PARAM_HAS_OVERLAY 7
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define I915_PARAM_HAS_PAGEFLIPPING 8
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#define I915_PARAM_HAS_EXECBUF2 9
|
|
#define I915_PARAM_HAS_BSD 10
|
|
#define I915_PARAM_HAS_BLT 11
|
|
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
|
#define I915_PARAM_HAS_RELAXED_FENCING 12
|
|
#define I915_PARAM_HAS_COHERENT_RINGS 13
|
|
#define I915_PARAM_HAS_EXEC_CONSTANTS 14
|
|
#define I915_PARAM_HAS_RELAXED_DELTA 15
|
|
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
|
#define I915_PARAM_HAS_GEN7_SOL_RESET 16
|
|
#define I915_PARAM_HAS_LLC 17
|
|
#define I915_PARAM_HAS_ALIASING_PPGTT 18
|
|
#define I915_PARAM_HAS_WAIT_TIMEOUT 19
|
|
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
|
#define I915_PARAM_HAS_SEMAPHORES 20
|
|
#define I915_PARAM_HAS_PRIME_VMAP_FLUSH 21
|
|
#define I915_PARAM_HAS_VEBOX 22
|
|
#define I915_PARAM_HAS_SECURE_BATCHES 23
|
|
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
|
#define I915_PARAM_HAS_PINNED_BATCHES 24
|
|
#define I915_PARAM_HAS_EXEC_NO_RELOC 25
|
|
#define I915_PARAM_HAS_EXEC_HANDLE_LUT 26
|
|
#define I915_PARAM_HAS_WT 27
|
|
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
|
#define I915_PARAM_CMD_PARSER_VERSION 28
|
|
typedef struct drm_i915_getparam {
|
|
int param;
|
|
int __user * value;
|
|
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
|
} drm_i915_getparam_t;
|
|
#define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1
|
|
#define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2
|
|
#define I915_SETPARAM_ALLOW_BATCHBUFFER 3
|
|
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
|
#define I915_SETPARAM_NUM_USED_FENCES 4
|
|
typedef struct drm_i915_setparam {
|
|
int param;
|
|
int value;
|
|
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
|
} drm_i915_setparam_t;
|
|
#define I915_MEM_REGION_AGP 1
|
|
typedef struct drm_i915_mem_alloc {
|
|
int region;
|
|
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
|
int alignment;
|
|
int size;
|
|
int __user * region_offset;
|
|
} drm_i915_mem_alloc_t;
|
|
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
|
typedef struct drm_i915_mem_free {
|
|
int region;
|
|
int region_offset;
|
|
} drm_i915_mem_free_t;
|
|
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
|
typedef struct drm_i915_mem_init_heap {
|
|
int region;
|
|
int size;
|
|
int start;
|
|
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
|
} drm_i915_mem_init_heap_t;
|
|
typedef struct drm_i915_mem_destroy_heap {
|
|
int region;
|
|
} drm_i915_mem_destroy_heap_t;
|
|
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
|
#define DRM_I915_VBLANK_PIPE_A 1
|
|
#define DRM_I915_VBLANK_PIPE_B 2
|
|
typedef struct drm_i915_vblank_pipe {
|
|
int pipe;
|
|
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
|
} drm_i915_vblank_pipe_t;
|
|
typedef struct drm_i915_vblank_swap {
|
|
drm_drawable_t drawable;
|
|
enum drm_vblank_seq_type seqtype;
|
|
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
|
unsigned int sequence;
|
|
} drm_i915_vblank_swap_t;
|
|
typedef struct drm_i915_hws_addr {
|
|
__u64 addr;
|
|
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
|
} drm_i915_hws_addr_t;
|
|
struct drm_i915_gem_init {
|
|
__u64 gtt_start;
|
|
__u64 gtt_end;
|
|
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
|
};
|
|
struct drm_i915_gem_create {
|
|
__u64 size;
|
|
__u32 handle;
|
|
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
|
__u32 pad;
|
|
};
|
|
struct drm_i915_gem_pread {
|
|
__u32 handle;
|
|
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
|
__u32 pad;
|
|
__u64 offset;
|
|
__u64 size;
|
|
__u64 data_ptr;
|
|
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
|
};
|
|
struct drm_i915_gem_pwrite {
|
|
__u32 handle;
|
|
__u32 pad;
|
|
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
|
__u64 offset;
|
|
__u64 size;
|
|
__u64 data_ptr;
|
|
};
|
|
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
|
struct drm_i915_gem_mmap {
|
|
__u32 handle;
|
|
__u32 pad;
|
|
__u64 offset;
|
|
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
|
__u64 size;
|
|
__u64 addr_ptr;
|
|
};
|
|
struct drm_i915_gem_mmap_gtt {
|
|
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
|
__u32 handle;
|
|
__u32 pad;
|
|
__u64 offset;
|
|
};
|
|
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
|
struct drm_i915_gem_set_domain {
|
|
__u32 handle;
|
|
__u32 read_domains;
|
|
__u32 write_domain;
|
|
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
|
};
|
|
struct drm_i915_gem_sw_finish {
|
|
__u32 handle;
|
|
};
|
|
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
|
struct drm_i915_gem_relocation_entry {
|
|
__u32 target_handle;
|
|
__u32 delta;
|
|
__u64 offset;
|
|
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
|
__u64 presumed_offset;
|
|
__u32 read_domains;
|
|
__u32 write_domain;
|
|
};
|
|
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
|
#define I915_GEM_DOMAIN_CPU 0x00000001
|
|
#define I915_GEM_DOMAIN_RENDER 0x00000002
|
|
#define I915_GEM_DOMAIN_SAMPLER 0x00000004
|
|
#define I915_GEM_DOMAIN_COMMAND 0x00000008
|
|
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
|
#define I915_GEM_DOMAIN_INSTRUCTION 0x00000010
|
|
#define I915_GEM_DOMAIN_VERTEX 0x00000020
|
|
#define I915_GEM_DOMAIN_GTT 0x00000040
|
|
struct drm_i915_gem_exec_object {
|
|
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
|
__u32 handle;
|
|
__u32 relocation_count;
|
|
__u64 relocs_ptr;
|
|
__u64 alignment;
|
|
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
|
__u64 offset;
|
|
};
|
|
struct drm_i915_gem_execbuffer {
|
|
__u64 buffers_ptr;
|
|
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
|
__u32 buffer_count;
|
|
__u32 batch_start_offset;
|
|
__u32 batch_len;
|
|
__u32 DR1;
|
|
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
|
__u32 DR4;
|
|
__u32 num_cliprects;
|
|
__u64 cliprects_ptr;
|
|
};
|
|
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
|
struct drm_i915_gem_exec_object2 {
|
|
__u32 handle;
|
|
__u32 relocation_count;
|
|
__u64 relocs_ptr;
|
|
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
|
__u64 alignment;
|
|
__u64 offset;
|
|
#define EXEC_OBJECT_NEEDS_FENCE (1 << 0)
|
|
#define EXEC_OBJECT_NEEDS_GTT (1 << 1)
|
|
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
|
#define EXEC_OBJECT_WRITE (1 << 2)
|
|
#define __EXEC_OBJECT_UNKNOWN_FLAGS - (EXEC_OBJECT_WRITE << 1)
|
|
__u64 flags;
|
|
__u64 rsvd1;
|
|
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
|
__u64 rsvd2;
|
|
};
|
|
struct drm_i915_gem_execbuffer2 {
|
|
__u64 buffers_ptr;
|
|
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
|
__u32 buffer_count;
|
|
__u32 batch_start_offset;
|
|
__u32 batch_len;
|
|
__u32 DR1;
|
|
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
|
__u32 DR4;
|
|
__u32 num_cliprects;
|
|
__u64 cliprects_ptr;
|
|
#define I915_EXEC_RING_MASK (7 << 0)
|
|
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
|
#define I915_EXEC_DEFAULT (0 << 0)
|
|
#define I915_EXEC_RENDER (1 << 0)
|
|
#define I915_EXEC_BSD (2 << 0)
|
|
#define I915_EXEC_BLT (3 << 0)
|
|
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
|
#define I915_EXEC_VEBOX (4 << 0)
|
|
#define I915_EXEC_CONSTANTS_MASK (3 << 6)
|
|
#define I915_EXEC_CONSTANTS_REL_GENERAL (0 << 6)
|
|
#define I915_EXEC_CONSTANTS_ABSOLUTE (1 << 6)
|
|
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
|
#define I915_EXEC_CONSTANTS_REL_SURFACE (2 << 6)
|
|
__u64 flags;
|
|
__u64 rsvd1;
|
|
__u64 rsvd2;
|
|
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
|
};
|
|
#define I915_EXEC_GEN7_SOL_RESET (1 << 8)
|
|
#define I915_EXEC_SECURE (1 << 9)
|
|
#define I915_EXEC_IS_PINNED (1 << 10)
|
|
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
|
#define I915_EXEC_NO_RELOC (1 << 11)
|
|
#define I915_EXEC_HANDLE_LUT (1 << 12)
|
|
#define __I915_EXEC_UNKNOWN_FLAGS - (I915_EXEC_HANDLE_LUT << 1)
|
|
#define I915_EXEC_CONTEXT_ID_MASK (0xffffffff)
|
|
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
|
#define i915_execbuffer2_set_context_id(eb2,context) (eb2).rsvd1 = context & I915_EXEC_CONTEXT_ID_MASK
|
|
#define i915_execbuffer2_get_context_id(eb2) ((eb2).rsvd1 & I915_EXEC_CONTEXT_ID_MASK)
|
|
struct drm_i915_gem_pin {
|
|
__u32 handle;
|
|
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
|
__u32 pad;
|
|
__u64 alignment;
|
|
__u64 offset;
|
|
};
|
|
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
|
struct drm_i915_gem_unpin {
|
|
__u32 handle;
|
|
__u32 pad;
|
|
};
|
|
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
|
struct drm_i915_gem_busy {
|
|
__u32 handle;
|
|
__u32 busy;
|
|
};
|
|
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
|
#define I915_CACHING_NONE 0
|
|
#define I915_CACHING_CACHED 1
|
|
#define I915_CACHING_DISPLAY 2
|
|
struct drm_i915_gem_caching {
|
|
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
|
__u32 handle;
|
|
__u32 caching;
|
|
};
|
|
#define I915_TILING_NONE 0
|
|
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
|
#define I915_TILING_X 1
|
|
#define I915_TILING_Y 2
|
|
#define I915_BIT_6_SWIZZLE_NONE 0
|
|
#define I915_BIT_6_SWIZZLE_9 1
|
|
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
|
#define I915_BIT_6_SWIZZLE_9_10 2
|
|
#define I915_BIT_6_SWIZZLE_9_11 3
|
|
#define I915_BIT_6_SWIZZLE_9_10_11 4
|
|
#define I915_BIT_6_SWIZZLE_UNKNOWN 5
|
|
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
|
#define I915_BIT_6_SWIZZLE_9_17 6
|
|
#define I915_BIT_6_SWIZZLE_9_10_17 7
|
|
struct drm_i915_gem_set_tiling {
|
|
__u32 handle;
|
|
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
|
__u32 tiling_mode;
|
|
__u32 stride;
|
|
__u32 swizzle_mode;
|
|
};
|
|
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
|
struct drm_i915_gem_get_tiling {
|
|
__u32 handle;
|
|
__u32 tiling_mode;
|
|
__u32 swizzle_mode;
|
|
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
|
};
|
|
struct drm_i915_gem_get_aperture {
|
|
__u64 aper_size;
|
|
__u64 aper_available_size;
|
|
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
|
};
|
|
struct drm_i915_get_pipe_from_crtc_id {
|
|
__u32 crtc_id;
|
|
__u32 pipe;
|
|
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
|
};
|
|
#define I915_MADV_WILLNEED 0
|
|
#define I915_MADV_DONTNEED 1
|
|
#define __I915_MADV_PURGED 2
|
|
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
|
struct drm_i915_gem_madvise {
|
|
__u32 handle;
|
|
__u32 madv;
|
|
__u32 retained;
|
|
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
|
};
|
|
#define I915_OVERLAY_TYPE_MASK 0xff
|
|
#define I915_OVERLAY_YUV_PLANAR 0x01
|
|
#define I915_OVERLAY_YUV_PACKED 0x02
|
|
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
|
#define I915_OVERLAY_RGB 0x03
|
|
#define I915_OVERLAY_DEPTH_MASK 0xff00
|
|
#define I915_OVERLAY_RGB24 0x1000
|
|
#define I915_OVERLAY_RGB16 0x2000
|
|
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
|
#define I915_OVERLAY_RGB15 0x3000
|
|
#define I915_OVERLAY_YUV422 0x0100
|
|
#define I915_OVERLAY_YUV411 0x0200
|
|
#define I915_OVERLAY_YUV420 0x0300
|
|
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
|
#define I915_OVERLAY_YUV410 0x0400
|
|
#define I915_OVERLAY_SWAP_MASK 0xff0000
|
|
#define I915_OVERLAY_NO_SWAP 0x000000
|
|
#define I915_OVERLAY_UV_SWAP 0x010000
|
|
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
|
#define I915_OVERLAY_Y_SWAP 0x020000
|
|
#define I915_OVERLAY_Y_AND_UV_SWAP 0x030000
|
|
#define I915_OVERLAY_FLAGS_MASK 0xff000000
|
|
#define I915_OVERLAY_ENABLE 0x01000000
|
|
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
|
struct drm_intel_overlay_put_image {
|
|
__u32 flags;
|
|
__u32 bo_handle;
|
|
__u16 stride_Y;
|
|
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
|
__u16 stride_UV;
|
|
__u32 offset_Y;
|
|
__u32 offset_U;
|
|
__u32 offset_V;
|
|
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
|
__u16 src_width;
|
|
__u16 src_height;
|
|
__u16 src_scan_width;
|
|
__u16 src_scan_height;
|
|
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
|
__u32 crtc_id;
|
|
__u16 dst_x;
|
|
__u16 dst_y;
|
|
__u16 dst_width;
|
|
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
|
__u16 dst_height;
|
|
};
|
|
#define I915_OVERLAY_UPDATE_ATTRS (1 << 0)
|
|
#define I915_OVERLAY_UPDATE_GAMMA (1 << 1)
|
|
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
|
struct drm_intel_overlay_attrs {
|
|
__u32 flags;
|
|
__u32 color_key;
|
|
__s32 brightness;
|
|
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
|
__u32 contrast;
|
|
__u32 saturation;
|
|
__u32 gamma0;
|
|
__u32 gamma1;
|
|
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
|
__u32 gamma2;
|
|
__u32 gamma3;
|
|
__u32 gamma4;
|
|
__u32 gamma5;
|
|
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
|
};
|
|
#define I915_SET_COLORKEY_NONE (1 << 0)
|
|
#define I915_SET_COLORKEY_DESTINATION (1 << 1)
|
|
#define I915_SET_COLORKEY_SOURCE (1 << 2)
|
|
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
|
struct drm_intel_sprite_colorkey {
|
|
__u32 plane_id;
|
|
__u32 min_value;
|
|
__u32 channel_mask;
|
|
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
|
__u32 max_value;
|
|
__u32 flags;
|
|
};
|
|
struct drm_i915_gem_wait {
|
|
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
|
__u32 bo_handle;
|
|
__u32 flags;
|
|
__s64 timeout_ns;
|
|
};
|
|
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
|
struct drm_i915_gem_context_create {
|
|
__u32 ctx_id;
|
|
__u32 pad;
|
|
};
|
|
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
|
struct drm_i915_gem_context_destroy {
|
|
__u32 ctx_id;
|
|
__u32 pad;
|
|
};
|
|
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
|
struct drm_i915_reg_read {
|
|
__u64 offset;
|
|
__u64 val;
|
|
};
|
|
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
|
struct drm_i915_reset_stats {
|
|
__u32 ctx_id;
|
|
__u32 flags;
|
|
__u32 reset_count;
|
|
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
|
__u32 batch_active;
|
|
__u32 batch_pending;
|
|
__u32 pad;
|
|
};
|
|
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
|
struct drm_i915_gem_userptr {
|
|
__u64 user_ptr;
|
|
__u64 user_size;
|
|
__u32 flags;
|
|
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
|
#define I915_USERPTR_READ_ONLY 0x1
|
|
#define I915_USERPTR_UNSYNCHRONIZED 0x80000000
|
|
__u32 handle;
|
|
};
|
|
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
|
#endif
|