103 lines
3.8 KiB
C
103 lines
3.8 KiB
C
/*
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* Copyright (C) 2011 The Android Open Source Project
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef BIONIC_ATOMIC_MIPS_H
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#define BIONIC_ATOMIC_MIPS_H
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/* Define a full memory barrier, this is only needed if we build the
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* platform for a multi-core device.
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*/
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#if defined(ANDROID_SMP) && ANDROID_SMP == 1
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__ATOMIC_INLINE__ void
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__bionic_memory_barrier()
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{
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__asm__ __volatile__ ( "sync" : : : "memory" );
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}
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#else
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__ATOMIC_INLINE__ void
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__bionic_memory_barrier()
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{
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/* A simple compiler barrier */
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__asm__ __volatile__ ( "" : : : "memory" );
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}
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#endif
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/* Compare-and-swap, without any explicit barriers. Note that this function
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* returns 0 on success, and 1 on failure. The opposite convention is typically
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* used on other platforms.
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*/
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__ATOMIC_INLINE__ int
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__bionic_cmpxchg(int32_t old_value, int32_t new_value, volatile int32_t* ptr)
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{
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int32_t prev, status;
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__asm__ __volatile__ ("1: move %[status], %[new_value] \n"
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" ll %[prev], 0(%[ptr]) \n"
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" bne %[old_value], %[prev], 2f \n"
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" sc %[status], 0(%[ptr]) \n"
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" beqz %[status], 1b \n"
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"2: \n"
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: [prev]"=&r"(prev), [status]"=&r"(status), "+m"(*ptr)
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: [new_value]"r"(new_value), [old_value]"r"(old_value), [ptr]"r"(ptr)
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: "memory");
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return prev != old_value;
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}
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/* Swap, without any explicit barriers */
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__ATOMIC_INLINE__ int32_t
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__bionic_swap(int32_t new_value, volatile int32_t *ptr)
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{
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int32_t prev, status;
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__asm__ __volatile__ ("1: move %[status], %[new_value] \n"
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" ll %[prev], 0(%[ptr]) \n"
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" sc %[status], 0(%[ptr]) \n"
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" beqz %[status], 1b \n"
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: [prev]"=&r"(prev), [status]"=&r"(status), "+m"(*ptr)
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: [ptr]"r"(ptr), [new_value]"r"(new_value)
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: "memory");
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return prev;
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}
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/* Atomic increment, without explicit barriers */
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__ATOMIC_INLINE__ int32_t
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__bionic_atomic_inc(volatile int32_t *ptr)
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{
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int32_t prev, status;
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__asm__ __volatile__ ("1: ll %[prev], 0(%[ptr]) \n"
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" addiu %[status], %[prev], 1 \n"
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" sc %[status], 0(%[ptr]) \n"
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" beqz %[status], 1b \n"
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: [prev]"=&r" (prev), [status]"=&r"(status), "+m" (*ptr)
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: [ptr]"r"(ptr)
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: "memory");
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return prev;
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}
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/* Atomic decrement, without explicit barriers */
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__ATOMIC_INLINE__ int32_t
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__bionic_atomic_dec(volatile int32_t *ptr)
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{
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int32_t prev, status;
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__asm__ __volatile__ ("1: ll %[prev], 0(%[ptr]) \n"
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" addiu %[status], %[prev], -1 \n"
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" sc %[status], 0(%[ptr]) \n"
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" beqz %[status], 1b \n"
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: [prev]"=&r" (prev), [status]"=&r"(status), "+m" (*ptr)
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: [ptr]"r"(ptr)
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: "memory");
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return prev;
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}
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#endif /* BIONIC_ATOMIC_MIPS_H */
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