Atomic/SMP update, part 3.
Update ARM atomic ops to use LDREX/STREX. Stripped out #if 0 chunk. Insert explicit memory barriers in pthread and semaphore code. For bug 2721865. Change-Id: I0f153b797753a655702d8be41679273d1d5d6ae7
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@@ -455,6 +455,14 @@ else # !arm
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endif # x86
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endif # !arm
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# Define ANDROID_SMP appropriately.
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ifeq ($(TARGET_CPU_SMP),true)
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libc_common_cflags += -DANDROID_SMP=1
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else
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libc_common_cflags += -DANDROID_SMP=0
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endif
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# Define some common includes
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# ========================================================
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libc_common_c_includes := \
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