NEON optimized memcpy.
372 MB/s for large transfers, 440 MB/s for smaller ones down to 1KB. 130 MB/s for very small transfers ( < 32 bytes ) Performance is similar with non-congruent buffers.
This commit is contained in:
Mathias Agopian
parent
33acbf0719
commit
ee223d02d9
@ -28,6 +28,136 @@
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#include <machine/cpu-features.h>
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#if __ARM_ARCH__ == 7 || defined(__ARM_NEON__)
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.text
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.fpu neon
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.global memcpy
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.type memcpy, %function
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.align 4
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/* a prefetch distance of 32*4 works best experimentally */
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#define PREFETCH_DISTANCE (32*4)
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memcpy:
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.fnstart
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.save {r0, lr}
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stmfd sp!, {r0, lr}
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/* start preloading as early as possible */
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pld [r1, #0]
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pld [r1, #32]
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/* do we have at least 16-bytes to copy (needed for alignment below) */
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cmp r2, #16
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blo 5f
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/* align destination to half cache-line for the write-buffer */
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rsb r3, r0, #0
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ands r3, r3, #0xF
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beq 0f
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/* copy up to 15-bytes (count in r3) */
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sub r2, r2, r3
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movs ip, r3, lsl #31
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ldrmib lr, [r1], #1
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strmib lr, [r0], #1
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ldrcsb ip, [r1], #1
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ldrcsb lr, [r1], #1
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strcsb ip, [r0], #1
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strcsb lr, [r0], #1
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movs ip, r3, lsl #29
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bge 1f
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// copies 4 bytes, destination 32-bits aligned
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vld4.8 {d0[0], d1[0], d2[0], d3[0]}, [r1]!
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vst4.8 {d0[0], d1[0], d2[0], d3[0]}, [r0, :32]!
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1: bcc 2f
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// copies 8 bytes, destination 64-bits aligned
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vld1.8 {d0}, [r1]!
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vst1.8 {d0}, [r0, :64]!
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2:
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0: /* preload immediately the next cache line, which we may need */
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pld [r1, #(32*0)]
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pld [r1, #(32*1)]
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pld [r1, #(32*2)]
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pld [r1, #(32*3)]
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/* make sure we have at least 128 bytes to copy */
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subs r2, r2, #128
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blo 2f
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/* preload all the cache lines we need.
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* NOTE: the number of pld below depends on PREFETCH_DISTANCE,
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* ideally would would increase the distance in the main loop to
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* avoid the goofy code below. In practice this doesn't seem to make
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* a big difference.
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*/
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pld [r1, #(PREFETCH_DISTANCE + 32*0)]
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pld [r1, #(PREFETCH_DISTANCE + 32*1)]
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pld [r1, #(PREFETCH_DISTANCE + 32*2)]
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pld [r1, #(PREFETCH_DISTANCE + 32*3)]
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1: /* The main loop copies 128 bytes at a time */
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vld1.8 {d0 - d3}, [r1]!
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vld1.8 {d4 - d7}, [r1]!
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vld1.8 {d16 - d19}, [r1]!
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vld1.8 {d20 - d23}, [r1]!
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pld [r1, #(PREFETCH_DISTANCE + 32*0)]
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pld [r1, #(PREFETCH_DISTANCE + 32*1)]
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pld [r1, #(PREFETCH_DISTANCE + 32*2)]
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pld [r1, #(PREFETCH_DISTANCE + 32*3)]
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subs r2, r2, #128
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vst1.8 {d0 - d3}, [r0, :128]!
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vst1.8 {d4 - d7}, [r0, :128]!
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vst1.8 {d16 - d19}, [r0, :128]!
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vst1.8 {d20 - d23}, [r0, :128]!
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bhs 1b
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2: /* fix-up the remaining count and make sure we have >= 32 bytes left */
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add r2, r2, #128
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subs r2, r2, #32
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blo 4f
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3: /* 32 bytes at a time. These cache lines were already preloaded */
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vld1.8 {d0 - d3}, [r1]!
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subs r2, r2, #32
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vst1.8 {d0 - d3}, [r0, :128]!
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bhs 3b
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4: /* less than 32 left */
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add r2, r2, #32
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tst r2, #0x10
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beq 5f
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// copies 16 bytes, 128-bits aligned
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vld1.8 {d0, d1}, [r1]!
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vst1.8 {d0, d1}, [r0, :128]!
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5: /* copy up to 15-bytes (count in r2) */
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movs ip, r2, lsl #29
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bcc 1f
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vld1.8 {d0}, [r1]!
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vst1.8 {d0}, [r0]!
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1: bge 2f
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vld4.8 {d0[0], d1[0], d2[0], d3[0]}, [r1]!
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vst4.8 {d0[0], d1[0], d2[0], d3[0]}, [r0]!
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2: movs ip, r2, lsl #31
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ldrmib r3, [r1], #1
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ldrcsb ip, [r1], #1
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ldrcsb lr, [r1], #1
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strmib r3, [r0], #1
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strcsb ip, [r0], #1
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strcsb lr, [r0], #1
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ldmfd sp!, {r0, lr}
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bx lr
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.fnend
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#else /* __ARM_ARCH__ < 7 */
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.text
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.global memcpy
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@ -40,9 +170,9 @@
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* note that memcpy() always returns the destination pointer,
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* so we have to preserve R0.
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*/
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memcpy:
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/* The stack must always be 64-bits aligned to be compliant with the
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memcpy:
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/* The stack must always be 64-bits aligned to be compliant with the
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* ARM ABI. Since we have to save R0, we might as well save R4
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* which we can use for better pipelining of the reads below
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*/
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@ -82,10 +212,10 @@ memcpy:
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strmib r3, [r0], #1
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strcsb r4, [r0], #1
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strcsb r12,[r0], #1
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src_aligned:
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/* see if src and dst are aligned together (congruent) */
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/* see if src and dst are aligned together (congruent) */
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eor r12, r0, r1
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tst r12, #3
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bne non_congruent
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@ -103,7 +233,7 @@ src_aligned:
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andhi r3, r2, #0x1C
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/* conditionnaly copies 0 to 7 words (length in r3) */
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movs r12, r3, lsl #28
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movs r12, r3, lsl #28
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ldmcsia r1!, {r4, r5, r6, r7} /* 16 bytes */
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ldmmiia r1!, {r8, r9} /* 8 bytes */
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stmcsia r0!, {r4, r5, r6, r7}
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@ -124,7 +254,7 @@ cached_aligned32:
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/*
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* We preload a cache-line up to 64 bytes ahead. On the 926, this will
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* stall only until the requested world is fetched, but the linefill
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* stall only until the requested world is fetched, but the linefill
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* continues in the the background.
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* While the linefill is going, we write our previous cache-line
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* into the write-buffer (which should have some free space).
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@ -150,19 +280,19 @@ cached_aligned32:
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// NOTE: if r12 is more than 64 ahead of r1, the following ldrhi
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// for ARM9 preload will not be safely guarded by the preceding subs.
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// When it is safely guarded the only possibility to have SIGSEGV here
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// When it is safely guarded the only possibility to have SIGSEGV here
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// is because the caller overstates the length.
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ldrhi r3, [r12], #32 /* cheap ARM9 preload */
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stmia r0!, { r4-r11 }
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bhs 1b
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add r2, r2, #32
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less_than_32_left:
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/*
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/*
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* less than 32 bytes left at this point (length in r2)
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*/
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@ -174,7 +304,7 @@ less_than_32_left:
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beq 1f
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/* conditionnaly copies 0 to 31 bytes */
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movs r12, r2, lsl #28
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movs r12, r2, lsl #28
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ldmcsia r1!, {r4, r5, r6, r7} /* 16 bytes */
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ldmmiia r1!, {r8, r9} /* 8 bytes */
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stmcsia r0!, {r4, r5, r6, r7}
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@ -182,7 +312,7 @@ less_than_32_left:
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movs r12, r2, lsl #30
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ldrcs r3, [r1], #4 /* 4 bytes */
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ldrmih r4, [r1], #2 /* 2 bytes */
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strcs r3, [r0], #4
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strcs r3, [r0], #4
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strmih r4, [r0], #2
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tst r2, #0x1
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ldrneb r3, [r1] /* last byte */
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@ -200,34 +330,34 @@ non_congruent:
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* here source is aligned to 4 bytes
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* but destination is not.
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*
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* in the code below r2 is the number of bytes read
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* in the code below r2 is the number of bytes read
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* (the number of bytes written is always smaller, because we have
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* partial words in the shift queue)
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*/
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cmp r2, #4
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blo copy_last_3_and_return
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/* Use post-incriment mode for stm to spill r5-r11 to reserved stack
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* frame. Don't update sp.
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*/
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stmea sp, {r5-r11}
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/* compute shifts needed to align src to dest */
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rsb r5, r0, #0
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and r5, r5, #3 /* r5 = # bytes in partial words */
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mov r12, r5, lsl #3 /* r12 = right */
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mov r12, r5, lsl #3 /* r12 = right */
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rsb lr, r12, #32 /* lr = left */
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/* read the first word */
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ldr r3, [r1], #4
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sub r2, r2, #4
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/* write a partial word (0 to 3 bytes), such that destination
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* becomes aligned to 32 bits (r5 = nb of words to copy for alignment)
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*/
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movs r5, r5, lsl #31
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strmib r3, [r0], #1
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movmi r3, r3, lsr #8
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movmi r3, r3, lsr #8
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strcsb r3, [r0], #1
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movcs r3, r3, lsr #8
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strcsb r3, [r0], #1
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@ -235,7 +365,7 @@ non_congruent:
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cmp r2, #4
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blo partial_word_tail
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/* Align destination to 32 bytes (cache line boundary) */
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1: tst r0, #0x1c
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beq 2f
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@ -366,7 +496,7 @@ partial_word_tail:
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strcsb r3, [r0], #1
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movcs r3, r3, lsr #8
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strcsb r3, [r0], #1
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/* Refill spilled registers from the stack. Don't update sp. */
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ldmfd sp, {r5-r11}
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@ -385,3 +515,5 @@ copy_last_3_and_return:
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bx lr
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.fnend
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#endif /* __ARM_ARCH__ < 7 */
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