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am d509f9cc: am 09ce7749: Merge "[MIPS] Clean Kernel headers are generated by running libc/kernel/tools/update_all.py script. This patch ignores any changes to libc/kernel directory not related to MIPS architecture."

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* commit 'd509f9ccbba6e1dd53acfd7425bfc06d6b3f8693':
  [MIPS] Clean Kernel headers are generated by running libc/kernel/tools/update_all.py script. This patch ignores any changes to libc/kernel directory not related to MIPS architecture.
This commit is contained in:
Elliott Hughes 2012-03-27 17:57:41 -07:00 committed by Android Git Automerger
commit ea76f41478
160 changed files with 18664 additions and 5 deletions
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39
libc/kernel/arch-mips/asm/a.out.h Normal file
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/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef _ASM_A_OUT_H
#define _ASM_A_OUT_H
struct exec
{
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
unsigned long a_info;
unsigned a_text;
unsigned a_data;
unsigned a_bss;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
unsigned a_syms;
unsigned a_entry;
unsigned a_trsize;
unsigned a_drsize;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
};
#define N_TRSIZE(a) ((a).a_trsize)
#define N_DRSIZE(a) ((a).a_drsize)
#define N_SYMSIZE(a) ((a).a_syms)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#endif

93
libc/kernel/arch-mips/asm/addrspace.h Normal file
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/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef _ASM_ADDRSPACE_H
#define _ASM_ADDRSPACE_H
#include <spaces.h>
#ifdef __ASSEMBLY__
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define _ATYPE_
#define _ATYPE32_
#define _ATYPE64_
#define _CONST64_(x) x
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#else
#define _ATYPE_ __PTRDIFF_TYPE__
#define _ATYPE32_ int
#define _ATYPE64_ __s64
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define _CONST64_(x) x ## LL
#endif
#ifdef __ASSEMBLY__
#define _ACAST32_
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define _ACAST64_
#else
#define _ACAST32_ (_ATYPE_)(_ATYPE32_)
#define _ACAST64_ (_ATYPE64_)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#endif
#define KSEGX(a) ((_ACAST32_ (a)) & 0xe0000000)
#define CPHYSADDR(a) ((_ACAST32_(a)) & 0x1fffffff)
#define XPHYSADDR(a) ((_ACAST64_(a)) & _CONST64_(0x000000ffffffffff))
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define CKSEG0ADDR(a) (CPHYSADDR(a) | KSEG0)
#define CKSEG1ADDR(a) (CPHYSADDR(a) | KSEG1)
#define CKSEG2ADDR(a) (CPHYSADDR(a) | KSEG2)
#define CKSEG3ADDR(a) (CPHYSADDR(a) | KSEG3)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define KSEG0ADDR(a) (CPHYSADDR(a) | KSEG0)
#define KSEG1ADDR(a) (CPHYSADDR(a) | KSEG1)
#define KSEG2ADDR(a) (CPHYSADDR(a) | KSEG2)
#define KSEG3ADDR(a) (CPHYSADDR(a) | KSEG3)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define KUSEG 0x00000000
#define KSEG0 0x80000000
#define KSEG1 0xa0000000
#define KSEG2 0xc0000000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define KSEG3 0xe0000000
#define CKUSEG 0x00000000
#define CKSEG0 0x80000000
#define CKSEG1 0xa0000000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define CKSEG2 0xc0000000
#define CKSEG3 0xe0000000
#define K_CALG_COH_EXCL1_NOL2 0
#define K_CALG_COH_SHRL1_NOL2 1
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define K_CALG_UNCACHED 2
#define K_CALG_NONCOHERENT 3
#define K_CALG_COH_EXCL 4
#define K_CALG_COH_SHAREABLE 5
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define K_CALG_NOTUSED 6
#define K_CALG_UNCACHED_ACCEL 7
#define PHYS_TO_XKSEG_UNCACHED(p) PHYS_TO_XKPHYS(K_CALG_UNCACHED, (p))
#define PHYS_TO_XKSEG_CACHED(p) PHYS_TO_XKPHYS(K_CALG_COH_SHAREABLE, (p))
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define XKPHYS_TO_PHYS(p) ((p) & TO_PHYS_MASK)
#define PHYS_TO_XKPHYS(cm, a) (_CONST64_(0x8000000000000000) | (_CONST64_(cm) << 59) | (a))
#define TO_PHYS_MASK _CONST64_(0x07ffffffffffffff)
#define COMPAT_K1BASE32 _CONST64_(0xffffffffa0000000)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PHYS_TO_COMPATK1(x) ((x) | COMPAT_K1BASE32)
#define KDM_TO_PHYS(x) (_ACAST64_ (x) & TO_PHYS_MASK)
#define PHYS_TO_K0(x) (_ACAST64_ (x) | CAC_BASE)
#endif
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */

263
libc/kernel/arch-mips/asm/asm.h Normal file
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/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef __ASM_ASM_H
#define __ASM_ASM_H
#include <asm/sgidefs.h>
#ifndef CAT
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#ifdef __STDC__
#define __CAT(str1, str2) str1##str2
#else
#define __CAT(str1, str2) str1 str2
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#endif
#define CAT(str1, str2) __CAT(str1, str2)
#endif
#ifdef __PIC__
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define CPRESTORE(register) .cprestore register
#define CPADD(register) .cpadd register
#define CPLOAD(register) .cpload register
#else
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define CPRESTORE(register)
#define CPADD(register)
#define CPLOAD(register)
#endif
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define LEAF(symbol) .globl symbol; .align 2; .type symbol, @function; .ent symbol, 0; symbol: .frame sp, 0, ra
#define NESTED(symbol, framesize, rpc) .globl symbol; .align 2; .type symbol, @function; .ent symbol, 0; symbol: .frame sp, framesize, rpc
#define END(function) .end function; .size function, .-function
#define EXPORT(symbol) .globl symbol; symbol:
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define FEXPORT(symbol) .globl symbol; .type symbol, @function; symbol:
#define ABS(symbol,value) .globl symbol; symbol = value
#define PANIC(msg) .set push; .set reorder; PTR_LA a0, 8f; jal panic; 9: b 9b; .set pop; TEXT(msg)
#define PRINT(string)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define TEXT(msg) .pushsection .data; 8: .asciiz msg; .popsection;
#define TTABLE(string) .pushsection .text; .word 1f; .popsection .pushsection .data; 1: .asciiz string; .popsection
#define PREF(hint, addr)
#define PREFX(hint, addr)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#if _MIPS_ISA == _MIPS_ISA_MIPS1
#define MOVN(rd, rs, rt) .set push; .set reorder; beqz rt, 9f; move rd, rs; .set pop; 9:
#define MOVZ(rd, rs, rt) .set push; .set reorder; bnez rt, 9f; move rd, rs; .set pop; 9:
#endif
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#if _MIPS_ISA == _MIPS_ISA_MIPS2 || _MIPS_ISA == _MIPS_ISA_MIPS3
#define MOVN(rd, rs, rt) .set push; .set noreorder; bnezl rt, 9f; move rd, rs; .set pop; 9:
#define MOVZ(rd, rs, rt) .set push; .set noreorder; beqzl rt, 9f; move rd, rs; .set pop; 9:
#endif
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#if _MIPS_ISA == _MIPS_ISA_MIPS4 || _MIPS_ISA == _MIPS_ISA_MIPS5 || _MIPS_ISA == _MIPS_ISA_MIPS32 || _MIPS_ISA == _MIPS_ISA_MIPS64
#define MOVN(rd, rs, rt) movn rd, rs, rt
#define MOVZ(rd, rs, rt) movz rd, rs, rt
#endif
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#if _MIPS_SIM == _MIPS_SIM_ABI32
#define ALSZ 7
#define ALMASK ~7
#endif
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#if _MIPS_SIM == _MIPS_SIM_NABI32 || _MIPS_SIM == _MIPS_SIM_ABI64
#define ALSZ 15
#define ALMASK ~15
#endif
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#ifdef __mips64
#define SZREG 8
#else
#define SZREG 4
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#endif
#if _MIPS_SIM == _MIPS_SIM_ABI32
#define REG_S sw
#define REG_L lw
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define REG_SUBU subu
#define REG_ADDU addu
#endif
#if _MIPS_SIM == _MIPS_SIM_NABI32 || _MIPS_SIM == _MIPS_SIM_ABI64
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define REG_S sd
#define REG_L ld
#define REG_SUBU dsubu
#define REG_ADDU daddu
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#endif
#if _MIPS_SZINT == 32
#define INT_ADD add
#define INT_ADDU addu
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define INT_ADDI addi
#define INT_ADDIU addiu
#define INT_SUB sub
#define INT_SUBU subu
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define INT_L lw
#define INT_S sw
#define INT_SLL sll
#define INT_SLLV sllv
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define INT_SRL srl
#define INT_SRLV srlv
#define INT_SRA sra
#define INT_SRAV srav
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#endif
#if _MIPS_SZINT == 64
#define INT_ADD dadd
#define INT_ADDU daddu
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define INT_ADDI daddi
#define INT_ADDIU daddiu
#define INT_SUB dsub
#define INT_SUBU dsubu
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define INT_L ld
#define INT_S sd
#define INT_SLL dsll
#define INT_SLLV dsllv
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define INT_SRL dsrl
#define INT_SRLV dsrlv
#define INT_SRA dsra
#define INT_SRAV dsrav
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#endif
#if _MIPS_SZLONG == 32
#define LONG_ADD add
#define LONG_ADDU addu
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define LONG_ADDI addi
#define LONG_ADDIU addiu
#define LONG_SUB sub
#define LONG_SUBU subu
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define LONG_L lw
#define LONG_S sw
#define LONG_SLL sll
#define LONG_SLLV sllv
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define LONG_SRL srl
#define LONG_SRLV srlv
#define LONG_SRA sra
#define LONG_SRAV srav
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define LONG .word
#define LONGSIZE 4
#define LONGMASK 3
#define LONGLOG 2
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#endif
#if _MIPS_SZLONG == 64
#define LONG_ADD dadd
#define LONG_ADDU daddu
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define LONG_ADDI daddi
#define LONG_ADDIU daddiu
#define LONG_SUB dsub
#define LONG_SUBU dsubu
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define LONG_L ld
#define LONG_S sd
#define LONG_SLL dsll
#define LONG_SLLV dsllv
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define LONG_SRL dsrl
#define LONG_SRLV dsrlv
#define LONG_SRA dsra
#define LONG_SRAV dsrav
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define LONG .dword
#define LONGSIZE 8
#define LONGMASK 7
#define LONGLOG 3
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#endif
#if _MIPS_SZPTR == 32
#define PTR_ADD add
#define PTR_ADDU addu
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PTR_ADDI addi
#define PTR_ADDIU addiu
#define PTR_SUB sub
#define PTR_SUBU subu
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PTR_L lw
#define PTR_S sw
#define PTR_LA la
#define PTR_LI li
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PTR_SLL sll
#define PTR_SLLV sllv
#define PTR_SRL srl
#define PTR_SRLV srlv
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PTR_SRA sra
#define PTR_SRAV srav
#define PTR_SCALESHIFT 2
#define PTR .word
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PTRSIZE 4
#define PTRLOG 2
#endif
#if _MIPS_SZPTR == 64
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PTR_ADD dadd
#define PTR_ADDU daddu
#define PTR_ADDI daddi
#define PTR_ADDIU daddiu
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PTR_SUB dsub
#define PTR_SUBU dsubu
#define PTR_L ld
#define PTR_S sd
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PTR_LA dla
#define PTR_LI dli
#define PTR_SLL dsll
#define PTR_SLLV dsllv
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PTR_SRL dsrl
#define PTR_SRLV dsrlv
#define PTR_SRA dsra
#define PTR_SRAV dsrav
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PTR_SCALESHIFT 3
#define PTR .dword
#define PTRSIZE 8
#define PTRLOG 3
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#endif
#if _MIPS_SIM == _MIPS_SIM_ABI32
#define MFC0 mfc0
#define MTC0 mtc0
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#endif
#if _MIPS_SIM == _MIPS_SIM_NABI32 || _MIPS_SIM == _MIPS_SIM_ABI64
#define MFC0 dmfc0
#define MTC0 dmtc0
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#endif
#define SSNOP sll zero, zero, 1
#define R10KCBARRIER(addr)
#endif
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */

23
libc/kernel/arch-mips/asm/asmmacro.h Normal file
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/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef _ASM_ASMMACRO_H
#define _ASM_ASMMACRO_H
#include <asm/hazards.h>
#endif
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */

54
libc/kernel/arch-mips/asm/atomic.h Normal file
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/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef _ASM_ATOMIC_H
#define _ASM_ATOMIC_H
#include <linux/irqflags.h>
#include <asm/barrier.h>
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#include <asm/cpu-features.h>
#include <asm/war.h>
#include <asm/system.h>
typedef struct { volatile int counter; } atomic_t;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define ATOMIC_INIT(i) { (i) }
#define atomic_read(v) ((v)->counter)
#define atomic_set(v, i) ((v)->counter = (i))
#define atomic_cmpxchg(v, o, n) (cmpxchg(&((v)->counter), (o), (n)))
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define atomic_xchg(v, new) (xchg(&((v)->counter), (new)))
#define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0)
#define atomic_dec_return(v) atomic_sub_return(1, (v))
#define atomic_inc_return(v) atomic_add_return(1, (v))
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define atomic_sub_and_test(i, v) (atomic_sub_return((i), (v)) == 0)
#define atomic_inc_and_test(v) (atomic_inc_return(v) == 0)
#define atomic_dec_and_test(v) (atomic_sub_return(1, (v)) == 0)
#define atomic_dec_if_positive(v) atomic_sub_if_positive(1, v)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define atomic_inc(v) atomic_add(1, (v))
#define atomic_dec(v) atomic_sub(1, (v))
#define atomic_add_negative(i, v) (atomic_add_return(i, (v)) < 0)
#define smp_mb__before_atomic_dec() smp_llsc_mb()
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define smp_mb__after_atomic_dec() smp_llsc_mb()
#define smp_mb__before_atomic_inc() smp_llsc_mb()
#define smp_mb__after_atomic_inc() smp_llsc_mb()
#include <asm-generic/atomic.h>
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#endif

21
libc/kernel/arch-mips/asm/auxvec.h Normal file
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/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef _ASM_AUXVEC_H
#define _ASM_AUXVEC_H
#endif

48
libc/kernel/arch-mips/asm/barrier.h Normal file
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/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef __ASM_BARRIER_H
#define __ASM_BARRIER_H
#define read_barrier_depends() do { } while(0)
#define smp_read_barrier_depends() do { } while(0)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define __sync() do { } while(0)
#define __fast_iob() __asm__ __volatile__( ".set push\n\t" ".set noreorder\n\t" "lw $0,%0\n\t" "nop\n\t" ".set pop" : : "m" (*(int *)CKSEG1) : "memory")
#define fast_wmb() __sync()
#define fast_rmb() __sync()
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define fast_mb() __sync()
#define fast_iob() do { __sync(); __fast_iob(); } while (0)
#define wmb() fast_wmb()
#define rmb() fast_rmb()
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define mb() fast_mb()
#define iob() fast_iob()
#define __WEAK_ORDERING_MB " \n"
#define __WEAK_LLSC_MB " \n"
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define smp_mb() __asm__ __volatile__(__WEAK_ORDERING_MB : : :"memory")
#define smp_rmb() __asm__ __volatile__(__WEAK_ORDERING_MB : : :"memory")
#define smp_wmb() __asm__ __volatile__(__WEAK_ORDERING_MB : : :"memory")
#define set_mb(var, value) do { var = value; smp_mb(); } while (0)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define smp_llsc_mb() __asm__ __volatile__(__WEAK_LLSC_MB : : :"memory")
#define smp_llsc_rmb() __asm__ __volatile__(__WEAK_LLSC_MB : : :"memory")
#define smp_llsc_wmb() __asm__ __volatile__(__WEAK_LLSC_MB : : :"memory")
#endif
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */

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/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef _ASM_BITOPS_H
#define _ASM_BITOPS_H
#ifndef _LINUX_BITOPS_H
#error only <linux/bitops.h> can be included directly
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#endif
#include <linux/compiler.h>
#include <linux/irqflags.h>
#include <linux/types.h>
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#include <asm/barrier.h>
#include <asm/bug.h>
#include <asm/byteorder.h>
#include <asm/cpu-features.h>
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#include <asm/sgidefs.h>
#include <asm/war.h>
#if _MIPS_SZLONG == 32
#define SZLONG_LOG 5
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SZLONG_MASK 31UL
#define __LL "ll "
#define __SC "sc "
#define __INS "ins "
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define __EXT "ext "
#elif _MIPS_SZLONG == 64
#define SZLONG_LOG 6
#define SZLONG_MASK 63UL
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define __LL "lld "
#define __SC "scd "
#define __INS "dins "
#define __EXT "dext "
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#endif
#define smp_mb__before_clear_bit() smp_llsc_mb()
#define smp_mb__after_clear_bit() smp_llsc_mb()
#include <asm-generic/bitops/non-atomic.h>
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#include <asm-generic/bitops/__ffs.h>
#include <asm-generic/bitops/__fls.h>
#include <asm-generic/bitops/ffs.h>
#include <asm-generic/bitops/fls.h>
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#include <asm-generic/bitops/fls64.h>
#include <asm-generic/bitops/ffz.h>
#include <asm-generic/bitops/find.h>
#endif
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */

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libc/kernel/arch-mips/asm/bootinfo.h Normal file
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/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef _ASM_BOOTINFO_H
#define _ASM_BOOTINFO_H
#include <linux/types.h>
#include <asm/setup.h>
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MACH_UNKNOWN 0
#define MACH_DSUNKNOWN 0
#define MACH_DS23100 1
#define MACH_DS5100 2
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MACH_DS5000_200 3
#define MACH_DS5000_1XX 4
#define MACH_DS5000_XX 5
#define MACH_DS5000_2X0 6
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MACH_DS5400 7
#define MACH_DS5500 8
#define MACH_DS5800 9
#define MACH_DS5900 10
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MACH_MSP4200_EVAL 0
#define MACH_MSP4200_GW 1
#define MACH_MSP4200_FPGA 2
#define MACH_MSP7120_EVAL 3
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MACH_MSP7120_GW 4
#define MACH_MSP7120_FPGA 5
#define MACH_MSP_OTHER 255
#define MACH_MIKROTIK_RB532 0
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MACH_MIKROTIK_RB532A 1
#define CL_SIZE COMMAND_LINE_SIZE
#define BOOT_MEM_MAP_MAX 32
#define BOOT_MEM_RAM 1
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BOOT_MEM_ROM_DATA 2
#define BOOT_MEM_RESERVED 3
struct boot_mem_map {
int nr_map;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
struct boot_mem_map_entry {
phys_t addr;
phys_t size;
long type;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
} map[BOOT_MEM_MAP_MAX];
};
#endif

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libc/kernel/arch-mips/asm/bug.h Normal file
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/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef __ASM_BUG_H
#define __ASM_BUG_H
#include <asm/sgidefs.h>
#include <asm-generic/bug.h>
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#endif

40
libc/kernel/arch-mips/asm/byteorder.h Normal file
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/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef _ASM_BYTEORDER_H
#define _ASM_BYTEORDER_H
#include <linux/compiler.h>
#include <asm/types.h>
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#ifdef __GNUC__
#ifndef __STRICT_ANSI__
#define __BYTEORDER_HAS_U64__
#define __SWAB_64_THRU_32__
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#endif
#endif
#ifdef __MIPSEB__
#include <linux/byteorder/big_endian.h>
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#elif defined(__MIPSEL__)
#include <linux/byteorder/little_endian.h>
#else
#error "MIPS, but neither __MIPSEB__, nor __MIPSEL__???"
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#endif
#endif

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libc/kernel/arch-mips/asm/cache.h Normal file
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/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef _ASM_CACHE_H
#define _ASM_CACHE_H
#include <kmalloc.h>
#define L1_CACHE_SHIFT CONFIG_MIPS_L1_CACHE_SHIFT
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
#define SMP_CACHE_SHIFT L1_CACHE_SHIFT
#define SMP_CACHE_BYTES L1_CACHE_BYTES
#endif
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */

28
libc/kernel/arch-mips/asm/cachectl.h Normal file
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/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef _ASM_CACHECTL
#define _ASM_CACHECTL
#define ICACHE (1<<0)
#define DCACHE (1<<1)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BCACHE (ICACHE|DCACHE)
#define CACHEABLE 0
#define UNCACHEABLE 1
#endif
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */

34
libc/kernel/arch-mips/asm/cacheflush.h Normal file
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/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef _ASM_CACHEFLUSH_H
#define _ASM_CACHEFLUSH_H
#include <linux/mm.h>
#include <asm/cpu-features.h>
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define flush_cache_dup_mm(mm) do { (void) (mm); } while (0)
#define flush_dcache_mmap_lock(mapping) do { } while (0)
#define flush_dcache_mmap_unlock(mapping) do { } while (0)
#define ARCH_HAS_FLUSH_ANON_PAGE
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PG_dcache_dirty PG_arch_1
#define Page_dcache_dirty(page) test_bit(PG_dcache_dirty, &(page)->flags)
#define SetPageDcacheDirty(page) set_bit(PG_dcache_dirty, &(page)->flags)
#define ClearPageDcacheDirty(page) clear_bit(PG_dcache_dirty, &(page)->flags)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#endif

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libc/kernel/arch-mips/asm/cacheops.h Normal file
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/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef __ASM_CACHEOPS_H
#define __ASM_CACHEOPS_H
#define Index_Invalidate_I 0x00
#define Index_Writeback_Inv_D 0x01
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define Index_Load_Tag_I 0x04
#define Index_Load_Tag_D 0x05
#define Index_Store_Tag_I 0x08
#define Index_Store_Tag_D 0x09
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define Hit_Invalidate_I 0x10
#define Hit_Invalidate_D 0x11
#define Hit_Writeback_Inv_D 0x15
#define Create_Dirty_Excl_D 0x0d
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define Fill 0x14
#define Hit_Writeback_I 0x18
#define Hit_Writeback_D 0x19
#define Index_Invalidate_SI 0x02
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define Index_Writeback_Inv_SD 0x03
#define Index_Load_Tag_SI 0x06
#define Index_Load_Tag_SD 0x07
#define Index_Store_Tag_SI 0x0A
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define Index_Store_Tag_SD 0x0B
#define Create_Dirty_Excl_SD 0x0f
#define Hit_Invalidate_SI 0x12
#define Hit_Invalidate_SD 0x13
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define Hit_Writeback_Inv_SD 0x17
#define Hit_Writeback_SD 0x1b
#define Hit_Set_Virtual_SI 0x1e
#define Hit_Set_Virtual_SD 0x1f
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define R5K_Page_Invalidate_S 0x17
#define Page_Invalidate_T 0x16
#define Index_Writeback_Inv_S 0x03
#define Index_Load_Tag_S 0x07
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define Index_Store_Tag_S 0x0B
#define Hit_Invalidate_S 0x13
#define Cache_Barrier 0x14
#define Hit_Writeback_Inv_S 0x17
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define Index_Load_Data_I 0x18
#define Index_Load_Data_D 0x19
#define Index_Load_Data_S 0x1b
#define Index_Store_Data_I 0x1c
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define Index_Store_Data_D 0x1d
#define Index_Store_Data_S 0x1f
#endif

30
libc/kernel/arch-mips/asm/checksum.h Normal file
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/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef _ASM_CHECKSUM_H
#define _ASM_CHECKSUM_H
#include <linux/in6.h>
#include <asm/uaccess.h>
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define HAVE_CSUM_COPY_USER
#ifdef __MIPSEL__
#else
#endif
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define _HAVE_ARCH_IPV6_CSUM
#endif

33
libc/kernel/arch-mips/asm/cmpxchg.h Normal file
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/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef __ASM_CMPXCHG_H
#define __ASM_CMPXCHG_H
#include <linux/irqflags.h>
#define __HAVE_ARCH_CMPXCHG 1
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define __cmpxchg_asm(ld, st, m, old, new) ({ __typeof(*(m)) __ret; if (cpu_has_llsc && R10000_LLSC_WAR) { __asm__ __volatile__( " .set push \n" " .set noat \n" " .set mips3 \n" "1: " ld " %0, %2 # __cmpxchg_asm \n" " bne %0, %z3, 2f \n" " .set mips0 \n" " move $1, %z4 \n" " .set mips3 \n" " " st " $1, %1 \n" " beqzl $1, 1b \n" "2: \n" " .set pop \n" : "=&r" (__ret), "=R" (*m) : "R" (*m), "Jr" (old), "Jr" (new) : "memory"); } else if (cpu_has_llsc) { __asm__ __volatile__( " .set push \n" " .set noat \n" " .set mips3 \n" "1: " ld " %0, %2 # __cmpxchg_asm \n" " bne %0, %z3, 2f \n" " .set mips0 \n" " move $1, %z4 \n" " .set mips3 \n" " " st " $1, %1 \n" " beqz $1, 3f \n" "2: \n" " .subsection 2 \n" "3: b 1b \n" " .previous \n" " .set pop \n" : "=&r" (__ret), "=R" (*m) : "R" (*m), "Jr" (old), "Jr" (new) : "memory"); } else { unsigned long __flags; raw_local_irq_save(__flags); __ret = *m; if (__ret == old) *m = new; raw_local_irq_restore(__flags); } __ret; })
#define __cmpxchg(ptr, old, new, barrier) ({ __typeof__(ptr) __ptr = (ptr); __typeof__(*(ptr)) __old = (old); __typeof__(*(ptr)) __new = (new); __typeof__(*(ptr)) __res = 0; barrier; switch (sizeof(*(__ptr))) { case 4: __res = __cmpxchg_asm("ll", "sc", __ptr, __old, __new); break; case 8: if (sizeof(long) == 8) { __res = __cmpxchg_asm("lld", "scd", __ptr, __old, __new); break; } default: __cmpxchg_called_with_bad_pointer(); break; } barrier; __res; })
#define cmpxchg(ptr, old, new) __cmpxchg(ptr, old, new, smp_llsc_mb())
#define cmpxchg_local(ptr, old, new) __cmpxchg(ptr, old, new, )
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define cmpxchg64(ptr, o, n) ({ BUILD_BUG_ON(sizeof(*(ptr)) != 8); cmpxchg((ptr), (o), (n)); })
#include <asm-generic/cmpxchg-local.h>
#define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
#endif
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */

30
libc/kernel/arch-mips/asm/compiler.h Normal file
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/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef _ASM_COMPILER_H
#define _ASM_COMPILER_H
#if __GNUC__ > (3 || __GNUC__ == (3 && __GNUC_MINOR__ >= 4))
#define GCC_IMM_ASM() "n"
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define GCC_REG_ACCUM "$0"
#else
#define GCC_IMM_ASM() "rn"
#define GCC_REG_ACCUM "accum"
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#endif
#endif

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libc/kernel/arch-mips/asm/cpu-features.h Normal file
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/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef __ASM_CPU_FEATURES_H
#define __ASM_CPU_FEATURES_H
#include <asm/cpu.h>
#include <asm/cpu-info.h>
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#include <cpu-feature-overrides.h>
#ifndef current_cpu_type
#define current_cpu_type() current_cpu_data.cputype
#endif
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#ifndef cpu_has_tlb
#define cpu_has_tlb (cpu_data[0].options & MIPS_CPU_TLB)
#endif
#ifndef cpu_has_4kex
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define cpu_has_4kex (cpu_data[0].options & MIPS_CPU_4KEX)
#endif
#ifndef cpu_has_3k_cache
#define cpu_has_3k_cache (cpu_data[0].options & MIPS_CPU_3K_CACHE)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#endif
#define cpu_has_6k_cache 0
#define cpu_has_8k_cache 0
#ifndef cpu_has_4k_cache
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define cpu_has_4k_cache (cpu_data[0].options & MIPS_CPU_4K_CACHE)
#endif
#ifndef cpu_has_tx39_cache
#define cpu_has_tx39_cache (cpu_data[0].options & MIPS_CPU_TX39_CACHE)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#endif
#ifndef cpu_has_fpu
#define cpu_has_fpu (current_cpu_data.options & MIPS_CPU_FPU)
#define raw_cpu_has_fpu (raw_current_cpu_data.options & MIPS_CPU_FPU)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#else
#define raw_cpu_has_fpu cpu_has_fpu
#endif
#ifndef cpu_has_32fpr
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define cpu_has_32fpr (cpu_data[0].options & MIPS_CPU_32FPR)
#endif
#ifndef cpu_has_counter
#define cpu_has_counter (cpu_data[0].options & MIPS_CPU_COUNTER)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#endif
#ifndef cpu_has_watch
#define cpu_has_watch (cpu_data[0].options & MIPS_CPU_WATCH)
#endif
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#ifndef cpu_has_divec
#define cpu_has_divec (cpu_data[0].options & MIPS_CPU_DIVEC)
#endif
#ifndef cpu_has_vce
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define cpu_has_vce (cpu_data[0].options & MIPS_CPU_VCE)
#endif
#ifndef cpu_has_cache_cdex_p
#define cpu_has_cache_cdex_p (cpu_data[0].options & MIPS_CPU_CACHE_CDEX_P)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#endif
#ifndef cpu_has_cache_cdex_s
#define cpu_has_cache_cdex_s (cpu_data[0].options & MIPS_CPU_CACHE_CDEX_S)
#endif
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#ifndef cpu_has_prefetch
#define cpu_has_prefetch (cpu_data[0].options & MIPS_CPU_PREFETCH)
#endif
#ifndef cpu_has_mcheck
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define cpu_has_mcheck (cpu_data[0].options & MIPS_CPU_MCHECK)
#endif
#ifndef cpu_has_ejtag
#define cpu_has_ejtag (cpu_data[0].options & MIPS_CPU_EJTAG)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#endif
#ifndef cpu_has_llsc
#define cpu_has_llsc (cpu_data[0].options & MIPS_CPU_LLSC)
#endif
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#ifndef cpu_has_mips16
#define cpu_has_mips16 (cpu_data[0].ases & MIPS_ASE_MIPS16)
#endif
#ifndef cpu_has_mdmx
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define cpu_has_mdmx (cpu_data[0].ases & MIPS_ASE_MDMX)
#endif
#ifndef cpu_has_mips3d
#define cpu_has_mips3d (cpu_data[0].ases & MIPS_ASE_MIPS3D)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#endif
#ifndef cpu_has_smartmips
#define cpu_has_smartmips (cpu_data[0].ases & MIPS_ASE_SMARTMIPS)
#endif
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#ifndef cpu_has_vtag_icache
#define cpu_has_vtag_icache (cpu_data[0].icache.flags & MIPS_CACHE_VTAG)
#endif
#ifndef cpu_has_dc_aliases
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define cpu_has_dc_aliases (cpu_data[0].dcache.flags & MIPS_CACHE_ALIASES)
#endif
#ifndef cpu_has_ic_fills_f_dc
#define cpu_has_ic_fills_f_dc (cpu_data[0].icache.flags & MIPS_CACHE_IC_F_DC)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#endif
#ifndef cpu_has_pindexed_dcache
#define cpu_has_pindexed_dcache (cpu_data[0].dcache.flags & MIPS_CACHE_PINDEX)
#endif
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#ifndef cpu_icache_snoops_remote_store
#define cpu_icache_snoops_remote_store 1
#endif
#ifndef cpu_has_mips32r1
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define cpu_has_mips32r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R1)
#endif
#ifndef cpu_has_mips32r2
#define cpu_has_mips32r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R2)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#endif
#ifndef cpu_has_mips64r1
#define cpu_has_mips64r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R1)
#endif
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#ifndef cpu_has_mips64r2
#define cpu_has_mips64r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R2)
#endif
#define cpu_has_mips32 (cpu_has_mips32r1 | cpu_has_mips32r2)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define cpu_has_mips64 (cpu_has_mips64r1 | cpu_has_mips64r2)
#define cpu_has_mips_r1 (cpu_has_mips32r1 | cpu_has_mips64r1)
#define cpu_has_mips_r2 (cpu_has_mips32r2 | cpu_has_mips64r2)
#ifndef cpu_has_dsp
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define cpu_has_dsp (cpu_data[0].ases & MIPS_ASE_DSP)
#endif
#ifndef cpu_has_mipsmt
#define cpu_has_mipsmt (cpu_data[0].ases & MIPS_ASE_MIPSMT)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#endif
#ifndef cpu_has_userlocal
#define cpu_has_userlocal (cpu_data[0].options & MIPS_CPU_ULRI)
#endif
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#ifndef cpu_has_vint
#define cpu_has_vint 0
#endif
#ifndef cpu_has_veic
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define cpu_has_veic 0
#endif
#ifndef cpu_has_inclusive_pcaches
#define cpu_has_inclusive_pcaches (cpu_data[0].options & MIPS_CPU_INCLUSIVE_CACHES)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#endif
#ifndef cpu_dcache_line_size
#define cpu_dcache_line_size() cpu_data[0].dcache.linesz
#endif
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#ifndef cpu_icache_line_size
#define cpu_icache_line_size() cpu_data[0].icache.linesz
#endif
#ifndef cpu_scache_line_size
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define cpu_scache_line_size() cpu_data[0].scache.linesz
#endif
#endif

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/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef __ASM_CPU_INFO_H
#define __ASM_CPU_INFO_H
#include <asm/cache.h>
struct cache_desc {
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
unsigned int waysize;
unsigned short sets;
unsigned char ways;
unsigned char linesz;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
unsigned char waybit;
unsigned char flags;
};
#define MIPS_CACHE_NOT_PRESENT 0x00000001
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MIPS_CACHE_VTAG 0x00000002
#define MIPS_CACHE_ALIASES 0x00000004
#define MIPS_CACHE_IC_F_DC 0x00000008
#define MIPS_IC_SNOOPS_REMOTE 0x00000010
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MIPS_CACHE_PINDEX 0x00000020
struct cpuinfo_mips {
unsigned long udelay_val;
unsigned long asid_cache;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
unsigned long options;
unsigned long ases;
unsigned int processor_id;
unsigned int fpu_id;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
unsigned int cputype;
int isa_level;
int tlbsize;
struct cache_desc icache;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
struct cache_desc dcache;
struct cache_desc scache;
struct cache_desc tcache;
int srsets;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
int core;
void *data;
} __attribute__((aligned(SMP_CACHE_BYTES)));
#define current_cpu_data cpu_data[smp_processor_id()]
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define raw_current_cpu_data cpu_data[raw_smp_processor_id()]
#define cpu_name_string() __cpu_name[smp_processor_id()]
#endif

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/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef _ASM_CPU_H
#define _ASM_CPU_H
#define PRID_COMP_LEGACY 0x000000
#define PRID_COMP_MIPS 0x010000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PRID_COMP_BROADCOM 0x020000
#define PRID_COMP_ALCHEMY 0x030000
#define PRID_COMP_SIBYTE 0x040000
#define PRID_COMP_SANDCRAFT 0x050000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PRID_COMP_NXP 0x060000
#define PRID_COMP_TOSHIBA 0x070000
#define PRID_COMP_LSI 0x080000
#define PRID_COMP_LEXRA 0x0b0000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PRID_IMP_R2000 0x0100
#define PRID_IMP_AU1_REV1 0x0100
#define PRID_IMP_AU1_REV2 0x0200
#define PRID_IMP_R3000 0x0200
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PRID_IMP_R6000 0x0300
#define PRID_IMP_R4000 0x0400
#define PRID_IMP_R6000A 0x0600
#define PRID_IMP_R10000 0x0900
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PRID_IMP_R4300 0x0b00
#define PRID_IMP_VR41XX 0x0c00
#define PRID_IMP_R12000 0x0e00
#define PRID_IMP_R14000 0x0f00
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PRID_IMP_R8000 0x1000
#define PRID_IMP_PR4450 0x1200
#define PRID_IMP_R4600 0x2000
#define PRID_IMP_R4700 0x2100
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PRID_IMP_TX39 0x2200
#define PRID_IMP_R4640 0x2200
#define PRID_IMP_R4650 0x2200
#define PRID_IMP_R5000 0x2300
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PRID_IMP_TX49 0x2d00
#define PRID_IMP_SONIC 0x2400
#define PRID_IMP_MAGIC 0x2500
#define PRID_IMP_RM7000 0x2700
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PRID_IMP_NEVADA 0x2800
#define PRID_IMP_RM9000 0x3400
#define PRID_IMP_LOONGSON1 0x4200
#define PRID_IMP_R5432 0x5400
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PRID_IMP_R5500 0x5500
#define PRID_IMP_LOONGSON2 0x6300
#define PRID_IMP_UNKNOWN 0xff00
#define PRID_IMP_4KC 0x8000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PRID_IMP_5KC 0x8100
#define PRID_IMP_20KC 0x8200
#define PRID_IMP_4KEC 0x8400
#define PRID_IMP_4KSC 0x8600
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PRID_IMP_25KF 0x8800
#define PRID_IMP_5KE 0x8900
#define PRID_IMP_4KECR2 0x9000
#define PRID_IMP_4KEMPR2 0x9100
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PRID_IMP_4KSD 0x9200
#define PRID_IMP_24K 0x9300
#define PRID_IMP_34K 0x9500
#define PRID_IMP_24KE 0x9600
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PRID_IMP_74K 0x9700
#define PRID_IMP_1004K 0x9900
#define PRID_IMP_SB1 0x0100
#define PRID_IMP_SB1A 0x1100
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PRID_IMP_SR71000 0x0400
#define PRID_IMP_BCM4710 0x4000
#define PRID_IMP_BCM3302 0x9000
#define PRID_REV_MASK 0x00ff
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PRID_REV_TX4927 0x0022
#define PRID_REV_TX4937 0x0030
#define PRID_REV_R4400 0x0040
#define PRID_REV_R3000A 0x0030
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PRID_REV_R3000 0x0020
#define PRID_REV_R2000A 0x0010
#define PRID_REV_TX3912 0x0010
#define PRID_REV_TX3922 0x0030
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PRID_REV_TX3927 0x0040
#define PRID_REV_VR4111 0x0050
#define PRID_REV_VR4181 0x0050
#define PRID_REV_VR4121 0x0060
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PRID_REV_VR4122 0x0070
#define PRID_REV_VR4181A 0x0070
#define PRID_REV_VR4130 0x0080
#define PRID_REV_34K_V1_0_2 0x0022
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PRID_REV_ENCODE_44(ver, rev) ((ver) << 4 | (rev))
#define PRID_REV_ENCODE_332(ver, rev, patch) ((ver) << 5 | (rev) << 2 | (patch))
#define FPIR_IMP_NONE 0x0000
enum cpu_type_enum {
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
CPU_UNKNOWN,
CPU_R2000, CPU_R3000, CPU_R3000A, CPU_R3041, CPU_R3051, CPU_R3052,
CPU_R3081, CPU_R3081E,
CPU_R6000, CPU_R6000A,
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
CPU_R4000PC, CPU_R4000SC, CPU_R4000MC, CPU_R4200, CPU_R4300, CPU_R4310,
CPU_R4400PC, CPU_R4400SC, CPU_R4400MC, CPU_R4600, CPU_R4640, CPU_R4650,
CPU_R4700, CPU_R5000, CPU_R5000A, CPU_R5500, CPU_NEVADA, CPU_R5432,
CPU_R10000, CPU_R12000, CPU_R14000, CPU_VR41XX, CPU_VR4111, CPU_VR4121,
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
CPU_VR4122, CPU_VR4131, CPU_VR4133, CPU_VR4181, CPU_VR4181A, CPU_RM7000,
CPU_SR71000, CPU_RM9000, CPU_TX49XX,
CPU_R8000,
CPU_TX3912, CPU_TX3922, CPU_TX3927,
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K,
CPU_AU1000, CPU_AU1100, CPU_AU1200, CPU_AU1210, CPU_AU1250, CPU_AU1500,
CPU_AU1550, CPU_PR4450, CPU_BCM3302, CPU_BCM4710,
CPU_5KC, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2,
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
CPU_LAST
};
#define MIPS_CPU_ISA_I 0x00000001
#define MIPS_CPU_ISA_II 0x00000002
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MIPS_CPU_ISA_III 0x00000004
#define MIPS_CPU_ISA_IV 0x00000008
#define MIPS_CPU_ISA_V 0x00000010
#define MIPS_CPU_ISA_M32R1 0x00000020
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MIPS_CPU_ISA_M32R2 0x00000040
#define MIPS_CPU_ISA_M64R1 0x00000080
#define MIPS_CPU_ISA_M64R2 0x00000100
#define MIPS_CPU_ISA_32BIT (MIPS_CPU_ISA_I | MIPS_CPU_ISA_II | MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 )
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MIPS_CPU_ISA_64BIT (MIPS_CPU_ISA_III | MIPS_CPU_ISA_IV | MIPS_CPU_ISA_V | MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)
#define MIPS_CPU_TLB 0x00000001
#define MIPS_CPU_4KEX 0x00000002
#define MIPS_CPU_3K_CACHE 0x00000004
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MIPS_CPU_4K_CACHE 0x00000008
#define MIPS_CPU_TX39_CACHE 0x00000010
#define MIPS_CPU_FPU 0x00000020
#define MIPS_CPU_32FPR 0x00000040
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MIPS_CPU_COUNTER 0x00000080
#define MIPS_CPU_WATCH 0x00000100
#define MIPS_CPU_DIVEC 0x00000200
#define MIPS_CPU_VCE 0x00000400
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MIPS_CPU_CACHE_CDEX_P 0x00000800
#define MIPS_CPU_CACHE_CDEX_S 0x00001000
#define MIPS_CPU_MCHECK 0x00002000
#define MIPS_CPU_EJTAG 0x00004000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MIPS_CPU_NOFPUEX 0x00008000
#define MIPS_CPU_LLSC 0x00010000
#define MIPS_CPU_INCLUSIVE_CACHES 0x00020000
#define MIPS_CPU_PREFETCH 0x00040000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MIPS_CPU_VINT 0x00080000
#define MIPS_CPU_VEIC 0x00100000
#define MIPS_CPU_ULRI 0x00200000
#define MIPS_ASE_MIPS16 0x00000001
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MIPS_ASE_MDMX 0x00000002
#define MIPS_ASE_MIPS3D 0x00000004
#define MIPS_ASE_SMARTMIPS 0x00000008
#define MIPS_ASE_DSP 0x00000010
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MIPS_ASE_MIPSMT 0x00000020
#endif

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/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef __MIPS_CPUTIME_H
#define __MIPS_CPUTIME_H
#include <asm-generic/cputime.h>
#endif
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */

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/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef _ASM_CURRENT_H
#define _ASM_CURRENT_H
#include <linux/thread_info.h>
struct task_struct;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define current get_current()
#endif

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/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef _ASM_DEBUG_H
#define _ASM_DEBUG_H
#define db_assert(x)
#define db_warn(x)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define db_verify(x, y) x
#define db_verify_warn(x, y) x
#define db_run(x)
#endif
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */

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/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef __ASM_MIPS_DEC_ECC_H
#define __ASM_MIPS_DEC_ECC_H
#define KN0X_EAR_VALID (1<<31)
#define KN0X_EAR_CPU (1<<30)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define KN0X_EAR_WRITE (1<<29)
#define KN0X_EAR_ECCERR (1<<28)
#define KN0X_EAR_RES_27 (1<<27)
#define KN0X_EAR_ADDRESS (0x7ffffff<<0)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define KN0X_ESR_VLDHI (1<<31)
#define KN0X_ESR_CHKHI (0x7f<<24)
#define KN0X_ESR_SNGHI (1<<23)
#define KN0X_ESR_SYNHI (0x7f<<16)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define KN0X_ESR_VLDLO (1<<15)
#define KN0X_ESR_CHKLO (0x7f<<8)
#define KN0X_ESR_SNGLO (1<<7)
#define KN0X_ESR_SYNLO (0x7f<<0)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#ifndef __ASSEMBLY__
#include <linux/interrupt.h>
struct pt_regs;
#endif
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#endif

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/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef __ASM_MIPS_DEC_IOASIC_ADDRS_H
#define __ASM_MIPS_DEC_IOASIC_ADDRS_H
#define IOASIC_SLOT_SIZE 0x00040000
#define IOASIC_SYS_ROM (0*IOASIC_SLOT_SIZE)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IOASIC_IOCTL (1*IOASIC_SLOT_SIZE)
#define IOASIC_ESAR (2*IOASIC_SLOT_SIZE)
#define IOASIC_LANCE (3*IOASIC_SLOT_SIZE)
#define IOASIC_SCC0 (4*IOASIC_SLOT_SIZE)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IOASIC_VDAC_HI (5*IOASIC_SLOT_SIZE)
#define IOASIC_SCC1 (6*IOASIC_SLOT_SIZE)
#define IOASIC_VDAC_LO (7*IOASIC_SLOT_SIZE)
#define IOASIC_TOY (8*IOASIC_SLOT_SIZE)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IOASIC_ISDN (9*IOASIC_SLOT_SIZE)
#define IOASIC_ERRADDR (9*IOASIC_SLOT_SIZE)
#define IOASIC_CHKSYN (10*IOASIC_SLOT_SIZE)
#define IOASIC_ACC_BUS (10*IOASIC_SLOT_SIZE)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IOASIC_MCR (11*IOASIC_SLOT_SIZE)
#define IOASIC_FLOPPY (11*IOASIC_SLOT_SIZE)
#define IOASIC_SCSI (12*IOASIC_SLOT_SIZE)
#define IOASIC_FDC_DMA (13*IOASIC_SLOT_SIZE)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IOASIC_SCSI_DMA (14*IOASIC_SLOT_SIZE)
#define IOASIC_RES_15 (15*IOASIC_SLOT_SIZE)
#define IO_REG_SCSI_DMA_P 0x00
#define IO_REG_SCSI_DMA_BP 0x10
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IO_REG_LANCE_DMA_P 0x20
#define IO_REG_SCC0A_T_DMA_P 0x30
#define IO_REG_SCC0A_R_DMA_P 0x40
#define IO_REG_SCC1A_T_DMA_P 0x50
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IO_REG_SCC1A_R_DMA_P 0x60
#define IO_REG_AB_T_DMA_P 0x50
#define IO_REG_AB_R_DMA_P 0x60
#define IO_REG_FLOPPY_DMA_P 0x70
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IO_REG_ISDN_T_DMA_P 0x80
#define IO_REG_ISDN_T_DMA_BP 0x90
#define IO_REG_ISDN_R_DMA_P 0xa0
#define IO_REG_ISDN_R_DMA_BP 0xb0
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IO_REG_DATA_0 0xc0
#define IO_REG_DATA_1 0xd0
#define IO_REG_DATA_2 0xe0
#define IO_REG_DATA_3 0xf0
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IO_REG_SSR 0x100
#define IO_REG_SIR 0x110
#define IO_REG_SIMR 0x120
#define IO_REG_SAR 0x130
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IO_REG_ISDN_T_DATA 0x140
#define IO_REG_ISDN_R_DATA 0x150
#define IO_REG_LANCE_SLOT 0x160
#define IO_REG_SCSI_SLOT 0x170
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IO_REG_SCC0A_SLOT 0x180
#define IO_REG_SCC1A_SLOT 0x190
#define IO_REG_AB_SLOT 0x190
#define IO_REG_FLOPPY_SLOT 0x1a0
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IO_REG_SCSI_SCR 0x1b0
#define IO_REG_SCSI_SDR0 0x1c0
#define IO_REG_SCSI_SDR1 0x1d0
#define IO_REG_FCTR 0x1e0
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IO_REG_RES_31 0x1f0
#define IO_SSR_SCC0A_TX_DMA_EN (1<<31)
#define IO_SSR_SCC0A_RX_DMA_EN (1<<30)
#define IO_SSR_RES_27 (1<<27)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IO_SSR_RES_26 (1<<26)
#define IO_SSR_RES_25 (1<<25)
#define IO_SSR_RES_24 (1<<24)
#define IO_SSR_RES_23 (1<<23)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IO_SSR_SCSI_DMA_DIR (1<<18)
#define IO_SSR_SCSI_DMA_EN (1<<17)
#define IO_SSR_LANCE_DMA_EN (1<<16)
#define IO_SSR_SCC1A_TX_DMA_EN (1<<29)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IO_SSR_SCC1A_RX_DMA_EN (1<<28)
#define IO_SSR_RES_22 (1<<22)
#define IO_SSR_RES_21 (1<<21)
#define IO_SSR_RES_20 (1<<20)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IO_SSR_RES_19 (1<<19)
#define IO_SSR_AB_TX_DMA_EN (1<<29)
#define IO_SSR_AB_RX_DMA_EN (1<<28)
#define IO_SSR_FLOPPY_DMA_DIR (1<<22)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IO_SSR_FLOPPY_DMA_EN (1<<21)
#define IO_SSR_ISDN_TX_DMA_EN (1<<20)
#define IO_SSR_ISDN_RX_DMA_EN (1<<19)
#define KN0X_IO_SSR_DIAGDN (1<<15)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define KN0X_IO_SSR_SCC_RST (1<<11)
#define KN0X_IO_SSR_RTC_RST (1<<10)
#define KN0X_IO_SSR_ASC_RST (1<<9)
#define KN0X_IO_SSR_LANCE_RST (1<<8)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#endif

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/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef __ASM_MIPS_DEC_KN02XA_H
#define __ASM_MIPS_DEC_KN02XA_H
#include <asm/dec/ioasic_addrs.h>
#define KN02XA_SLOT_BASE 0x1c000000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define KN02XA_MER 0x0c400000
#define KN02XA_MSR 0x0c800000
#define KN02XA_MEM_CONF 0x0e000000
#define KN02XA_EAR 0x0e000004
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define KN02XA_BOOT0 0x0e000008
#define KN02XA_MEM_INTR 0x0e00000c
#define KN02XA_MER_RES_28 (0xf<<28)
#define KN02XA_MER_RES_17 (0x3ff<<17)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define KN02XA_MER_PAGERR (1<<16)
#define KN02XA_MER_TRANSERR (1<<15)
#define KN02XA_MER_PARDIS (1<<14)
#define KN02XA_MER_SIZE (1<<13)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define KN02XA_MER_RES_12 (1<<12)
#define KN02XA_MER_BYTERR (0xf<<8)
#define KN02XA_MER_BYTERR_3 (0x8<<8)
#define KN02XA_MER_BYTERR_2 (0x4<<8)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define KN02XA_MER_BYTERR_1 (0x2<<8)
#define KN02XA_MER_BYTERR_0 (0x1<<8)
#define KN02XA_MER_RES_0 (0xff<<0)
#define KN02XA_MSR_RES_27 (0x1f<<27)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define KN02XA_MSR_RES_14 (0x7<<14)
#define KN02XA_MSR_SIZE (1<<13)
#define KN02XA_MSR_RES_0 (0x1fff<<0)
#define KN02XA_EAR_RES_29 (0x7<<29)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define KN02XA_EAR_ADDRESS (0x7ffffff<<2)
#define KN02XA_EAR_RES_0 (0x3<<0)
#ifndef __ASSEMBLY__
#include <linux/interrupt.h>
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
struct pt_regs;
#endif
#endif

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/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef __ASM_DEC_SYSTEM_H
#define __ASM_DEC_SYSTEM_H
#endif

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/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef _ASM_DELAY_H
#define _ASM_DELAY_H
#include <linux/param.h>
#include <linux/smp.h>
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#include <asm/compiler.h>
#include <asm/war.h>
#define __udelay_val cpu_data[raw_smp_processor_id()].udelay_val
#define udelay(usecs) __udelay((usecs), __udelay_val)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#if HZ >= 1000
#define MAX_UDELAY_MS 1
#elif HZ <= 200
#define MAX_UDELAY_MS 5
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#else
#define MAX_UDELAY_MS (1000 / HZ)
#endif
#endif
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */

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/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#include <asm-generic/device.h>

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/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef _ASM_DIV64_H
#define _ASM_DIV64_H
#include <linux/types.h>
#if _MIPS_SZLONG == 32
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#include <asm/compiler.h>
#define do_div64_32(res, high, low, base) ({ unsigned long __quot32, __mod32; unsigned long __cf, __tmp, __tmp2, __i; __asm__(".set push\n\t" ".set noat\n\t" ".set noreorder\n\t" "move %2, $0\n\t" "move %3, $0\n\t" "b 1f\n\t" " li %4, 0x21\n" "0:\n\t" "sll $1, %0, 0x1\n\t" "srl %3, %0, 0x1f\n\t" "or %0, $1, %5\n\t" "sll %1, %1, 0x1\n\t" "sll %2, %2, 0x1\n" "1:\n\t" "bnez %3, 2f\n\t" " sltu %5, %0, %z6\n\t" "bnez %5, 3f\n" "2:\n\t" " addiu %4, %4, -1\n\t" "subu %0, %0, %z6\n\t" "addiu %2, %2, 1\n" "3:\n\t" "bnez %4, 0b\n\t" " srl %5, %1, 0x1f\n\t" ".set pop" : "=&r" (__mod32), "=&r" (__tmp), "=&r" (__quot32), "=&r" (__cf), "=&r" (__i), "=&r" (__tmp2) : "Jr" (base), "0" (high), "1" (low)); (res) = __quot32; __mod32; })
#define do_div(n, base) ({ unsigned long long __quot; unsigned long __mod; unsigned long long __div; unsigned long __upper, __low, __high, __base; __div = (n); __base = (base); __high = __div >> 32; __low = __div; __upper = __high; if (__high) __asm__("divu $0, %z2, %z3" : "=h" (__upper), "=l" (__high) : "Jr" (__high), "Jr" (__base) : GCC_REG_ACCUM); __mod = do_div64_32(__low, __upper, __low, __base); __quot = __high; __quot = __quot << 32 | __low; (n) = __quot; __mod; })
#endif
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#if _MIPS_SZLONG == 64
#define do_div(n, base) ({ unsigned long __quot; unsigned int __mod; unsigned long __div; unsigned int __base; __div = (n); __base = (base); __mod = __div % __base; __quot = __div / __base; (n) = __quot; __mod; })
#endif
#endif
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */

24
libc/kernel/arch-mips/asm/dma-mapping.h Normal file
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/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef _ASM_DMA_MAPPING_H
#define _ASM_DMA_MAPPING_H
#include <asm/scatterlist.h>
#include <asm/cache.h>
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#endif

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libc/kernel/arch-mips/asm/dma.h Normal file
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/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef _ASM_DMA_H
#define _ASM_DMA_H
#include <asm/io.h>
#include <linux/spinlock.h>
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#include <linux/delay.h>
#include <asm/system.h>
#ifdef HAVE_REALLY_SLOW_DMA_CONTROLLER
#define dma_outb outb_p
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#else
#define dma_outb outb
#endif
#define dma_inb inb
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MAX_DMA_CHANNELS 8
#define MAX_DMA_ADDRESS (PAGE_OFFSET + 0x01000000)
#define MAX_DMA_PFN PFN_DOWN(virt_to_phys((void *)MAX_DMA_ADDRESS))
#define MAX_DMA32_PFN (1UL << (32 - PAGE_SHIFT))
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IO_DMA1_BASE 0x00
#define IO_DMA2_BASE 0xC0
#define DMA1_CMD_REG 0x08
#define DMA1_STAT_REG 0x08
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define DMA1_REQ_REG 0x09
#define DMA1_MASK_REG 0x0A
#define DMA1_MODE_REG 0x0B
#define DMA1_CLEAR_FF_REG 0x0C
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define DMA1_TEMP_REG 0x0D
#define DMA1_RESET_REG 0x0D
#define DMA1_CLR_MASK_REG 0x0E
#define DMA1_MASK_ALL_REG 0x0F
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define DMA2_CMD_REG 0xD0
#define DMA2_STAT_REG 0xD0
#define DMA2_REQ_REG 0xD2
#define DMA2_MASK_REG 0xD4
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define DMA2_MODE_REG 0xD6
#define DMA2_CLEAR_FF_REG 0xD8
#define DMA2_TEMP_REG 0xDA
#define DMA2_RESET_REG 0xDA
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define DMA2_CLR_MASK_REG 0xDC
#define DMA2_MASK_ALL_REG 0xDE
#define DMA_ADDR_0 0x00
#define DMA_ADDR_1 0x02
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define DMA_ADDR_2 0x04
#define DMA_ADDR_3 0x06
#define DMA_ADDR_4 0xC0
#define DMA_ADDR_5 0xC4
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define DMA_ADDR_6 0xC8
#define DMA_ADDR_7 0xCC
#define DMA_CNT_0 0x01
#define DMA_CNT_1 0x03
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define DMA_CNT_2 0x05
#define DMA_CNT_3 0x07
#define DMA_CNT_4 0xC2
#define DMA_CNT_5 0xC6
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define DMA_CNT_6 0xCA
#define DMA_CNT_7 0xCE
#define DMA_PAGE_0 0x87
#define DMA_PAGE_1 0x83
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define DMA_PAGE_2 0x81
#define DMA_PAGE_3 0x82
#define DMA_PAGE_5 0x8B
#define DMA_PAGE_6 0x89
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define DMA_PAGE_7 0x8A
#define DMA_MODE_READ 0x44
#define DMA_MODE_WRITE 0x48
#define DMA_MODE_CASCADE 0xC0
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define DMA_AUTOINIT 0x10
#define isa_dma_bridge_buggy (0)
#endif

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libc/kernel/arch-mips/asm/ds1286.h Normal file
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/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef _ASM_DS1286_H
#define _ASM_DS1286_H
#include <ds1286.h>
#endif
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */

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libc/kernel/arch-mips/asm/dsp.h Normal file
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/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef _ASM_DSP_H
#define _ASM_DSP_H
#include <asm/cpu.h>
#include <asm/cpu-features.h>
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#include <asm/hazards.h>
#include <asm/mipsregs.h>
#define DSP_DEFAULT 0x00000000
#define DSP_MASK 0x3ff
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define __enable_dsp_hazard() do { asm("_ehb"); } while (0)
#define __save_dsp(tsk) do { tsk->thread.dsp.dspr[0] = mfhi1(); tsk->thread.dsp.dspr[1] = mflo1(); tsk->thread.dsp.dspr[2] = mfhi2(); tsk->thread.dsp.dspr[3] = mflo2(); tsk->thread.dsp.dspr[4] = mfhi3(); tsk->thread.dsp.dspr[5] = mflo3(); tsk->thread.dsp.dspcontrol = rddsp(DSP_MASK); } while (0)
#define save_dsp(tsk) do { if (cpu_has_dsp) __save_dsp(tsk); } while (0)
#define __restore_dsp(tsk) do { mthi1(tsk->thread.dsp.dspr[0]); mtlo1(tsk->thread.dsp.dspr[1]); mthi2(tsk->thread.dsp.dspr[2]); mtlo2(tsk->thread.dsp.dspr[3]); mthi3(tsk->thread.dsp.dspr[4]); mtlo3(tsk->thread.dsp.dspr[5]); wrdsp(tsk->thread.dsp.dspcontrol, DSP_MASK); } while (0)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define restore_dsp(tsk) do { if (cpu_has_dsp) __restore_dsp(tsk); } while (0)
#define __get_dsp_regs(tsk) ({ if (tsk == current) __save_dsp(current); tsk->thread.dsp.dspr; })
#endif

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/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef _ASM_ELF_H
#define _ASM_ELF_H
#define EF_MIPS_ARCH_1 0x00000000
#define EF_MIPS_ARCH_2 0x10000000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define EF_MIPS_ARCH_3 0x20000000
#define EF_MIPS_ARCH_4 0x30000000
#define EF_MIPS_ARCH_5 0x40000000
#define EF_MIPS_ARCH_32 0x50000000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define EF_MIPS_ARCH_64 0x60000000
#define EF_MIPS_ARCH_32R2 0x70000000
#define EF_MIPS_ARCH_64R2 0x80000000
#define EF_MIPS_ABI_O32 0x00001000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define EF_MIPS_ABI_O64 0x00002000
#define PT_MIPS_REGINFO 0x70000000
#define PT_MIPS_RTPROC 0x70000001
#define PT_MIPS_OPTIONS 0x70000002
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define EF_MIPS_NOREORDER 0x00000001
#define EF_MIPS_PIC 0x00000002
#define EF_MIPS_CPIC 0x00000004
#define EF_MIPS_ABI2 0x00000020
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define EF_MIPS_OPTIONS_FIRST 0x00000080
#define EF_MIPS_32BITMODE 0x00000100
#define EF_MIPS_ABI 0x0000f000
#define EF_MIPS_ARCH 0xf0000000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define DT_MIPS_RLD_VERSION 0x70000001
#define DT_MIPS_TIME_STAMP 0x70000002
#define DT_MIPS_ICHECKSUM 0x70000003
#define DT_MIPS_IVERSION 0x70000004
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define DT_MIPS_FLAGS 0x70000005
#define RHF_NONE 0x00000000
#define RHF_HARDWAY 0x00000001
#define RHF_NOTPOT 0x00000002
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define RHF_SGI_ONLY 0x00000010
#define DT_MIPS_BASE_ADDRESS 0x70000006
#define DT_MIPS_CONFLICT 0x70000008
#define DT_MIPS_LIBLIST 0x70000009
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define DT_MIPS_LOCAL_GOTNO 0x7000000a
#define DT_MIPS_CONFLICTNO 0x7000000b
#define DT_MIPS_LIBLISTNO 0x70000010
#define DT_MIPS_SYMTABNO 0x70000011
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define DT_MIPS_UNREFEXTNO 0x70000012
#define DT_MIPS_GOTSYM 0x70000013
#define DT_MIPS_HIPAGENO 0x70000014
#define DT_MIPS_RLD_MAP 0x70000016
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define R_MIPS_NONE 0
#define R_MIPS_16 1
#define R_MIPS_32 2
#define R_MIPS_REL32 3
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define R_MIPS_26 4
#define R_MIPS_HI16 5
#define R_MIPS_LO16 6
#define R_MIPS_GPREL16 7
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define R_MIPS_LITERAL 8
#define R_MIPS_GOT16 9
#define R_MIPS_PC16 10
#define R_MIPS_CALL16 11
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define R_MIPS_GPREL32 12
#define R_MIPS_UNUSED1 13
#define R_MIPS_UNUSED2 14
#define R_MIPS_UNUSED3 15
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define R_MIPS_SHIFT5 16
#define R_MIPS_SHIFT6 17
#define R_MIPS_64 18
#define R_MIPS_GOT_DISP 19
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define R_MIPS_GOT_PAGE 20
#define R_MIPS_GOT_OFST 21
#define R_MIPS_GOTHI16 22
#define R_MIPS_GOTLO16 23
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define R_MIPS_SUB 24
#define R_MIPS_INSERT_A 25
#define R_MIPS_INSERT_B 26
#define R_MIPS_DELETE 27
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define R_MIPS_HIGHER 28
#define R_MIPS_HIGHEST 29
#define R_MIPS_CALLHI16 30
#define R_MIPS_CALLLO16 31
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define R_MIPS_LOVENDOR 100
#define R_MIPS_HIVENDOR 127
#define SHN_MIPS_ACCOMON 0xff00
#define SHN_MIPS_TEXT 0xff01
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SHN_MIPS_DATA 0xff02
#define SHN_MIPS_SCOMMON 0xff03
#define SHN_MIPS_SUNDEFINED 0xff04
#define SHT_MIPS_LIST 0x70000000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SHT_MIPS_CONFLICT 0x70000002
#define SHT_MIPS_GPTAB 0x70000003
#define SHT_MIPS_UCODE 0x70000004
#define SHT_MIPS_DEBUG 0x70000005
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SHT_MIPS_REGINFO 0x70000006
#define SHT_MIPS_PACKAGE 0x70000007
#define SHT_MIPS_PACKSYM 0x70000008
#define SHT_MIPS_RELD 0x70000009
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SHT_MIPS_IFACE 0x7000000b
#define SHT_MIPS_CONTENT 0x7000000c
#define SHT_MIPS_OPTIONS 0x7000000d
#define SHT_MIPS_SHDR 0x70000010
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SHT_MIPS_FDESC 0x70000011
#define SHT_MIPS_EXTSYM 0x70000012
#define SHT_MIPS_DENSE 0x70000013
#define SHT_MIPS_PDESC 0x70000014
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SHT_MIPS_LOCSYM 0x70000015
#define SHT_MIPS_AUXSYM 0x70000016
#define SHT_MIPS_OPTSYM 0x70000017
#define SHT_MIPS_LOCSTR 0x70000018
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SHT_MIPS_LINE 0x70000019
#define SHT_MIPS_RFDESC 0x7000001a
#define SHT_MIPS_DELTASYM 0x7000001b
#define SHT_MIPS_DELTAINST 0x7000001c
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SHT_MIPS_DELTACLASS 0x7000001d
#define SHT_MIPS_DWARF 0x7000001e
#define SHT_MIPS_DELTADECL 0x7000001f
#define SHT_MIPS_SYMBOL_LIB 0x70000020
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SHT_MIPS_EVENTS 0x70000021
#define SHT_MIPS_TRANSLATE 0x70000022
#define SHT_MIPS_PIXIE 0x70000023
#define SHT_MIPS_XLATE 0x70000024
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SHT_MIPS_XLATE_DEBUG 0x70000025
#define SHT_MIPS_WHIRL 0x70000026
#define SHT_MIPS_EH_REGION 0x70000027
#define SHT_MIPS_XLATE_OLD 0x70000028
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SHT_MIPS_PDR_EXCEPTION 0x70000029
#define SHF_MIPS_GPREL 0x10000000
#define SHF_MIPS_MERGE 0x20000000
#define SHF_MIPS_ADDR 0x40000000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SHF_MIPS_STRING 0x80000000
#define SHF_MIPS_NOSTRIP 0x08000000
#define SHF_MIPS_LOCAL 0x04000000
#define SHF_MIPS_NAMES 0x02000000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SHF_MIPS_NODUPES 0x01000000
#ifndef ELF_ARCH
#define ELF_NGREG 45
#define ELF_NFPREG 33
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
typedef unsigned long elf_greg_t;
typedef elf_greg_t elf_gregset_t[ELF_NGREG];
typedef double elf_fpreg_t;
typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG];
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#ifdef __MIPSEB__
#define ELF_DATA ELFDATA2MSB
#elif __MIPSEL__
#define ELF_DATA ELFDATA2LSB
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#endif
#define ELF_ARCH EM_MIPS
#endif
struct mips_abi;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
struct task_struct;
#define ELF_CORE_COPY_REGS(elf_regs, regs) elf_dump_regs((elf_greg_t *)&(elf_regs), regs);
#define ELF_CORE_COPY_TASK_REGS(tsk, elf_regs) dump_task_regs(tsk, elf_regs)
#define ELF_CORE_COPY_FPREGS(tsk, elf_fpregs) dump_task_fpu(tsk, elf_fpregs)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define USE_ELF_CORE_DUMP
#define ELF_EXEC_PAGESIZE PAGE_SIZE
#define ELF_HWCAP (0)
#define ELF_PLATFORM (NULL)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define ELF_PLAT_INIT(_r, load_addr) do { _r->regs[1] = _r->regs[2] = _r->regs[3] = _r->regs[4] = 0; _r->regs[5] = _r->regs[6] = _r->regs[7] = _r->regs[8] = 0; _r->regs[9] = _r->regs[10] = _r->regs[11] = _r->regs[12] = 0; _r->regs[13] = _r->regs[14] = _r->regs[15] = _r->regs[16] = 0; _r->regs[17] = _r->regs[18] = _r->regs[19] = _r->regs[20] = 0; _r->regs[21] = _r->regs[22] = _r->regs[23] = _r->regs[24] = 0; _r->regs[25] = _r->regs[26] = _r->regs[27] = _r->regs[28] = 0; _r->regs[30] = _r->regs[31] = 0; } while (0)
#ifndef ELF_ET_DYN_BASE
#define ELF_ET_DYN_BASE (TASK_SIZE / 3 * 2)
#endif
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#endif

146
libc/kernel/arch-mips/asm/errno.h Normal file
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/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef _ASM_ERRNO_H
#define _ASM_ERRNO_H
#include <asm-generic/errno-base.h>
#define ENOMSG 35
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define EIDRM 36
#define ECHRNG 37
#define EL2NSYNC 38
#define EL3HLT 39
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define EL3RST 40
#define ELNRNG 41
#define EUNATCH 42
#define ENOCSI 43
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define EL2HLT 44
#define EDEADLK 45
#define ENOLCK 46
#define EBADE 50
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define EBADR 51
#define EXFULL 52
#define ENOANO 53
#define EBADRQC 54
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define EBADSLT 55
#define EDEADLOCK 56
#define EBFONT 59
#define ENOSTR 60
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define ENODATA 61
#define ETIME 62
#define ENOSR 63
#define ENONET 64
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define ENOPKG 65
#define EREMOTE 66
#define ENOLINK 67
#define EADV 68
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define ESRMNT 69
#define ECOMM 70
#define EPROTO 71
#define EDOTDOT 73
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define EMULTIHOP 74
#define EBADMSG 77
#define ENAMETOOLONG 78
#define EOVERFLOW 79
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define ENOTUNIQ 80
#define EBADFD 81
#define EREMCHG 82
#define ELIBACC 83
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define ELIBBAD 84
#define ELIBSCN 85
#define ELIBMAX 86
#define ELIBEXEC 87
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define EILSEQ 88
#define ENOSYS 89
#define ELOOP 90
#define ERESTART 91
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define ESTRPIPE 92
#define ENOTEMPTY 93
#define EUSERS 94
#define ENOTSOCK 95
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define EDESTADDRREQ 96
#define EMSGSIZE 97
#define EPROTOTYPE 98
#define ENOPROTOOPT 99
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define EPROTONOSUPPORT 120
#define ESOCKTNOSUPPORT 121
#define EOPNOTSUPP 122
#define EPFNOSUPPORT 123
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define EAFNOSUPPORT 124
#define EADDRINUSE 125
#define EADDRNOTAVAIL 126
#define ENETDOWN 127
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define ENETUNREACH 128
#define ENETRESET 129
#define ECONNABORTED 130
#define ECONNRESET 131
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define ENOBUFS 132
#define EISCONN 133
#define ENOTCONN 134
#define EUCLEAN 135
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define ENOTNAM 137
#define ENAVAIL 138
#define EISNAM 139
#define EREMOTEIO 140
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define EINIT 141
#define EREMDEV 142
#define ESHUTDOWN 143
#define ETOOMANYREFS 144
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define ETIMEDOUT 145
#define ECONNREFUSED 146
#define EHOSTDOWN 147
#define EHOSTUNREACH 148
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define EWOULDBLOCK EAGAIN
#define EALREADY 149
#define EINPROGRESS 150
#define ESTALE 151
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define ECANCELED 158
#define ENOMEDIUM 159
#define EMEDIUMTYPE 160
#define ENOKEY 161
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define EKEYEXPIRED 162
#define EKEYREVOKED 163
#define EKEYREJECTED 164
#define EOWNERDEAD 165
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define ENOTRECOVERABLE 166
#define EDQUOT 1133
#endif

48
libc/kernel/arch-mips/asm/fcntl.h Normal file
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/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef _ASM_FCNTL_H
#define _ASM_FCNTL_H
#define O_APPEND 0x0008
#define O_SYNC 0x0010
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define O_NONBLOCK 0x0080
#define O_CREAT 0x0100
#define O_TRUNC 0x0200
#define O_EXCL 0x0400
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define O_NOCTTY 0x0800
#define FASYNC 0x1000
#define O_LARGEFILE 0x2000
#define O_DIRECT 0x8000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define F_GETLK 14
#define F_SETLK 6
#define F_SETLKW 7
#define F_SETOWN 24
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define F_GETOWN 23
#ifndef __mips64
#define F_GETLK64 33
#define F_SETLK64 34
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define F_SETLKW64 35
#endif
#include <asm-generic/fcntl.h>
#endif
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */

36
libc/kernel/arch-mips/asm/fixmap.h Normal file
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@ -0,0 +1,36 @@
/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef _ASM_FIXMAP_H
#define _ASM_FIXMAP_H
#include <asm/page.h>
enum fixed_addresses {
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define FIX_N_COLOURS 8
FIX_CMAP_BEGIN,
FIX_CMAP_END = FIX_CMAP_BEGIN + FIX_N_COLOURS,
__end_of_fixed_addresses
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
};
#define FIXADDR_TOP ((unsigned long)(long)(int)0xfffe0000)
#define FIXADDR_SIZE (__end_of_fixed_addresses << PAGE_SHIFT)
#define FIXADDR_START (FIXADDR_TOP - FIXADDR_SIZE)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define __fix_to_virt(x) (FIXADDR_TOP - ((x) << PAGE_SHIFT))
#define __virt_to_fix(x) ((FIXADDR_TOP - ((x)&PAGE_MASK)) >> PAGE_SHIFT)
#endif

34
libc/kernel/arch-mips/asm/floppy.h Normal file
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/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef _ASM_FLOPPY_H
#define _ASM_FLOPPY_H
#include <linux/dma-mapping.h>
#define MAX_BUFFER_SECTORS 24
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define FLOPPY0_TYPE fd_drive_type(0)
#define FLOPPY1_TYPE fd_drive_type(1)
#define FDC1 fd_getfdaddr1();
#define N_FDC 1
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define N_DRIVE 8
#define CROSS_64KB(a, s) ((unsigned long)(a)/K_64 != ((unsigned long)(a) + (s) - 1) / K_64)
#define EXTRA_FLOPPY_PARAMS
#include <floppy.h>
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#endif

110
libc/kernel/arch-mips/asm/fpregdef.h Normal file
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/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef _ASM_FPREGDEF_H
#define _ASM_FPREGDEF_H
#include <asm/sgidefs.h>
#if _MIPS_SIM == _MIPS_SIM_ABI32
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define fv0 $f0
#define fv0f $f1
#define fv1 $f2
#define fv1f $f3
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define fa0 $f12
#define fa0f $f13
#define fa1 $f14
#define fa1f $f15
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define ft0 $f4
#define ft0f $f5
#define ft1 $f6
#define ft1f $f7
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define ft2 $f8
#define ft2f $f9
#define ft3 $f10
#define ft3f $f11
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define ft4 $f16
#define ft4f $f17
#define ft5 $f18
#define ft5f $f19
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define fs0 $f20
#define fs0f $f21
#define fs1 $f22
#define fs1f $f23
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define fs2 $f24
#define fs2f $f25
#define fs3 $f26
#define fs3f $f27
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define fs4 $f28
#define fs4f $f29
#define fs5 $f30
#define fs5f $f31
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define fcr31 $31
#endif
#if _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32
#define fv0 $f0
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define fv1 $f2
#define fa0 $f12
#define fa1 $f13
#define fa2 $f14
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define fa3 $f15
#define fa4 $f16
#define fa5 $f17
#define fa6 $f18
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define fa7 $f19
#define ft0 $f4
#define ft1 $f5
#define ft2 $f6
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define ft3 $f7
#define ft4 $f8
#define ft5 $f9
#define ft6 $f10
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define ft7 $f11
#define ft8 $f20
#define ft9 $f21
#define ft10 $f22
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define ft11 $f23
#define ft12 $f1
#define ft13 $f3
#define fs0 $f24
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define fs1 $f25
#define fs2 $f26
#define fs3 $f27
#define fs4 $f28
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define fs5 $f29
#define fs6 $f30
#define fs7 $f31
#define fcr31 $31
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#endif
#endif

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libc/kernel/arch-mips/asm/fw/arc/types.h Normal file
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/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef _ASM_ARC_TYPES_H
#define _ASM_ARC_TYPES_H
typedef CHAR *PCHAR;
typedef SHORT *PSHORT;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
typedef LARGE_INTEGER *PLARGE_INTEGER;
typedef LONG *PLONG;
typedef UCHAR *PUCHAR;
typedef USHORT *PUSHORT;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
typedef ULONG *PULONG;
typedef VOID *PVOID;
typedef struct {
USHORT CursorXPosition;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
USHORT CursorYPosition;
USHORT CursorMaxXPosition;
USHORT CursorMaxYPosition;
USHORT ForegroundColor;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
USHORT BackgroundColor;
UCHAR HighIntensity;
UCHAR Underscored;
UCHAR ReverseVideo;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
} DISPLAY_STATUS;
#endif

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libc/kernel/arch-mips/asm/gt64120.h Normal file
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/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef _ASM_GT64120_H
#define _ASM_GT64120_H
#include <linux/clocksource.h>
#include <asm/addrspace.h>
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#include <asm/byteorder.h>
#define MSK(n) ((1 << (n)) - 1)
#define GT_CPU_OFS 0x000
#define GT_MULTI_OFS 0x120
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define GT_SCS10LD_OFS 0x008
#define GT_SCS10HD_OFS 0x010
#define GT_SCS32LD_OFS 0x018
#define GT_SCS32HD_OFS 0x020
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define GT_CS20LD_OFS 0x028
#define GT_CS20HD_OFS 0x030
#define GT_CS3BOOTLD_OFS 0x038
#define GT_CS3BOOTHD_OFS 0x040
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define GT_PCI0IOLD_OFS 0x048
#define GT_PCI0IOHD_OFS 0x050
#define GT_PCI0M0LD_OFS 0x058
#define GT_PCI0M0HD_OFS 0x060
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define GT_ISD_OFS 0x068
#define GT_PCI0M1LD_OFS 0x080
#define GT_PCI0M1HD_OFS 0x088
#define GT_PCI1IOLD_OFS 0x090
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define GT_PCI1IOHD_OFS 0x098
#define GT_PCI1M0LD_OFS 0x0a0
#define GT_PCI1M0HD_OFS 0x0a8
#define GT_PCI1M1LD_OFS 0x0b0
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define GT_PCI1M1HD_OFS 0x0b8
#define GT_PCI1M1LD_OFS 0x0b0
#define GT_PCI1M1HD_OFS 0x0b8
#define GT_SCS10AR_OFS 0x0d0
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define GT_SCS32AR_OFS 0x0d8
#define GT_CS20R_OFS 0x0e0
#define GT_CS3BOOTR_OFS 0x0e8
#define GT_PCI0IOREMAP_OFS 0x0f0
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define GT_PCI0M0REMAP_OFS 0x0f8
#define GT_PCI0M1REMAP_OFS 0x100
#define GT_PCI1IOREMAP_OFS 0x108
#define GT_PCI1M0REMAP_OFS 0x110
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define GT_PCI1M1REMAP_OFS 0x118
#define GT_CPUERR_ADDRLO_OFS 0x070
#define GT_CPUERR_ADDRHI_OFS 0x078
#define GT_CPUERR_DATALO_OFS 0x128
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define GT_CPUERR_DATAHI_OFS 0x130
#define GT_CPUERR_PARITY_OFS 0x138
#define GT_PCI0SYNC_OFS 0x0c0
#define GT_PCI1SYNC_OFS 0x0c8
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define GT_SCS0LD_OFS 0x400
#define GT_SCS0HD_OFS 0x404
#define GT_SCS1LD_OFS 0x408
#define GT_SCS1HD_OFS 0x40c
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define GT_SCS2LD_OFS 0x410
#define GT_SCS2HD_OFS 0x414
#define GT_SCS3LD_OFS 0x418
#define GT_SCS3HD_OFS 0x41c
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define GT_CS0LD_OFS 0x420
#define GT_CS0HD_OFS 0x424
#define GT_CS1LD_OFS 0x428
#define GT_CS1HD_OFS 0x42c
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define GT_CS2LD_OFS 0x430
#define GT_CS2HD_OFS 0x434
#define GT_CS3LD_OFS 0x438
#define GT_CS3HD_OFS 0x43c
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define GT_BOOTLD_OFS 0x440
#define GT_BOOTHD_OFS 0x444
#define GT_ADERR_OFS 0x470
#define GT_SDRAM_CFG_OFS 0x448
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define GT_SDRAM_OPMODE_OFS 0x474
#define GT_SDRAM_BM_OFS 0x478
#define GT_SDRAM_ADDRDECODE_OFS 0x47c
#define GT_SDRAM_B0_OFS 0x44c
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define GT_SDRAM_B1_OFS 0x450
#define GT_SDRAM_B2_OFS 0x454
#define GT_SDRAM_B3_OFS 0x458
#define GT_DEV_B0_OFS 0x45c
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define GT_DEV_B1_OFS 0x460
#define GT_DEV_B2_OFS 0x464
#define GT_DEV_B3_OFS 0x468
#define GT_DEV_BOOT_OFS 0x46c
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define GT_ECC_ERRDATALO 0x480
#define GT_ECC_ERRDATAHI 0x484
#define GT_ECC_MEM 0x488
#define GT_ECC_CALC 0x48c
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define GT_ECC_ERRADDR 0x490
#define GT_DMA0_CNT_OFS 0x800
#define GT_DMA1_CNT_OFS 0x804
#define GT_DMA2_CNT_OFS 0x808
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define GT_DMA3_CNT_OFS 0x80c
#define GT_DMA0_SA_OFS 0x810
#define GT_DMA1_SA_OFS 0x814
#define GT_DMA2_SA_OFS 0x818
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define GT_DMA3_SA_OFS 0x81c
#define GT_DMA0_DA_OFS 0x820
#define GT_DMA1_DA_OFS 0x824
#define GT_DMA2_DA_OFS 0x828
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define GT_DMA3_DA_OFS 0x82c
#define GT_DMA0_NEXT_OFS 0x830
#define GT_DMA1_NEXT_OFS 0x834
#define GT_DMA2_NEXT_OFS 0x838
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define GT_DMA3_NEXT_OFS 0x83c
#define GT_DMA0_CUR_OFS 0x870
#define GT_DMA1_CUR_OFS 0x874
#define GT_DMA2_CUR_OFS 0x878
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define GT_DMA3_CUR_OFS 0x87c
#define GT_DMA0_CTRL_OFS 0x840
#define GT_DMA1_CTRL_OFS 0x844
#define GT_DMA2_CTRL_OFS 0x848
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define GT_DMA3_CTRL_OFS 0x84c
#define GT_DMA_ARB_OFS 0x860
#define GT_TC0_OFS 0x850
#define GT_TC1_OFS 0x854
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define GT_TC2_OFS 0x858
#define GT_TC3_OFS 0x85c
#define GT_TC_CONTROL_OFS 0x864
#define GT_PCI0_CMD_OFS 0xc00
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define GT_PCI0_TOR_OFS 0xc04
#define GT_PCI0_BS_SCS10_OFS 0xc08
#define GT_PCI0_BS_SCS32_OFS 0xc0c
#define GT_PCI0_BS_CS20_OFS 0xc10
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define GT_PCI0_BS_CS3BT_OFS 0xc14
#define GT_PCI1_IACK_OFS 0xc30
#define GT_PCI0_IACK_OFS 0xc34
#define GT_PCI0_BARE_OFS 0xc3c
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define GT_PCI0_PREFMBR_OFS 0xc40
#define GT_PCI0_SCS10_BAR_OFS 0xc48
#define GT_PCI0_SCS32_BAR_OFS 0xc4c
#define GT_PCI0_CS20_BAR_OFS 0xc50
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define GT_PCI0_CS3BT_BAR_OFS 0xc54
#define GT_PCI0_SSCS10_BAR_OFS 0xc58
#define GT_PCI0_SSCS32_BAR_OFS 0xc5c
#define GT_PCI0_SCS3BT_BAR_OFS 0xc64
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define GT_PCI1_CMD_OFS 0xc80
#define GT_PCI1_TOR_OFS 0xc84
#define GT_PCI1_BS_SCS10_OFS 0xc88
#define GT_PCI1_BS_SCS32_OFS 0xc8c
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define GT_PCI1_BS_CS20_OFS 0xc90
#define GT_PCI1_BS_CS3BT_OFS 0xc94
#define GT_PCI1_BARE_OFS 0xcbc
#define GT_PCI1_PREFMBR_OFS 0xcc0
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define GT_PCI1_SCS10_BAR_OFS 0xcc8
#define GT_PCI1_SCS32_BAR_OFS 0xccc
#define GT_PCI1_CS20_BAR_OFS 0xcd0
#define GT_PCI1_CS3BT_BAR_OFS 0xcd4
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define GT_PCI1_SSCS10_BAR_OFS 0xcd8
#define GT_PCI1_SSCS32_BAR_OFS 0xcdc
#define GT_PCI1_SCS3BT_BAR_OFS 0xce4
#define GT_PCI1_CFGADDR_OFS 0xcf0
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define GT_PCI1_CFGDATA_OFS 0xcf4
#define GT_PCI0_CFGADDR_OFS 0xcf8
#define GT_PCI0_CFGDATA_OFS 0xcfc
#define GT_INTRCAUSE_OFS 0xc18
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define GT_INTRMASK_OFS 0xc1c
#define GT_PCI0_ICMASK_OFS 0xc24
#define GT_PCI0_SERR0MASK_OFS 0xc28
#define GT_CPU_INTSEL_OFS 0xc70
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define GT_PCI0_INTSEL_OFS 0xc74
#define GT_HINTRCAUSE_OFS 0xc98
#define GT_HINTRMASK_OFS 0xc9c
#define GT_PCI0_HICMASK_OFS 0xca4
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define GT_PCI1_SERR1MASK_OFS 0xca8
#define INBOUND_MESSAGE_REGISTER0_PCI_SIDE 0x010
#define INBOUND_MESSAGE_REGISTER1_PCI_SIDE 0x014
#define OUTBOUND_MESSAGE_REGISTER0_PCI_SIDE 0x018
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define OUTBOUND_MESSAGE_REGISTER1_PCI_SIDE 0x01c
#define INBOUND_DOORBELL_REGISTER_PCI_SIDE 0x020
#define INBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE 0x024
#define INBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE 0x028
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define OUTBOUND_DOORBELL_REGISTER_PCI_SIDE 0x02c
#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE 0x030
#define OUTBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE 0x034
#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE 0x040
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE 0x044
#define QUEUE_CONTROL_REGISTER_PCI_SIDE 0x050
#define QUEUE_BASE_ADDRESS_REGISTER_PCI_SIDE 0x054
#define INBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE 0x060
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define INBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE 0x064
#define INBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE 0x068
#define INBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE 0x06c
#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE 0x070
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE 0x074
#define OUTBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE 0x078
#define OUTBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE 0x07c
#define INBOUND_MESSAGE_REGISTER0_CPU_SIDE 0x1c10
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define INBOUND_MESSAGE_REGISTER1_CPU_SIDE 0x1c14
#define OUTBOUND_MESSAGE_REGISTER0_CPU_SIDE 0x1c18
#define OUTBOUND_MESSAGE_REGISTER1_CPU_SIDE 0x1c1c
#define INBOUND_DOORBELL_REGISTER_CPU_SIDE 0x1c20
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define INBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE 0x1c24
#define INBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE 0x1c28
#define OUTBOUND_DOORBELL_REGISTER_CPU_SIDE 0x1c2c
#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE 0x1c30
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define OUTBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE 0x1c34
#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE 0x1c40
#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE 0x1c44
#define QUEUE_CONTROL_REGISTER_CPU_SIDE 0x1c50
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define QUEUE_BASE_ADDRESS_REGISTER_CPU_SIDE 0x1c54
#define INBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE 0x1c60
#define INBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE 0x1c64
#define INBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE 0x1c68
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define INBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE 0x1c6c
#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE 0x1c70
#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE 0x1c74
#define OUTBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE 0x1c78
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define OUTBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE 0x1c7c
#define GT_CPU_ENDIAN_SHF 12
#define GT_CPU_ENDIAN_MSK (MSK(1) << GT_CPU_ENDIAN_SHF)
#define GT_CPU_ENDIAN_BIT GT_CPU_ENDIAN_MSK
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define GT_CPU_WR_SHF 16
#define GT_CPU_WR_MSK (MSK(1) << GT_CPU_WR_SHF)
#define GT_CPU_WR_BIT GT_CPU_WR_MSK
#define GT_CPU_WR_DXDXDXDX 0
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define GT_CPU_WR_DDDD 1
#define GT_PCI_DCRM_SHF 21
#define GT_PCI_LD_SHF 0
#define GT_PCI_LD_MSK (MSK(15) << GT_PCI_LD_SHF)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define GT_PCI_HD_SHF 0
#define GT_PCI_HD_MSK (MSK(7) << GT_PCI_HD_SHF)
#define GT_PCI_REMAP_SHF 0
#define GT_PCI_REMAP_MSK (MSK(11) << GT_PCI_REMAP_SHF)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define GT_CFGADDR_CFGEN_SHF 31
#define GT_CFGADDR_CFGEN_MSK (MSK(1) << GT_CFGADDR_CFGEN_SHF)
#define GT_CFGADDR_CFGEN_BIT GT_CFGADDR_CFGEN_MSK
#define GT_CFGADDR_BUSNUM_SHF 16
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define GT_CFGADDR_BUSNUM_MSK (MSK(8) << GT_CFGADDR_BUSNUM_SHF)
#define GT_CFGADDR_DEVNUM_SHF 11
#define GT_CFGADDR_DEVNUM_MSK (MSK(5) << GT_CFGADDR_DEVNUM_SHF)
#define GT_CFGADDR_FUNCNUM_SHF 8
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define GT_CFGADDR_FUNCNUM_MSK (MSK(3) << GT_CFGADDR_FUNCNUM_SHF)
#define GT_CFGADDR_REGNUM_SHF 2
#define GT_CFGADDR_REGNUM_MSK (MSK(6) << GT_CFGADDR_REGNUM_SHF)
#define GT_SDRAM_BM_ORDER_SHF 2
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define GT_SDRAM_BM_ORDER_MSK (MSK(1) << GT_SDRAM_BM_ORDER_SHF)
#define GT_SDRAM_BM_ORDER_BIT GT_SDRAM_BM_ORDER_MSK
#define GT_SDRAM_BM_ORDER_SUB 1
#define GT_SDRAM_BM_ORDER_LIN 0
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define GT_SDRAM_BM_RSVD_ALL1 0xffb
#define GT_SDRAM_ADDRDECODE_ADDR_SHF 0
#define GT_SDRAM_ADDRDECODE_ADDR_MSK (MSK(3) << GT_SDRAM_ADDRDECODE_ADDR_SHF)
#define GT_SDRAM_ADDRDECODE_ADDR_0 0
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define GT_SDRAM_ADDRDECODE_ADDR_1 1
#define GT_SDRAM_ADDRDECODE_ADDR_2 2
#define GT_SDRAM_ADDRDECODE_ADDR_3 3
#define GT_SDRAM_ADDRDECODE_ADDR_4 4
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define GT_SDRAM_ADDRDECODE_ADDR_5 5
#define GT_SDRAM_ADDRDECODE_ADDR_6 6
#define GT_SDRAM_ADDRDECODE_ADDR_7 7
#define GT_SDRAM_B0_CASLAT_SHF 0
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define GT_SDRAM_B0_CASLAT_MSK (MSK(2) << GT_SDRAM_B0__SHF)
#define GT_SDRAM_B0_CASLAT_2 1
#define GT_SDRAM_B0_CASLAT_3 2
#define GT_SDRAM_B0_FTDIS_SHF 2
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define GT_SDRAM_B0_FTDIS_MSK (MSK(1) << GT_SDRAM_B0_FTDIS_SHF)
#define GT_SDRAM_B0_FTDIS_BIT GT_SDRAM_B0_FTDIS_MSK
#define GT_SDRAM_B0_SRASPRCHG_SHF 3
#define GT_SDRAM_B0_SRASPRCHG_MSK (MSK(1) << GT_SDRAM_B0_SRASPRCHG_SHF)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define GT_SDRAM_B0_SRASPRCHG_BIT GT_SDRAM_B0_SRASPRCHG_MSK
#define GT_SDRAM_B0_SRASPRCHG_2 0
#define GT_SDRAM_B0_SRASPRCHG_3 1
#define GT_SDRAM_B0_B0COMPAB_SHF 4
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define GT_SDRAM_B0_B0COMPAB_MSK (MSK(1) << GT_SDRAM_B0_B0COMPAB_SHF)
#define GT_SDRAM_B0_B0COMPAB_BIT GT_SDRAM_B0_B0COMPAB_MSK
#define GT_SDRAM_B0_64BITINT_SHF 5
#define GT_SDRAM_B0_64BITINT_MSK (MSK(1) << GT_SDRAM_B0_64BITINT_SHF)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define GT_SDRAM_B0_64BITINT_BIT GT_SDRAM_B0_64BITINT_MSK
#define GT_SDRAM_B0_64BITINT_2 0
#define GT_SDRAM_B0_64BITINT_4 1
#define GT_SDRAM_B0_BW_SHF 6
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define GT_SDRAM_B0_BW_MSK (MSK(1) << GT_SDRAM_B0_BW_SHF)
#define GT_SDRAM_B0_BW_BIT GT_SDRAM_B0_BW_MSK
#define GT_SDRAM_B0_BW_32 0
#define GT_SDRAM_B0_BW_64 1
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define GT_SDRAM_B0_BLODD_SHF 7
#define GT_SDRAM_B0_BLODD_MSK (MSK(1) << GT_SDRAM_B0_BLODD_SHF)
#define GT_SDRAM_B0_BLODD_BIT GT_SDRAM_B0_BLODD_MSK
#define GT_SDRAM_B0_PAR_SHF 8
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define GT_SDRAM_B0_PAR_MSK (MSK(1) << GT_SDRAM_B0_PAR_SHF)
#define GT_SDRAM_B0_PAR_BIT GT_SDRAM_B0_PAR_MSK
#define GT_SDRAM_B0_BYPASS_SHF 9
#define GT_SDRAM_B0_BYPASS_MSK (MSK(1) << GT_SDRAM_B0_BYPASS_SHF)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define GT_SDRAM_B0_BYPASS_BIT GT_SDRAM_B0_BYPASS_MSK
#define GT_SDRAM_B0_SRAS2SCAS_SHF 10
#define GT_SDRAM_B0_SRAS2SCAS_MSK (MSK(1) << GT_SDRAM_B0_SRAS2SCAS_SHF)
#define GT_SDRAM_B0_SRAS2SCAS_BIT GT_SDRAM_B0_SRAS2SCAS_MSK
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define GT_SDRAM_B0_SRAS2SCAS_2 0
#define GT_SDRAM_B0_SRAS2SCAS_3 1
#define GT_SDRAM_B0_SIZE_SHF 11
#define GT_SDRAM_B0_SIZE_MSK (MSK(1) << GT_SDRAM_B0_SIZE_SHF)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define GT_SDRAM_B0_SIZE_BIT GT_SDRAM_B0_SIZE_MSK
#define GT_SDRAM_B0_SIZE_16M 0
#define GT_SDRAM_B0_SIZE_64M 1
#define GT_SDRAM_B0_EXTPAR_SHF 12
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define GT_SDRAM_B0_EXTPAR_MSK (MSK(1) << GT_SDRAM_B0_EXTPAR_SHF)
#define GT_SDRAM_B0_EXTPAR_BIT GT_SDRAM_B0_EXTPAR_MSK
#define GT_SDRAM_B0_BLEN_SHF 13
#define GT_SDRAM_B0_BLEN_MSK (MSK(1) << GT_SDRAM_B0_BLEN_SHF)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define GT_SDRAM_B0_BLEN_BIT GT_SDRAM_B0_BLEN_MSK
#define GT_SDRAM_B0_BLEN_8 0
#define GT_SDRAM_B0_BLEN_4 1
#define GT_SDRAM_CFG_REFINT_SHF 0
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define GT_SDRAM_CFG_REFINT_MSK (MSK(14) << GT_SDRAM_CFG_REFINT_SHF)
#define GT_SDRAM_CFG_NINTERLEAVE_SHF 14
#define GT_SDRAM_CFG_NINTERLEAVE_MSK (MSK(1) << GT_SDRAM_CFG_NINTERLEAVE_SHF)
#define GT_SDRAM_CFG_NINTERLEAVE_BIT GT_SDRAM_CFG_NINTERLEAVE_MSK
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define GT_SDRAM_CFG_RMW_SHF 15
#define GT_SDRAM_CFG_RMW_MSK (MSK(1) << GT_SDRAM_CFG_RMW_SHF)
#define GT_SDRAM_CFG_RMW_BIT GT_SDRAM_CFG_RMW_MSK
#define GT_SDRAM_CFG_NONSTAGREF_SHF 16
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define GT_SDRAM_CFG_NONSTAGREF_MSK (MSK(1) << GT_SDRAM_CFG_NONSTAGREF_SHF)
#define GT_SDRAM_CFG_NONSTAGREF_BIT GT_SDRAM_CFG_NONSTAGREF_MSK
#define GT_SDRAM_CFG_DUPCNTL_SHF 19
#define GT_SDRAM_CFG_DUPCNTL_MSK (MSK(1) << GT_SDRAM_CFG_DUPCNTL_SHF)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define GT_SDRAM_CFG_DUPCNTL_BIT GT_SDRAM_CFG_DUPCNTL_MSK
#define GT_SDRAM_CFG_DUPBA_SHF 20
#define GT_SDRAM_CFG_DUPBA_MSK (MSK(1) << GT_SDRAM_CFG_DUPBA_SHF)
#define GT_SDRAM_CFG_DUPBA_BIT GT_SDRAM_CFG_DUPBA_MSK
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define GT_SDRAM_CFG_DUPEOT0_SHF 21
#define GT_SDRAM_CFG_DUPEOT0_MSK (MSK(1) << GT_SDRAM_CFG_DUPEOT0_SHF)
#define GT_SDRAM_CFG_DUPEOT0_BIT GT_SDRAM_CFG_DUPEOT0_MSK
#define GT_SDRAM_CFG_DUPEOT1_SHF 22
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define GT_SDRAM_CFG_DUPEOT1_MSK (MSK(1) << GT_SDRAM_CFG_DUPEOT1_SHF)
#define GT_SDRAM_CFG_DUPEOT1_BIT GT_SDRAM_CFG_DUPEOT1_MSK
#define GT_SDRAM_OPMODE_OP_SHF 0
#define GT_SDRAM_OPMODE_OP_MSK (MSK(3) << GT_SDRAM_OPMODE_OP_SHF)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define GT_SDRAM_OPMODE_OP_NORMAL 0
#define GT_SDRAM_OPMODE_OP_NOP 1
#define GT_SDRAM_OPMODE_OP_PRCHG 2
#define GT_SDRAM_OPMODE_OP_MODE 3
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define GT_SDRAM_OPMODE_OP_CBR 4
#define GT_TC_CONTROL_ENTC0_SHF 0
#define GT_TC_CONTROL_ENTC0_MSK (MSK(1) << GT_TC_CONTROL_ENTC0_SHF)
#define GT_TC_CONTROL_ENTC0_BIT GT_TC_CONTROL_ENTC0_MSK
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define GT_TC_CONTROL_SELTC0_SHF 1
#define GT_TC_CONTROL_SELTC0_MSK (MSK(1) << GT_TC_CONTROL_SELTC0_SHF)
#define GT_TC_CONTROL_SELTC0_BIT GT_TC_CONTROL_SELTC0_MSK
#define GT_PCI0_BARE_SWSCS3BOOTDIS_SHF 0
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define GT_PCI0_BARE_SWSCS3BOOTDIS_MSK (MSK(1) << GT_PCI0_BARE_SWSCS3BOOTDIS_SHF)
#define GT_PCI0_BARE_SWSCS3BOOTDIS_BIT GT_PCI0_BARE_SWSCS3BOOTDIS_MSK
#define GT_PCI0_BARE_SWSCS32DIS_SHF 1
#define GT_PCI0_BARE_SWSCS32DIS_MSK (MSK(1) << GT_PCI0_BARE_SWSCS32DIS_SHF)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define GT_PCI0_BARE_SWSCS32DIS_BIT GT_PCI0_BARE_SWSCS32DIS_MSK
#define GT_PCI0_BARE_SWSCS10DIS_SHF 2
#define GT_PCI0_BARE_SWSCS10DIS_MSK (MSK(1) << GT_PCI0_BARE_SWSCS10DIS_SHF)
#define GT_PCI0_BARE_SWSCS10DIS_BIT GT_PCI0_BARE_SWSCS10DIS_MSK
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define GT_PCI0_BARE_INTIODIS_SHF 3
#define GT_PCI0_BARE_INTIODIS_MSK (MSK(1) << GT_PCI0_BARE_INTIODIS_SHF)
#define GT_PCI0_BARE_INTIODIS_BIT GT_PCI0_BARE_INTIODIS_MSK
#define GT_PCI0_BARE_INTMEMDIS_SHF 4
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define GT_PCI0_BARE_INTMEMDIS_MSK (MSK(1) << GT_PCI0_BARE_INTMEMDIS_SHF)
#define GT_PCI0_BARE_INTMEMDIS_BIT GT_PCI0_BARE_INTMEMDIS_MSK
#define GT_PCI0_BARE_CS3BOOTDIS_SHF 5
#define GT_PCI0_BARE_CS3BOOTDIS_MSK (MSK(1) << GT_PCI0_BARE_CS3BOOTDIS_SHF)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define GT_PCI0_BARE_CS3BOOTDIS_BIT GT_PCI0_BARE_CS3BOOTDIS_MSK
#define GT_PCI0_BARE_CS20DIS_SHF 6
#define GT_PCI0_BARE_CS20DIS_MSK (MSK(1) << GT_PCI0_BARE_CS20DIS_SHF)
#define GT_PCI0_BARE_CS20DIS_BIT GT_PCI0_BARE_CS20DIS_MSK
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define GT_PCI0_BARE_SCS32DIS_SHF 7
#define GT_PCI0_BARE_SCS32DIS_MSK (MSK(1) << GT_PCI0_BARE_SCS32DIS_SHF)
#define GT_PCI0_BARE_SCS32DIS_BIT GT_PCI0_BARE_SCS32DIS_MSK
#define GT_PCI0_BARE_SCS10DIS_SHF 8
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define GT_PCI0_BARE_SCS10DIS_MSK (MSK(1) << GT_PCI0_BARE_SCS10DIS_SHF)
#define GT_PCI0_BARE_SCS10DIS_BIT GT_PCI0_BARE_SCS10DIS_MSK
#define GT_INTRCAUSE_MASABORT0_SHF 18
#define GT_INTRCAUSE_MASABORT0_MSK (MSK(1) << GT_INTRCAUSE_MASABORT0_SHF)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define GT_INTRCAUSE_MASABORT0_BIT GT_INTRCAUSE_MASABORT0_MSK
#define GT_INTRCAUSE_TARABORT0_SHF 19
#define GT_INTRCAUSE_TARABORT0_MSK (MSK(1) << GT_INTRCAUSE_TARABORT0_SHF)
#define GT_INTRCAUSE_TARABORT0_BIT GT_INTRCAUSE_TARABORT0_MSK
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define GT_PCI0_CFGADDR_REGNUM_SHF 2
#define GT_PCI0_CFGADDR_REGNUM_MSK (MSK(6) << GT_PCI0_CFGADDR_REGNUM_SHF)
#define GT_PCI0_CFGADDR_FUNCTNUM_SHF 8
#define GT_PCI0_CFGADDR_FUNCTNUM_MSK (MSK(3) << GT_PCI0_CFGADDR_FUNCTNUM_SHF)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define GT_PCI0_CFGADDR_DEVNUM_SHF 11
#define GT_PCI0_CFGADDR_DEVNUM_MSK (MSK(5) << GT_PCI0_CFGADDR_DEVNUM_SHF)
#define GT_PCI0_CFGADDR_BUSNUM_SHF 16
#define GT_PCI0_CFGADDR_BUSNUM_MSK (MSK(8) << GT_PCI0_CFGADDR_BUSNUM_SHF)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define GT_PCI0_CFGADDR_CONFIGEN_SHF 31
#define GT_PCI0_CFGADDR_CONFIGEN_MSK (MSK(1) << GT_PCI0_CFGADDR_CONFIGEN_SHF)
#define GT_PCI0_CFGADDR_CONFIGEN_BIT GT_PCI0_CFGADDR_CONFIGEN_MSK
#define GT_PCI0_CMD_MBYTESWAP_SHF 0
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define GT_PCI0_CMD_MBYTESWAP_MSK (MSK(1) << GT_PCI0_CMD_MBYTESWAP_SHF)
#define GT_PCI0_CMD_MBYTESWAP_BIT GT_PCI0_CMD_MBYTESWAP_MSK
#define GT_PCI0_CMD_MWORDSWAP_SHF 10
#define GT_PCI0_CMD_MWORDSWAP_MSK (MSK(1) << GT_PCI0_CMD_MWORDSWAP_SHF)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define GT_PCI0_CMD_MWORDSWAP_BIT GT_PCI0_CMD_MWORDSWAP_MSK
#define GT_PCI0_CMD_SBYTESWAP_SHF 16
#define GT_PCI0_CMD_SBYTESWAP_MSK (MSK(1) << GT_PCI0_CMD_SBYTESWAP_SHF)
#define GT_PCI0_CMD_SBYTESWAP_BIT GT_PCI0_CMD_SBYTESWAP_MSK
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define GT_PCI0_CMD_SWORDSWAP_SHF 11
#define GT_PCI0_CMD_SWORDSWAP_MSK (MSK(1) << GT_PCI0_CMD_SWORDSWAP_SHF)
#define GT_PCI0_CMD_SWORDSWAP_BIT GT_PCI0_CMD_SWORDSWAP_MSK
#define GT_INTR_T0EXP_SHF 8
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define GT_INTR_T0EXP_MSK (MSK(1) << GT_INTR_T0EXP_SHF)
#define GT_INTR_T0EXP_BIT GT_INTR_T0EXP_MSK
#define GT_INTR_RETRYCTR0_SHF 20
#define GT_INTR_RETRYCTR0_MSK (MSK(1) << GT_INTR_RETRYCTR0_SHF)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define GT_INTR_RETRYCTR0_BIT GT_INTR_RETRYCTR0_MSK
#define GT_DEF_PCI0_IO_BASE 0x10000000UL
#define GT_DEF_PCI0_IO_SIZE 0x02000000UL
#define GT_DEF_PCI0_MEM0_BASE 0x12000000UL
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define GT_DEF_PCI0_MEM0_SIZE 0x02000000UL
#define GT_DEF_BASE 0x14000000UL
#define GT_MAX_BANKSIZE (256 * 1024 * 1024)
#define GT_LATTIM_MIN 6
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#include <mach-gt64120.h>
#define __GT_READ(ofs) (*(volatile u32 *)(GT64120_BASE+(ofs)))
#define __GT_WRITE(ofs, data) do { *(volatile u32 *)(GT64120_BASE+(ofs)) = (data); } while (0)
#define GT_READ(ofs) le32_to_cpu(__GT_READ(ofs))
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define GT_WRITE(ofs, data) __GT_WRITE(ofs, cpu_to_le32(data))
#endif

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/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef _ASM_HARDIRQ_H
#define _ASM_HARDIRQ_H
#include <linux/threads.h>
#include <linux/irq.h>
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
typedef struct {
unsigned int __softirq_pending;
} ____cacheline_aligned irq_cpustat_t;
#include <linux/irq_cpustat.h>
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#endif

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libc/kernel/arch-mips/asm/hazards.h Normal file
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/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef _ASM_HAZARDS_H
#define _ASM_HAZARDS_H
#ifdef __ASSEMBLY__
#define ASMMACRO(name, code...) .macro name; code; .endm
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#else
#include <asm/cpu-features.h>
#define ASMMACRO(name, code...) __asm__(".macro " #name "; " #code "; .endm"); static inline void name(void) { __asm__ __volatile__ (#name); }
#endif
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define instruction_hazard() do { } while (0)
#endif

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libc/kernel/arch-mips/asm/hw_irq.h Normal file
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/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef __ASM_HW_IRQ_H
#define __ASM_HW_IRQ_H
#include <asm/atomic.h>
#endif
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */

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libc/kernel/arch-mips/asm/i8253.h Normal file
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/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef __ASM_I8253_H
#define __ASM_I8253_H
#include <linux/spinlock.h>
#define PIT_MODE 0x43
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PIT_CH0 0x40
#define PIT_CH2 0x42
#define PIT_TICK_RATE 1193182UL
#endif
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */

40
libc/kernel/arch-mips/asm/i8259.h Normal file
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/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef _ASM_I8259_H
#define _ASM_I8259_H
#include <linux/compiler.h>
#include <linux/spinlock.h>
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#include <asm/io.h>
#include <irq.h>
#define PIC_MASTER_CMD 0x20
#define PIC_MASTER_IMR 0x21
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PIC_MASTER_ISR PIC_MASTER_CMD
#define PIC_MASTER_POLL PIC_MASTER_ISR
#define PIC_MASTER_OCW3 PIC_MASTER_ISR
#define PIC_SLAVE_CMD 0xa0
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PIC_SLAVE_IMR 0xa1
#define PIC_CASCADE_IR 2
#define MASTER_ICW4_DEFAULT 0x01
#define SLAVE_ICW4_DEFAULT 0x01
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PIC_ICW4_AEOI 2
#endif

23
libc/kernel/arch-mips/asm/ide.h Normal file
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/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef __ASM_IDE_H
#define __ASM_IDE_H
#include <ide.h>
#endif
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */

113
libc/kernel/arch-mips/asm/io.h Normal file
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/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef _ASM_IO_H
#define _ASM_IO_H
#include <linux/compiler.h>
#include <linux/kernel.h>
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#include <linux/types.h>
#include <asm/addrspace.h>
#include <asm/byteorder.h>
#include <asm/cpu.h>
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#include <asm/cpu-features.h>
#include <asm-generic/iomap.h>
#include <asm/page.h>
#include <asm/pgtable-bits.h>
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#include <asm/processor.h>
#include <asm/string.h>
#include <ioremap.h>
#include <mangle-port.h>
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#undef CONF_SLOWDOWN_IO
#define __raw_ioswabb(a, x) (x)
#define __raw_ioswabw(a, x) (x)
#define __raw_ioswabl(a, x) (x)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define __raw_ioswabq(a, x) (x)
#define ____raw_ioswabq(a, x) (x)
#define IO_SPACE_LIMIT 0xffff
#define __SLOW_DOWN_IO __asm__ __volatile__( "sb\t$0,0x80(%0)" : : "r" (mips_io_port_base));
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#ifdef CONF_SLOWDOWN_IO
#ifdef REALLY_SLOW_IO
#define SLOW_DOWN_IO { __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; }
#else
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SLOW_DOWN_IO __SLOW_DOWN_IO
#endif
#else
#define SLOW_DOWN_IO
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#endif
#define isa_page_to_bus page_to_phys
#define virt_to_bus virt_to_phys
#define bus_to_virt phys_to_virt
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define page_to_phys(page) ((dma_addr_t)page_to_pfn(page) << PAGE_SHIFT)
#define __IS_LOW512(addr) (!((phys_t)(addr) & (phys_t) ~0x1fffffffULL))
#undef __IS_LOW512
#define ioremap(offset, size) __ioremap_mode((offset), (size), _CACHE_UNCACHED)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define ioremap_nocache(offset, size) __ioremap_mode((offset), (size), _CACHE_UNCACHED)
#define ioremap_cachable(offset, size) __ioremap_mode((offset), (size), _page_cachable_default)
#define ioremap_cacheable_cow(offset, size) __ioremap_mode((offset), (size), _CACHE_CACHABLE_COW)
#define ioremap_uncached_accelerated(offset, size) __ioremap_mode((offset), (size), _CACHE_UNCACHED_ACCELERATED)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define __IS_KSEG1(addr) (((unsigned long)(addr) & ~0x1fffffffUL) == CKSEG1)
#undef __IS_KSEG1
#define __BUILD_MEMORY_SINGLE(pfx, bwlq, type, irq) static inline void pfx##write##bwlq(type val, volatile void __iomem *mem) { volatile type *__mem; type __val; __mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem)); __val = pfx##ioswab##bwlq(__mem, val); if (sizeof(type) != sizeof(u64) || sizeof(u64) == sizeof(long)) *__mem = __val; else if (cpu_has_64bits) { unsigned long __flags; type __tmp; if (irq) local_irq_save(__flags); __asm__ __volatile__( ".set mips3" "\t\t# __writeq""\n\t" "dsll32 %L0, %L0, 0" "\n\t" "dsrl32 %L0, %L0, 0" "\n\t" "dsll32 %M0, %M0, 0" "\n\t" "or %L0, %L0, %M0" "\n\t" "sd %L0, %2" "\n\t" ".set mips0" "\n" : "=r" (__tmp) : "0" (__val), "m" (*__mem)); if (irq) local_irq_restore(__flags); } else BUG(); } static inline type pfx##read##bwlq(const volatile void __iomem *mem) { volatile type *__mem; type __val; __mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem)); if (sizeof(type) != sizeof(u64) || sizeof(u64) == sizeof(long)) __val = *__mem; else if (cpu_has_64bits) { unsigned long __flags; if (irq) local_irq_save(__flags); __asm__ __volatile__( ".set mips3" "\t\t# __readq" "\n\t" "ld %L0, %1" "\n\t" "dsra32 %M0, %L0, 0" "\n\t" "sll %L0, %L0, 0" "\n\t" ".set mips0" "\n" : "=r" (__val) : "m" (*__mem)); if (irq) local_irq_restore(__flags); } else { __val = 0; BUG(); } return pfx##ioswab##bwlq(__mem, __val); }
#define __BUILD_IOPORT_SINGLE(pfx, bwlq, type, p, slow) static inline void pfx##out##bwlq##p(type val, unsigned long port) { volatile type *__addr; type __val; __addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base + port); __val = pfx##ioswab##bwlq(__addr, val); BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long)); *__addr = __val; slow; } static inline type pfx##in##bwlq##p(unsigned long port) { volatile type *__addr; type __val; __addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base + port); BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long)); __val = *__addr; slow; return pfx##ioswab##bwlq(__addr, __val); }
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define __BUILD_MEMORY_PFX(bus, bwlq, type) __BUILD_MEMORY_SINGLE(bus, bwlq, type, 1)
#define BUILDIO_MEM(bwlq, type) __BUILD_MEMORY_PFX(__raw_, bwlq, type) __BUILD_MEMORY_PFX(, bwlq, type) __BUILD_MEMORY_PFX(__mem_, bwlq, type)
#define __BUILD_IOPORT_PFX(bus, bwlq, type) __BUILD_IOPORT_SINGLE(bus, bwlq, type, ,) __BUILD_IOPORT_SINGLE(bus, bwlq, type, _p, SLOW_DOWN_IO)
#define BUILDIO_IOPORT(bwlq, type) __BUILD_IOPORT_PFX(, bwlq, type) __BUILD_IOPORT_PFX(__mem_, bwlq, type)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define __BUILDIO(bwlq, type) __BUILD_MEMORY_SINGLE(____raw_, bwlq, type, 0)
#define readb_relaxed readb
#define readw_relaxed readw
#define readl_relaxed readl
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define readq_relaxed readq
#define readq readq
#define writeq writeq
#define __BUILD_MEMORY_STRING(bwlq, type) static inline void writes##bwlq(volatile void __iomem *mem, const void *addr, unsigned int count) { const volatile type *__addr = addr; while (count--) { __mem_write##bwlq(*__addr, mem); __addr++; } } static inline void reads##bwlq(volatile void __iomem *mem, void *addr, unsigned int count) { volatile type *__addr = addr; while (count--) { *__addr = __mem_read##bwlq(mem); __addr++; } }
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define __BUILD_IOPORT_STRING(bwlq, type) static inline void outs##bwlq(unsigned long port, const void *addr, unsigned int count) { const volatile type *__addr = addr; while (count--) { __mem_out##bwlq(*__addr, port); __addr++; } } static inline void ins##bwlq(unsigned long port, void *addr, unsigned int count) { volatile type *__addr = addr; while (count--) { *__addr = __mem_in##bwlq(port); __addr++; } }
#define BUILDSTRING(bwlq, type) __BUILD_MEMORY_STRING(bwlq, type) __BUILD_IOPORT_STRING(bwlq, type)
#define mmiowb() asm volatile ("sync" ::: "memory")
#define dma_cache_wback_inv(start,size) do { (void) (start); (void) (size); } while (0)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define dma_cache_wback(start,size) do { (void) (start); (void) (size); } while (0)
#define dma_cache_inv(start,size) do { (void) (start); (void) (size); } while (0)
#ifdef __MIPSEB__
#define __CSR_32_ADJUST 4
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#else
#define __CSR_32_ADJUST 0
#endif
#define csr_out32(v, a) (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST) = (v))
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define csr_in32(a) (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST))
#define xlate_dev_mem_ptr(p) __va(p)
#define xlate_dev_kmem_ptr(p) p
#endif
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */

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/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef _ASM_IOCTL_H
#define _ASM_IOCTL_H
#define _IOC_NRBITS 8
#define _IOC_TYPEBITS 8
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define _IOC_SIZEBITS 13
#define _IOC_DIRBITS 3
#define _IOC_NRMASK ((1 << _IOC_NRBITS)-1)
#define _IOC_TYPEMASK ((1 << _IOC_TYPEBITS)-1)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define _IOC_SIZEMASK ((1 << _IOC_SIZEBITS)-1)
#define _IOC_DIRMASK ((1 << _IOC_DIRBITS)-1)
#define _IOC_NRSHIFT 0
#define _IOC_TYPESHIFT (_IOC_NRSHIFT+_IOC_NRBITS)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define _IOC_SIZESHIFT (_IOC_TYPESHIFT+_IOC_TYPEBITS)
#define _IOC_DIRSHIFT (_IOC_SIZESHIFT+_IOC_SIZEBITS)
#define _IOC_NONE 1U
#define _IOC_READ 2U
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define _IOC_WRITE 4U
#define _IOC_VOID 0x20000000
#define _IOC_OUT 0x40000000
#define _IOC_IN 0x80000000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define _IOC_INOUT (IOC_IN|IOC_OUT)
#define _IOC(dir, type, nr, size) (((dir) << _IOC_DIRSHIFT) | ((type) << _IOC_TYPESHIFT) | ((nr) << _IOC_NRSHIFT) | ((size) << _IOC_SIZESHIFT))
extern unsigned int __invalid_size_argument_for_IOC;
#define _IOC_TYPECHECK(t) ((sizeof(t) == sizeof(t[1]) && sizeof(t) < (1 << _IOC_SIZEBITS)) ? sizeof(t) : __invalid_size_argument_for_IOC)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define _IO(type, nr) _IOC(_IOC_NONE, (type), (nr), 0)
#define _IOR(type, nr, size) _IOC(_IOC_READ, (type), (nr), (_IOC_TYPECHECK(size)))
#define _IOW(type, nr, size) _IOC(_IOC_WRITE, (type), (nr), (_IOC_TYPECHECK(size)))
#define _IOWR(type, nr, size) _IOC(_IOC_READ|_IOC_WRITE, (type), (nr), (_IOC_TYPECHECK(size)))
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define _IOR_BAD(type, nr, size) _IOC(_IOC_READ, (type), (nr), sizeof(size))
#define _IOW_BAD(type, nr, size) _IOC(_IOC_WRITE, (type), (nr), sizeof(size))
#define _IOWR_BAD(type, nr, size) _IOC(_IOC_READ|_IOC_WRITE, (type), (nr), sizeof(size))
#define _IOC_DIR(nr) (((nr) >> _IOC_DIRSHIFT) & _IOC_DIRMASK)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define _IOC_TYPE(nr) (((nr) >> _IOC_TYPESHIFT) & _IOC_TYPEMASK)
#define _IOC_NR(nr) (((nr) >> _IOC_NRSHIFT) & _IOC_NRMASK)
#define _IOC_SIZE(nr) (((nr) >> _IOC_SIZESHIFT) & _IOC_SIZEMASK)
#define IOC_IN (_IOC_WRITE << _IOC_DIRSHIFT)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IOC_OUT (_IOC_READ << _IOC_DIRSHIFT)
#define IOC_INOUT ((_IOC_WRITE|_IOC_READ) << _IOC_DIRSHIFT)
#define IOCSIZE_MASK (_IOC_SIZEMASK << _IOC_SIZESHIFT)
#define IOCSIZE_SHIFT (_IOC_SIZESHIFT)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#endif

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/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef __ASM_IOCTLS_H
#define __ASM_IOCTLS_H
#include <asm/ioctl.h>
#define TCGETA 0x5401
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define TCSETA 0x5402
#define TCSETAW 0x5403
#define TCSETAF 0x5404
#define TCSBRK 0x5405
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define TCXONC 0x5406
#define TCFLSH 0x5407
#define TCGETS 0x540d
#define TCSETS 0x540e
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define TCSETSW 0x540f
#define TCSETSF 0x5410
#define TIOCEXCL 0x740d
#define TIOCNXCL 0x740e
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define TIOCOUTQ 0x7472
#define TIOCSTI 0x5472
#define TIOCMGET 0x741d
#define TIOCMBIS 0x741b
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define TIOCMBIC 0x741c
#define TIOCMSET 0x741a
#define TIOCPKT 0x5470
#define TIOCPKT_DATA 0x00
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define TIOCPKT_FLUSHREAD 0x01
#define TIOCPKT_FLUSHWRITE 0x02
#define TIOCPKT_STOP 0x04
#define TIOCPKT_START 0x08
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define TIOCPKT_NOSTOP 0x10
#define TIOCPKT_DOSTOP 0x20
#define TIOCSWINSZ _IOW('t', 103, struct winsize)
#define TIOCGWINSZ _IOR('t', 104, struct winsize)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define TIOCNOTTY 0x5471
#define TIOCSETD 0x7401
#define TIOCGETD 0x7400
#define FIOCLEX 0x6601
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define FIONCLEX 0x6602
#define FIOASYNC 0x667d
#define FIONBIO 0x667e
#define FIOQSIZE 0x667f
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define TIOCGLTC 0x7474
#define TIOCSLTC 0x7475
#define TIOCSPGRP _IOW('t', 118, int)
#define TIOCGPGRP _IOR('t', 119, int)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define TIOCCONS _IOW('t', 120, int)
#define FIONREAD 0x467f
#define TIOCINQ FIONREAD
#define TIOCGETP 0x7408
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define TIOCSETP 0x7409
#define TIOCSETN 0x740a
#define TIOCSBRK 0x5427
#define TIOCCBRK 0x5428
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define TIOCGSID 0x7416
#define TCGETS2 _IOR('T', 0x2A, struct termios2)
#define TCSETS2 _IOW('T', 0x2B, struct termios2)
#define TCSETSW2 _IOW('T', 0x2C, struct termios2)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define TCSETSF2 _IOW('T', 0x2D, struct termios2)
#define TIOCGPTN _IOR('T', 0x30, unsigned int)
#define TIOCSPTLCK _IOW('T', 0x31, int)
#define TIOCSCTTY 0x5480
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define TIOCGSOFTCAR 0x5481
#define TIOCSSOFTCAR 0x5482
#define TIOCLINUX 0x5483
#define TIOCGSERIAL 0x5484
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define TIOCSSERIAL 0x5485
#define TCSBRKP 0x5486
#define TIOCSERCONFIG 0x5488
#define TIOCSERGWILD 0x5489
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define TIOCSERSWILD 0x548a
#define TIOCGLCKTRMIOS 0x548b
#define TIOCSLCKTRMIOS 0x548c
#define TIOCSERGSTRUCT 0x548d
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define TIOCSERGETLSR 0x548e
#define TIOCSERGETMULTI 0x548f
#define TIOCSERSETMULTI 0x5490
#define TIOCMIWAIT 0x5491
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define TIOCGICOUNT 0x5492
#define TIOCGHAYESESP 0x5493
#define TIOCSHAYESESP 0x5494
#endif
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */

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/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef __ASM_CRIME_H__
#define __ASM_CRIME_H__
#define CRIME_BASE 0x14000000
struct sgi_crime {
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
volatile unsigned long id;
#define CRIME_ID_MASK 0xff
#define CRIME_ID_IDBITS 0xf0
#define CRIME_ID_IDVALUE 0xa0
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define CRIME_ID_REV 0x0f
#define CRIME_REV_PETTY 0x00
#define CRIME_REV_11 0x11
#define CRIME_REV_13 0x13
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define CRIME_REV_14 0x14
volatile unsigned long control;
#define CRIME_CONTROL_MASK 0x3fff
#define CRIME_CONTROL_TRITON_SYSADC 0x2000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define CRIME_CONTROL_CRIME_SYSADC 0x1000
#define CRIME_CONTROL_HARD_RESET 0x0800
#define CRIME_CONTROL_SOFT_RESET 0x0400
#define CRIME_CONTROL_DOG_ENA 0x0200
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define CRIME_CONTROL_ENDIANESS 0x0100
#define CRIME_CONTROL_ENDIAN_BIG 0x0100
#define CRIME_CONTROL_ENDIAN_LITTLE 0x0000
#define CRIME_CONTROL_CQUEUE_HWM 0x000f
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define CRIME_CONTROL_CQUEUE_SHFT 0
#define CRIME_CONTROL_WBUF_HWM 0x00f0
#define CRIME_CONTROL_WBUF_SHFT 8
volatile unsigned long istat;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
volatile unsigned long imask;
volatile unsigned long soft_int;
volatile unsigned long hard_int;
#define MACE_VID_IN1_INT BIT(0)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MACE_VID_IN2_INT BIT(1)
#define MACE_VID_OUT_INT BIT(2)
#define MACE_ETHERNET_INT BIT(3)
#define MACE_SUPERIO_INT BIT(4)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MACE_MISC_INT BIT(5)
#define MACE_AUDIO_INT BIT(6)
#define MACE_PCI_BRIDGE_INT BIT(7)
#define MACEPCI_SCSI0_INT BIT(8)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MACEPCI_SCSI1_INT BIT(9)
#define MACEPCI_SLOT0_INT BIT(10)
#define MACEPCI_SLOT1_INT BIT(11)
#define MACEPCI_SLOT2_INT BIT(12)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MACEPCI_SHARED0_INT BIT(13)
#define MACEPCI_SHARED1_INT BIT(14)
#define MACEPCI_SHARED2_INT BIT(15)
#define CRIME_GBE0_INT BIT(16)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define CRIME_GBE1_INT BIT(17)
#define CRIME_GBE2_INT BIT(18)
#define CRIME_GBE3_INT BIT(19)
#define CRIME_CPUERR_INT BIT(20)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define CRIME_MEMERR_INT BIT(21)
#define CRIME_RE_EMPTY_E_INT BIT(22)
#define CRIME_RE_FULL_E_INT BIT(23)
#define CRIME_RE_IDLE_E_INT BIT(24)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define CRIME_RE_EMPTY_L_INT BIT(25)
#define CRIME_RE_FULL_L_INT BIT(26)
#define CRIME_RE_IDLE_L_INT BIT(27)
#define CRIME_SOFT0_INT BIT(28)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define CRIME_SOFT1_INT BIT(29)
#define CRIME_SOFT2_INT BIT(30)
#define CRIME_SYSCORERR_INT CRIME_SOFT2_INT
#define CRIME_VICE_INT BIT(31)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define CRIME_MACE_INT_MASK 0x8f
#define CRIME_MACEISA_INT_MASK 0x70
#define CRIME_MACEPCI_INT_MASK 0xff00
#define CRIME_CRIME_INT_MASK 0xffff0000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
volatile unsigned long watchdog;
#define CRIME_DOG_POWER_ON_RESET 0x00010000
#define CRIME_DOG_WARM_RESET 0x00080000
#define CRIME_DOG_TIMEOUT (CRIME_DOG_POWER_ON_RESET|CRIME_DOG_WARM_RESET)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define CRIME_DOG_VALUE 0x00007fff
volatile unsigned long timer;
#define CRIME_MASTER_FREQ 66666500
#define CRIME_NS_PER_TICK 15
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
volatile unsigned long cpu_error_addr;
#define CRIME_CPU_ERROR_ADDR_MASK 0x3ffffffff
volatile unsigned long cpu_error_stat;
#define CRIME_CPU_ERROR_MASK 0x7
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define CRIME_CPU_ERROR_CPU_ILL_ADDR 0x4
#define CRIME_CPU_ERROR_VICE_WRT_PRTY 0x2
#define CRIME_CPU_ERROR_CPU_WRT_PRTY 0x1
unsigned long _pad0[54];
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
volatile unsigned long mc_ctrl;
volatile unsigned long bank_ctrl[8];
#define CRIME_MEM_BANK_CONTROL_MASK 0x11f
#define CRIME_MEM_BANK_CONTROL_ADDR 0x01f
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define CRIME_MEM_BANK_CONTROL_SDRAM_SIZE 0x100
#define CRIME_MAXBANKS 8
volatile unsigned long mem_ref_counter;
#define CRIME_MEM_REF_COUNTER_MASK 0x3ff
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
volatile unsigned long mem_error_stat;
#define CRIME_MEM_ERROR_STAT_MASK 0x0ff7ffff
#define CRIME_MEM_ERROR_MACE_ID 0x0000007f
#define CRIME_MEM_ERROR_MACE_ACCESS 0x00000080
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define CRIME_MEM_ERROR_RE_ID 0x00007f00
#define CRIME_MEM_ERROR_RE_ACCESS 0x00008000
#define CRIME_MEM_ERROR_GBE_ACCESS 0x00010000
#define CRIME_MEM_ERROR_VICE_ACCESS 0x00020000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define CRIME_MEM_ERROR_CPU_ACCESS 0x00040000
#define CRIME_MEM_ERROR_RESERVED 0x00080000
#define CRIME_MEM_ERROR_SOFT_ERR 0x00100000
#define CRIME_MEM_ERROR_HARD_ERR 0x00200000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define CRIME_MEM_ERROR_MULTIPLE 0x00400000
#define CRIME_MEM_ERROR_ECC 0x01800000
#define CRIME_MEM_ERROR_MEM_ECC_RD 0x00800000
#define CRIME_MEM_ERROR_MEM_ECC_RMW 0x01000000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define CRIME_MEM_ERROR_INV 0x0e000000
#define CRIME_MEM_ERROR_INV_MEM_ADDR_RD 0x02000000
#define CRIME_MEM_ERROR_INV_MEM_ADDR_WR 0x04000000
#define CRIME_MEM_ERROR_INV_MEM_ADDR_RMW 0x08000000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
volatile unsigned long mem_error_addr;
#define CRIME_MEM_ERROR_ADDR_MASK 0x3fffffff
volatile unsigned long mem_ecc_syn;
#define CRIME_MEM_ERROR_ECC_SYN_MASK 0xffffffff
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
volatile unsigned long mem_ecc_chk;
#define CRIME_MEM_ERROR_ECC_CHK_MASK 0xffffffff
volatile unsigned long mem_ecc_repl;
#define CRIME_MEM_ERROR_ECC_REPL_MASK 0xffffffff
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
};
#define CRIME_HI_MEM_BASE 0x40000000
#endif

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/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef __ASM_MACE_H__
#define __ASM_MACE_H__
#define MACE_BASE 0x1f000000
struct mace_pci {
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
volatile unsigned int error_addr;
volatile unsigned int error;
#define MACEPCI_ERROR_MASTER_ABORT BIT(31)
#define MACEPCI_ERROR_TARGET_ABORT BIT(30)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MACEPCI_ERROR_DATA_PARITY_ERR BIT(29)
#define MACEPCI_ERROR_RETRY_ERR BIT(28)
#define MACEPCI_ERROR_ILLEGAL_CMD BIT(27)
#define MACEPCI_ERROR_SYSTEM_ERR BIT(26)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MACEPCI_ERROR_INTERRUPT_TEST BIT(25)
#define MACEPCI_ERROR_PARITY_ERR BIT(24)
#define MACEPCI_ERROR_OVERRUN BIT(23)
#define MACEPCI_ERROR_RSVD BIT(22)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MACEPCI_ERROR_MEMORY_ADDR BIT(21)
#define MACEPCI_ERROR_CONFIG_ADDR BIT(20)
#define MACEPCI_ERROR_MASTER_ABORT_ADDR_VALID BIT(19)
#define MACEPCI_ERROR_TARGET_ABORT_ADDR_VALID BIT(18)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MACEPCI_ERROR_DATA_PARITY_ADDR_VALID BIT(17)
#define MACEPCI_ERROR_RETRY_ADDR_VALID BIT(16)
#define MACEPCI_ERROR_SIG_TABORT BIT(4)
#define MACEPCI_ERROR_DEVSEL_MASK 0xc0
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MACEPCI_ERROR_DEVSEL_FAST 0
#define MACEPCI_ERROR_DEVSEL_MED 0x40
#define MACEPCI_ERROR_DEVSEL_SLOW 0x80
#define MACEPCI_ERROR_FBB BIT(1)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MACEPCI_ERROR_66MHZ BIT(0)
volatile unsigned int control;
#define MACEPCI_CONTROL_INT(x) BIT(x)
#define MACEPCI_CONTROL_INT_MASK 0xff
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MACEPCI_CONTROL_SERR_ENA BIT(8)
#define MACEPCI_CONTROL_ARB_N6 BIT(9)
#define MACEPCI_CONTROL_PARITY_ERR BIT(10)
#define MACEPCI_CONTROL_MRMRA_ENA BIT(11)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MACEPCI_CONTROL_ARB_N3 BIT(12)
#define MACEPCI_CONTROL_ARB_N4 BIT(13)
#define MACEPCI_CONTROL_ARB_N5 BIT(14)
#define MACEPCI_CONTROL_PARK_LIU BIT(15)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MACEPCI_CONTROL_INV_INT(x) BIT(16+x)
#define MACEPCI_CONTROL_INV_INT_MASK 0x00ff0000
#define MACEPCI_CONTROL_OVERRUN_INT BIT(24)
#define MACEPCI_CONTROL_PARITY_INT BIT(25)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MACEPCI_CONTROL_SERR_INT BIT(26)
#define MACEPCI_CONTROL_IT_INT BIT(27)
#define MACEPCI_CONTROL_RE_INT BIT(28)
#define MACEPCI_CONTROL_DPED_INT BIT(29)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MACEPCI_CONTROL_TAR_INT BIT(30)
#define MACEPCI_CONTROL_MAR_INT BIT(31)
volatile unsigned int rev;
unsigned int _pad[0xcf8/4 - 4];
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
volatile unsigned int config_addr;
union {
volatile unsigned char b[4];
volatile unsigned short w[2];
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
volatile unsigned int l;
} config_data;
};
#define MACEPCI_LOW_MEMORY 0x1a000000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MACEPCI_LOW_IO 0x18000000
#define MACEPCI_SWAPPED_VIEW 0
#define MACEPCI_NATIVE_VIEW 0x40000000
#define MACEPCI_IO 0x80000000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MACEPCI_HI_MEMORY 0x280000000
#define MACEPCI_HI_IO 0x100000000
struct mace_video {
unsigned long xxx;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
};
struct mace_ethernet {
volatile unsigned long mac_ctrl;
volatile unsigned long int_stat;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
volatile unsigned long dma_ctrl;
volatile unsigned long timer;
volatile unsigned long tx_int_al;
volatile unsigned long rx_int_al;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
volatile unsigned long tx_info;
volatile unsigned long tx_info_al;
volatile unsigned long rx_buff;
volatile unsigned long rx_buff_al1;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
volatile unsigned long rx_buff_al2;
volatile unsigned long diag;
volatile unsigned long phy_data;
volatile unsigned long phy_regs;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
volatile unsigned long phy_trans_go;
volatile unsigned long backoff_seed;
volatile unsigned long imq_reserved[4];
volatile unsigned long mac_addr;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
volatile unsigned long mac_addr2;
volatile unsigned long mcast_filter;
volatile unsigned long tx_ring_base;
volatile unsigned long tx_pkt1_hdr;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
volatile unsigned long tx_pkt1_ptr[3];
volatile unsigned long tx_pkt2_hdr;
volatile unsigned long tx_pkt2_ptr[3];
volatile unsigned long rx_fifo;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
};
struct mace_audio {
volatile unsigned long control;
volatile unsigned long codec_control;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
volatile unsigned long codec_mask;
volatile unsigned long codec_read;
struct {
volatile unsigned long control;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
volatile unsigned long read_ptr;
volatile unsigned long write_ptr;
volatile unsigned long depth;
} chan[3];
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
};
struct mace_parport {
#define MACEPAR_CONTEXT_LASTFLAG BIT(63)
#define MACEPAR_CONTEXT_DATA_BOUND 0x0000000000001000UL
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MACEPAR_CONTEXT_DATALEN_MASK 0x00000fff00000000UL
#define MACEPAR_CONTEXT_DATALEN_SHIFT 32
#define MACEPAR_CONTEXT_BASEADDR_MASK 0x00000000ffffffffUL
volatile u64 context_a;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
volatile u64 context_b;
#define MACEPAR_CTLSTAT_DIRECTION BIT(0)
#define MACEPAR_CTLSTAT_ENABLE BIT(1)
#define MACEPAR_CTLSTAT_RESET BIT(2)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MACEPAR_CTLSTAT_CTXB_VALID BIT(3)
#define MACEPAR_CTLSTAT_CTXA_VALID BIT(4)
volatile u64 cntlstat;
#define MACEPAR_DIAG_CTXINUSE BIT(0)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MACEPAR_DIAG_DMACTIVE BIT(1)
#define MACEPAR_DIAG_CTRMASK 0x0000000000003ffcUL
#define MACEPAR_DIAG_CTRSHIFT 2
volatile u64 diagnostic;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
};
struct mace_isactrl {
volatile unsigned long ringbase;
#define MACEISA_RINGBUFFERS_SIZE (8 * 4096)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
volatile unsigned long misc;
#define MACEISA_FLASH_WE BIT(0)
#define MACEISA_PWD_CLEAR BIT(1)
#define MACEISA_NIC_DEASSERT BIT(2)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MACEISA_NIC_DATA BIT(3)
#define MACEISA_LED_RED BIT(4)
#define MACEISA_LED_GREEN BIT(5)
#define MACEISA_DP_RAM_ENABLE BIT(6)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
volatile unsigned long istat;
volatile unsigned long imask;
#define MACEISA_AUDIO_SW_INT BIT(0)
#define MACEISA_AUDIO_SC_INT BIT(1)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MACEISA_AUDIO1_DMAT_INT BIT(2)
#define MACEISA_AUDIO1_OF_INT BIT(3)
#define MACEISA_AUDIO2_DMAT_INT BIT(4)
#define MACEISA_AUDIO2_MERR_INT BIT(5)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MACEISA_AUDIO3_DMAT_INT BIT(6)
#define MACEISA_AUDIO3_MERR_INT BIT(7)
#define MACEISA_RTC_INT BIT(8)
#define MACEISA_KEYB_INT BIT(9)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MACEISA_KEYB_POLL_INT BIT(10)
#define MACEISA_MOUSE_INT BIT(11)
#define MACEISA_MOUSE_POLL_INT BIT(12)
#define MACEISA_TIMER0_INT BIT(13)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MACEISA_TIMER1_INT BIT(14)
#define MACEISA_TIMER2_INT BIT(15)
#define MACEISA_PARALLEL_INT BIT(16)
#define MACEISA_PAR_CTXA_INT BIT(17)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MACEISA_PAR_CTXB_INT BIT(18)
#define MACEISA_PAR_MERR_INT BIT(19)
#define MACEISA_SERIAL1_INT BIT(20)
#define MACEISA_SERIAL1_TDMAT_INT BIT(21)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MACEISA_SERIAL1_TDMAPR_INT BIT(22)
#define MACEISA_SERIAL1_TDMAME_INT BIT(23)
#define MACEISA_SERIAL1_RDMAT_INT BIT(24)
#define MACEISA_SERIAL1_RDMAOR_INT BIT(25)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MACEISA_SERIAL2_INT BIT(26)
#define MACEISA_SERIAL2_TDMAT_INT BIT(27)
#define MACEISA_SERIAL2_TDMAPR_INT BIT(28)
#define MACEISA_SERIAL2_TDMAME_INT BIT(29)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MACEISA_SERIAL2_RDMAT_INT BIT(30)
#define MACEISA_SERIAL2_RDMAOR_INT BIT(31)
volatile unsigned long _pad[0x2000/8 - 4];
volatile unsigned long dp_ram[0x400];
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
struct mace_parport parport;
};
struct mace_ps2port {
volatile unsigned long tx;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
volatile unsigned long rx;
volatile unsigned long control;
volatile unsigned long status;
};
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
struct mace_ps2 {
struct mace_ps2port keyb;
struct mace_ps2port mouse;
};
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
struct mace_i2c {
volatile unsigned long config;
#define MACEI2C_RESET BIT(0)
#define MACEI2C_FAST BIT(1)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MACEI2C_DATA_OVERRIDE BIT(2)
#define MACEI2C_CLOCK_OVERRIDE BIT(3)
#define MACEI2C_DATA_STATUS BIT(4)
#define MACEI2C_CLOCK_STATUS BIT(5)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
volatile unsigned long control;
volatile unsigned long data;
};
typedef union {
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
volatile unsigned long ust_msc;
struct reg {
volatile unsigned int ust;
volatile unsigned int msc;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
} reg;
} timer_reg;
struct mace_timers {
volatile unsigned long ust;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MACE_UST_PERIOD_NS 960
volatile unsigned long compare1;
volatile unsigned long compare2;
volatile unsigned long compare3;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
timer_reg audio_in;
timer_reg audio_out1;
timer_reg audio_out2;
timer_reg video_in1;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
timer_reg video_in2;
timer_reg video_out;
};
struct mace_perif {
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
struct mace_audio audio;
char _pad0[0x10000 - sizeof(struct mace_audio)];
struct mace_isactrl ctrl;
char _pad1[0x10000 - sizeof(struct mace_isactrl)];
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
struct mace_ps2 ps2;
char _pad2[0x10000 - sizeof(struct mace_ps2)];
struct mace_i2c i2c;
char _pad3[0x10000 - sizeof(struct mace_i2c)];
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
struct mace_timers timers;
char _pad4[0x10000 - sizeof(struct mace_timers)];
};
struct mace_parallel {
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
};
struct mace_ecp1284 {
};
struct mace_serial {
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
volatile unsigned long xxx;
};
struct mace_isa {
struct mace_parallel parallel;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
char _pad1[0x8000 - sizeof(struct mace_parallel)];
struct mace_ecp1284 ecp1284;
char _pad2[0x8000 - sizeof(struct mace_ecp1284)];
struct mace_serial serial1;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
char _pad3[0x8000 - sizeof(struct mace_serial)];
struct mace_serial serial2;
char _pad4[0x8000 - sizeof(struct mace_serial)];
volatile unsigned char rtc[0x10000];
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
};
struct sgi_mace {
char _reserved[0x80000];
struct mace_pci pci;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
char _pad0[0x80000 - sizeof(struct mace_pci)];
struct mace_video video_in1;
char _pad1[0x80000 - sizeof(struct mace_video)];
struct mace_video video_in2;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
char _pad2[0x80000 - sizeof(struct mace_video)];
struct mace_video video_out;
char _pad3[0x80000 - sizeof(struct mace_video)];
struct mace_ethernet eth;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
char _pad4[0x80000 - sizeof(struct mace_ethernet)];
struct mace_perif perif;
char _pad5[0x80000 - sizeof(struct mace_perif)];
struct mace_isa isa;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
char _pad6[0x80000 - sizeof(struct mace_isa)];
};
#endif

38
libc/kernel/arch-mips/asm/ipcbuf.h Normal file
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/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef _ASM_IPCBUF_H
#define _ASM_IPCBUF_H
struct ipc64_perm
{
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
__kernel_key_t key;
__kernel_uid_t uid;
__kernel_gid_t gid;
__kernel_uid_t cuid;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
__kernel_gid_t cgid;
__kernel_mode_t mode;
unsigned short seq;
unsigned short __pad1;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
unsigned long __unused1;
unsigned long __unused2;
};
#endif
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */

33
libc/kernel/arch-mips/asm/irq.h Normal file
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/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef _ASM_IRQ_H
#define _ASM_IRQ_H
#include <linux/linkage.h>
#include <asm/mipsmtregs.h>
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#include <irq.h>
#define irq_canonicalize(irq) (irq)
#define IRQ_AFFINITY_HOOK(irq) do { } while (0)
#define __DO_IRQ_SMTC_HOOK(irq) do { IRQ_AFFINITY_HOOK(irq); } while (0)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define __NO_AFFINITY_IRQ_SMTC_HOOK(irq) do { } while (0)
#define do_IRQ(irq) do { irq_enter(); __DO_IRQ_SMTC_HOOK(irq); generic_handle_irq(irq); irq_exit(); } while (0)
#define CP0_LEGACY_COMPARE_IRQ 7
#endif
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */

61
libc/kernel/arch-mips/asm/irq_gt641xx.h Normal file
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/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef _ASM_IRQ_GT641XX_H
#define _ASM_IRQ_GT641XX_H
#ifndef GT641XX_IRQ_BASE
#define GT641XX_IRQ_BASE 8
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#endif
#define GT641XX_MEMORY_OUT_OF_RANGE_IRQ (GT641XX_IRQ_BASE + 1)
#define GT641XX_DMA_OUT_OF_RANGE_IRQ (GT641XX_IRQ_BASE + 2)
#define GT641XX_CPU_ACCESS_OUT_OF_RANGE_IRQ (GT641XX_IRQ_BASE + 3)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define GT641XX_DMA0_IRQ (GT641XX_IRQ_BASE + 4)
#define GT641XX_DMA1_IRQ (GT641XX_IRQ_BASE + 5)
#define GT641XX_DMA2_IRQ (GT641XX_IRQ_BASE + 6)
#define GT641XX_DMA3_IRQ (GT641XX_IRQ_BASE + 7)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define GT641XX_TIMER0_IRQ (GT641XX_IRQ_BASE + 8)
#define GT641XX_TIMER1_IRQ (GT641XX_IRQ_BASE + 9)
#define GT641XX_TIMER2_IRQ (GT641XX_IRQ_BASE + 10)
#define GT641XX_TIMER3_IRQ (GT641XX_IRQ_BASE + 11)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define GT641XX_PCI_0_MASTER_READ_ERROR_IRQ (GT641XX_IRQ_BASE + 12)
#define GT641XX_PCI_0_SLAVE_WRITE_ERROR_IRQ (GT641XX_IRQ_BASE + 13)
#define GT641XX_PCI_0_MASTER_WRITE_ERROR_IRQ (GT641XX_IRQ_BASE + 14)
#define GT641XX_PCI_0_SLAVE_READ_ERROR_IRQ (GT641XX_IRQ_BASE + 15)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define GT641XX_PCI_0_ADDRESS_ERROR_IRQ (GT641XX_IRQ_BASE + 16)
#define GT641XX_MEMORY_ERROR_IRQ (GT641XX_IRQ_BASE + 17)
#define GT641XX_PCI_0_MASTER_ABORT_IRQ (GT641XX_IRQ_BASE + 18)
#define GT641XX_PCI_0_TARGET_ABORT_IRQ (GT641XX_IRQ_BASE + 19)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define GT641XX_PCI_0_RETRY_TIMEOUT_IRQ (GT641XX_IRQ_BASE + 20)
#define GT641XX_CPU_INT0_IRQ (GT641XX_IRQ_BASE + 21)
#define GT641XX_CPU_INT1_IRQ (GT641XX_IRQ_BASE + 22)
#define GT641XX_CPU_INT2_IRQ (GT641XX_IRQ_BASE + 23)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define GT641XX_CPU_INT3_IRQ (GT641XX_IRQ_BASE + 24)
#define GT641XX_CPU_INT4_IRQ (GT641XX_IRQ_BASE + 25)
#define GT641XX_PCI_INT0_IRQ (GT641XX_IRQ_BASE + 26)
#define GT641XX_PCI_INT1_IRQ (GT641XX_IRQ_BASE + 27)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define GT641XX_PCI_INT2_IRQ (GT641XX_IRQ_BASE + 28)
#define GT641XX_PCI_INT3_IRQ (GT641XX_IRQ_BASE + 29)
#endif

24
libc/kernel/arch-mips/asm/irq_regs.h Normal file
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/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef __ASM_IRQ_REGS_H
#define __ASM_IRQ_REGS_H
#define ARCH_HAS_OWN_IRQ_REGS
#include <linux/thread_info.h>
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#endif

168
libc/kernel/arch-mips/asm/jazz.h Normal file
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/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef __ASM_JAZZ_H
#define __ASM_JAZZ_H
#define JAZZ_LOCAL_IO_SPACE 0xe0000000
#define PICA_ASIC_REVISION 0xe0000008
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PICA_LED 0xe000f000
#define LED_DOT 0x01
#define LED_SPACE 0x00
#define LED_0 0xfc
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define LED_1 0x60
#define LED_2 0xda
#define LED_3 0xf2
#define LED_4 0x66
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define LED_5 0xb6
#define LED_6 0xbe
#define LED_7 0xe0
#define LED_8 0xfe
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define LED_9 0xf6
#define LED_A 0xee
#define LED_b 0x3e
#define LED_C 0x9c
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define LED_d 0x7a
#define LED_E 0x9e
#define LED_F 0x8e
#ifndef __ASSEMBLY__
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#endif
#define JAZZ_ETHERNET_BASE 0xe0001000
#define JAZZ_SCSI_BASE 0xe0002000
#define JAZZ_KEYBOARD_ADDRESS 0xe0005000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define JAZZ_KEYBOARD_DATA 0xe0005000
#define JAZZ_KEYBOARD_COMMAND 0xe0005001
#ifndef __ASSEMBLY__
typedef struct {
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
unsigned char data;
unsigned char command;
} jazz_keyboard_hardware;
#define jazz_kh ((keyboard_hardware *) JAZZ_KEYBOARD_ADDRESS)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
typedef struct {
unsigned char pad0[3];
unsigned char data;
unsigned char pad1[3];
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
unsigned char command;
} mips_keyboard_hardware;
#define keyboard_hardware jazz_keyboard_hardware
#endif
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MIPS_KEYBOARD_ADDRESS 0xb9005000
#define MIPS_KEYBOARD_DATA 0xb9005003
#define MIPS_KEYBOARD_COMMAND 0xb9005007
#define JAZZ_SERIAL1_BASE (unsigned int)0xe0006000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define JAZZ_SERIAL2_BASE (unsigned int)0xe0007000
#define JAZZ_PARALLEL_BASE (unsigned int)0xe0008000
#define JAZZ_DUMMY_DEVICE 0xe000d000
#define JAZZ_TIMER_INTERVAL 0xe0000228
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define JAZZ_TIMER_REGISTER 0xe0000230
#ifndef __ASSEMBLY__
#ifdef __MIPSEL__
typedef struct {
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
unsigned int bank2 : 3;
unsigned int bank1 : 3;
unsigned int mem_bus_width : 1;
unsigned int reserved2 : 1;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
unsigned int page_mode : 1;
unsigned int reserved1 : 23;
} dram_configuration;
#else
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
typedef struct {
unsigned int reserved1 : 23;
unsigned int page_mode : 1;
unsigned int reserved2 : 1;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
unsigned int mem_bus_width : 1;
unsigned int bank1 : 3;
unsigned int bank2 : 3;
} dram_configuration;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#endif
#endif
#define PICA_DRAM_CONFIG 0xe00fffe0
#define JAZZ_IO_IRQ_SOURCE 0xe0010000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define JAZZ_IO_IRQ_ENABLE 0xe0010002
#define JAZZ_IRQ_START 24
#define JAZZ_IRQ_END (24 + 9)
#define JAZZ_PARALLEL_IRQ (JAZZ_IRQ_START + 0)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define JAZZ_FLOPPY_IRQ (JAZZ_IRQ_START + 1)
#define JAZZ_SOUND_IRQ (JAZZ_IRQ_START + 2)
#define JAZZ_VIDEO_IRQ (JAZZ_IRQ_START + 3)
#define JAZZ_ETHERNET_IRQ (JAZZ_IRQ_START + 4)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define JAZZ_SCSI_IRQ (JAZZ_IRQ_START + 5)
#define JAZZ_KEYBOARD_IRQ (JAZZ_IRQ_START + 6)
#define JAZZ_MOUSE_IRQ (JAZZ_IRQ_START + 7)
#define JAZZ_SERIAL1_IRQ (JAZZ_IRQ_START + 8)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define JAZZ_SERIAL2_IRQ (JAZZ_IRQ_START + 9)
#define JAZZ_TIMER_IRQ (MIPS_CPU_IRQ_BASE+6)
#define JAZZ_SCSI_DMA 0
#define JAZZ_FLOPPY_DMA 1
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define JAZZ_AUDIOL_DMA 2
#define JAZZ_AUDIOR_DMA 3
#define JAZZ_R4030_CONFIG 0xE0000000
#define JAZZ_R4030_REVISION 0xE0000008
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define JAZZ_R4030_INV_ADDR 0xE0000010
#define JAZZ_R4030_TRSTBL_BASE 0xE0000018
#define JAZZ_R4030_TRSTBL_LIM 0xE0000020
#define JAZZ_R4030_TRSTBL_INV 0xE0000028
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define JAZZ_R4030_CACHE_MTNC 0xE0000030
#define JAZZ_R4030_R_FAIL_ADDR 0xE0000038
#define JAZZ_R4030_M_FAIL_ADDR 0xE0000040
#define JAZZ_R4030_CACHE_PTAG 0xE0000048
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define JAZZ_R4030_CACHE_LTAG 0xE0000050
#define JAZZ_R4030_CACHE_BMASK 0xE0000058
#define JAZZ_R4030_CACHE_BWIN 0xE0000060
#define JAZZ_R4030_REM_SPEED 0xE0000070
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define JAZZ_R4030_IRQ_ENABLE 0xE00000E8
#define JAZZ_R4030_INVAL_ADDR 0xE0000010
#define JAZZ_R4030_IRQ_SOURCE 0xE0000200
#define JAZZ_R4030_I386_ERROR 0xE0000208
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define JAZZ_EISA_IRQ_ACK 0xE0000238
#ifndef __ASSEMBLY__
#endif
#define JAZZ_FDC_BASE 0xe0003000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define JAZZ_RTC_BASE 0xe0004000
#define JAZZ_PORT_BASE 0xe2000000
#define JAZZ_EISA_BASE 0xe3000000
#endif
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */

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/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef _ASM_JAZZDMA_H
#define _ASM_JAZZDMA_H
#define VDMA_PAGESIZE 4096
#define VDMA_PGTBL_ENTRIES 4096
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define VDMA_PGTBL_SIZE (sizeof(VDMA_PGTBL_ENTRY) * VDMA_PGTBL_ENTRIES)
#define VDMA_PAGE_EMPTY 0xff000000
#define VDMA_PAGE(a) ((unsigned int)(a) >> 12)
#define VDMA_OFFSET(a) ((unsigned int)(a) & (VDMA_PAGESIZE-1))
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define VDMA_ERROR 0xffffffff
typedef volatile struct VDMA_PGTBL_ENTRY {
unsigned int frame;
unsigned int owner;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
} VDMA_PGTBL_ENTRY;
#define JAZZ_R4030_CHNL_MODE 0xE0000100
#define JAZZ_R4030_CHNL_ENABLE 0xE0000108
#define JAZZ_R4030_CHNL_COUNT 0xE0000110
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define JAZZ_R4030_CHNL_ADDR 0xE0000118
#define R4030_CHNL_ENABLE (1<<0)
#define R4030_CHNL_WRITE (1<<1)
#define R4030_TC_INTR (1<<8)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define R4030_MEM_INTR (1<<9)
#define R4030_ADDR_INTR (1<<10)
#define R4030_MODE_ATIME_40 (0)
#define R4030_MODE_ATIME_80 (1)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define R4030_MODE_ATIME_120 (2)
#define R4030_MODE_ATIME_160 (3)
#define R4030_MODE_ATIME_200 (4)
#define R4030_MODE_ATIME_240 (5)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define R4030_MODE_ATIME_280 (6)
#define R4030_MODE_ATIME_320 (7)
#define R4030_MODE_WIDTH_8 (1<<3)
#define R4030_MODE_WIDTH_16 (2<<3)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define R4030_MODE_WIDTH_32 (3<<3)
#define R4030_MODE_INTR_EN (1<<5)
#define R4030_MODE_BURST (1<<6)
#define R4030_MODE_FAST_ACK (1<<7)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#endif

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libc/kernel/arch-mips/asm/kdebug.h Normal file
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/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef _ASM_MIPS_KDEBUG_H
#define _ASM_MIPS_KDEBUG_H
#include <linux/notifier.h>
enum die_val {
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
DIE_OOPS = 1,
DIE_FP,
DIE_TRAP,
DIE_RI,
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
};
#endif

44
libc/kernel/arch-mips/asm/kmap_types.h Normal file
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/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef _ASM_KMAP_TYPES_H
#define _ASM_KMAP_TYPES_H
#define D(n)
enum km_type {
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
D(0) KM_BOUNCE_READ,
D(1) KM_SKB_SUNRPC_DATA,
D(2) KM_SKB_DATA_SOFTIRQ,
D(3) KM_USER0,
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
D(4) KM_USER1,
D(5) KM_BIO_SRC_IRQ,
D(6) KM_BIO_DST_IRQ,
D(7) KM_PTE0,
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
D(8) KM_PTE1,
D(9) KM_IRQ0,
D(10) KM_IRQ1,
D(11) KM_SOFTIRQ0,
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
D(12) KM_SOFTIRQ1,
D(13) KM_TYPE_NR
};
#undef D
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#endif

209
libc/kernel/arch-mips/asm/lasat/lasat.h Normal file
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/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef _LASAT_H
#define _LASAT_H
#ifndef _LANGUAGE_ASSEMBLY
enum lasat_mtdparts {
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
LASAT_MTD_BOOTLOADER,
LASAT_MTD_SERVICE,
LASAT_MTD_NORMAL,
LASAT_MTD_CONFIG,
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
LASAT_MTD_FS,
LASAT_MTD_LAST
};
#include <linux/types.h>
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define LASAT_EEPROM_VERSION 7
struct lasat_eeprom_struct {
unsigned int version;
unsigned int cfg[3];
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
unsigned char hwaddr[6];
unsigned char print_partno[12];
unsigned char term0;
unsigned char print_serial[14];
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
unsigned char term1;
unsigned char prod_partno[12];
unsigned char term2;
unsigned char prod_serial[14];
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
unsigned char term3;
unsigned char passwd_hash[16];
unsigned char pwdnull;
unsigned char vendid;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
unsigned char ts_ref;
unsigned char ts_signoff;
unsigned char reserved[11];
unsigned char debugaccess;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
unsigned short prid;
unsigned int serviceflag;
unsigned int ipaddr;
unsigned int netmask;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
unsigned int crc32;
};
struct lasat_eeprom_struct_pre7 {
unsigned int version;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
unsigned int flags[3];
unsigned char hwaddr0[6];
unsigned char hwaddr1[6];
unsigned char print_partno[9];
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
unsigned char term0;
unsigned char print_serial[14];
unsigned char term1;
unsigned char prod_partno[9];
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
unsigned char term2;
unsigned char prod_serial[14];
unsigned char term3;
unsigned char passwd_hash[24];
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
unsigned char pwdnull;
unsigned char vendor;
unsigned char ts_ref;
unsigned char ts_signoff;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
unsigned char reserved[6];
unsigned int writecount;
unsigned int ipaddr;
unsigned int netmask;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
unsigned int crc32;
};
#define LASAT_W0_DSCTYPE(v) (((v)) & 0xf)
#define LASAT_W0_BMID(v) (((v) >> 0x04) & 0xf)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define LASAT_W0_CPUTYPE(v) (((v) >> 0x08) & 0xf)
#define LASAT_W0_BUSSPEED(v) (((v) >> 0x0c) & 0xf)
#define LASAT_W0_CPUCLK(v) (((v) >> 0x10) & 0xf)
#define LASAT_W0_SDRAMBANKSZ(v) (((v) >> 0x14) & 0xf)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define LASAT_W0_SDRAMBANKS(v) (((v) >> 0x18) & 0xf)
#define LASAT_W0_L2CACHE(v) (((v) >> 0x1c) & 0xf)
#define LASAT_W1_EDHAC(v) (((v)) & 0xf)
#define LASAT_W1_HIFN(v) (((v) >> 0x04) & 0x1)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define LASAT_W1_ISDN(v) (((v) >> 0x05) & 0x1)
#define LASAT_W1_IDE(v) (((v) >> 0x06) & 0x1)
#define LASAT_W1_HDLC(v) (((v) >> 0x07) & 0x1)
#define LASAT_W1_USVERSION(v) (((v) >> 0x08) & 0x1)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define LASAT_W1_4MACS(v) (((v) >> 0x09) & 0x1)
#define LASAT_W1_EXTSERIAL(v) (((v) >> 0x0a) & 0x1)
#define LASAT_W1_FLASHSIZE(v) (((v) >> 0x0c) & 0xf)
#define LASAT_W1_PCISLOTS(v) (((v) >> 0x10) & 0xf)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define LASAT_W1_PCI1OPT(v) (((v) >> 0x14) & 0xf)
#define LASAT_W1_PCI2OPT(v) (((v) >> 0x18) & 0xf)
#define LASAT_W1_PCI3OPT(v) (((v) >> 0x1c) & 0xf)
#define LASAT_BMID_MASQUERADE2 0
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define LASAT_BMID_MASQUERADEPRO 1
#define LASAT_BMID_SAFEPIPE25 2
#define LASAT_BMID_SAFEPIPE50 3
#define LASAT_BMID_SAFEPIPE100 4
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define LASAT_BMID_SAFEPIPE5000 5
#define LASAT_BMID_SAFEPIPE7000 6
#define LASAT_BMID_SAFEPIPE1000 7
#define LASAT_BMID_UNKNOWN 0xf
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define LASAT_MAX_BMID_NAMES 9
#define LASAT_HAS_EDHAC (1 << 0)
#define LASAT_EDHAC_FAST (1 << 1)
#define LASAT_HAS_EADI (1 << 2)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define LASAT_HAS_HIFN (1 << 3)
#define LASAT_HAS_ISDN (1 << 4)
#define LASAT_HAS_LEASEDLINE_IF (1 << 5)
#define LASAT_HAS_HDC (1 << 6)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define LASAT_PRID_MASQUERADE2 0
#define LASAT_PRID_MASQUERADEPRO 1
#define LASAT_PRID_SAFEPIPE25 2
#define LASAT_PRID_SAFEPIPE50 3
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define LASAT_PRID_SAFEPIPE100 4
#define LASAT_PRID_SAFEPIPE5000 5
#define LASAT_PRID_SAFEPIPE7000 6
#define LASAT_PRID_SAFEPIPE30 7
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define LASAT_PRID_SAFEPIPE5100 8
#define LASAT_PRID_SAFEPIPE7100 9
#define LASAT_PRID_SAFEPIPE1110 10
#define LASAT_PRID_SAFEPIPE3020 11
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define LASAT_PRID_SAFEPIPE3030 12
#define LASAT_PRID_SAFEPIPE5020 13
#define LASAT_PRID_SAFEPIPE5030 14
#define LASAT_PRID_SAFEPIPE1120 15
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define LASAT_PRID_SAFEPIPE1130 16
#define LASAT_PRID_SAFEPIPE6010 17
#define LASAT_PRID_SAFEPIPE6110 18
#define LASAT_PRID_SAFEPIPE6210 19
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define LASAT_PRID_SAFEPIPE1020 20
#define LASAT_PRID_SAFEPIPE1040 21
#define LASAT_PRID_SAFEPIPE1060 22
struct lasat_info {
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
unsigned int li_cpu_hz;
unsigned int li_bus_hz;
unsigned int li_bmid;
unsigned int li_memsize;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
unsigned int li_flash_size;
unsigned int li_prid;
unsigned char li_bmstr[16];
unsigned char li_namestr[32];
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
unsigned char li_typestr[16];
unsigned int li_flash_base;
unsigned long li_flashpart_base[LASAT_MTD_LAST];
unsigned long li_flashpart_size[LASAT_MTD_LAST];
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
struct lasat_eeprom_struct li_eeprom_info;
unsigned int li_eeprom_upgrade_version;
unsigned int li_debugaccess;
};
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define N_MACHTYPES 2
#include <linux/delay.h>
#define LASAT_100_DIVIDER 20
#define LASAT_200_DIVIDER 8
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IS_LASAT_200() (current_cpu_data.cputype == CPU_R5000)
#endif
#define LASAT_SERVICEMODE_MAGIC_1 0xdeadbeef
#define LASAT_SERVICEMODE_MAGIC_2 0xfedeabba
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define LASAT_GT_BASE (KSEG1ADDR(0x14000000))
#define Vrc5074_PHYS_BASE 0x1fa00000
#define Vrc5074_BASE (KSEG1ADDR(Vrc5074_PHYS_BASE))
#define PCI_WINDOW1 0x1a000000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#endif

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libc/kernel/arch-mips/asm/linkage.h Normal file
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/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef __ASM_LINKAGE_H
#define __ASM_LINKAGE_H
#ifdef __ASSEMBLY__
#include <asm/asm.h>
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#endif
#define __weak __attribute__((weak))
#endif

74
libc/kernel/arch-mips/asm/local.h Normal file
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/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef _ARCH_MIPS_LOCAL_H
#define _ARCH_MIPS_LOCAL_H
#include <linux/percpu.h>
#include <linux/bitops.h>
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#include <asm/atomic.h>
#include <asm/cmpxchg.h>
#include <asm/war.h>
typedef struct
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
{
atomic_long_t a;
} local_t;
#define LOCAL_INIT(i) { ATOMIC_LONG_INIT(i) }
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define local_read(l) atomic_long_read(&(l)->a)
#define local_set(l, i) atomic_long_set(&(l)->a, (i))
#define local_add(i, l) atomic_long_add((i), (&(l)->a))
#define local_sub(i, l) atomic_long_sub((i), (&(l)->a))
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define local_inc(l) atomic_long_inc(&(l)->a)
#define local_dec(l) atomic_long_dec(&(l)->a)
#define local_cmpxchg(l, o, n) ((long)cmpxchg_local(&((l)->a.counter), (o), (n)))
#define local_xchg(l, n) (xchg_local(&((l)->a.counter), (n)))
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define local_add_unless(l, a, u) ({ long c, old; c = local_read(l); while (c != (u) && (old = local_cmpxchg((l), c, c + (a))) != c) c = old; c != (u); })
#define local_inc_not_zero(l) local_add_unless((l), 1, 0)
#define local_dec_return(l) local_sub_return(1, (l))
#define local_inc_return(l) local_add_return(1, (l))
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define local_sub_and_test(i, l) (local_sub_return((i), (l)) == 0)
#define local_inc_and_test(l) (local_inc_return(l) == 0)
#define local_dec_and_test(l) (local_sub_return(1, (l)) == 0)
#define local_add_negative(i, l) (local_add_return(i, (l)) < 0)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define __local_inc(l) ((l)->a.counter++)
#define __local_dec(l) ((l)->a.counter++)
#define __local_add(i, l) ((l)->a.counter+=(i))
#define __local_sub(i, l) ((l)->a.counter-=(i))
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define cpu_local_wrap_v(l) ({ local_t res__; preempt_disable(); res__ = (l); preempt_enable(); res__; })
#define cpu_local_wrap(l) ({ preempt_disable(); l; preempt_enable(); })
#define cpu_local_read(l) cpu_local_wrap_v(local_read(&__get_cpu_var(l)))
#define cpu_local_set(l, i) cpu_local_wrap(local_set(&__get_cpu_var(l), (i)))
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define cpu_local_inc(l) cpu_local_wrap(local_inc(&__get_cpu_var(l)))
#define cpu_local_dec(l) cpu_local_wrap(local_dec(&__get_cpu_var(l)))
#define cpu_local_add(i, l) cpu_local_wrap(local_add((i), &__get_cpu_var(l)))
#define cpu_local_sub(i, l) cpu_local_wrap(local_sub((i), &__get_cpu_var(l)))
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define __cpu_local_inc(l) cpu_local_inc(l)
#define __cpu_local_dec(l) cpu_local_dec(l)
#define __cpu_local_add(i, l) cpu_local_add((i), (l))
#define __cpu_local_sub(i, l) cpu_local_sub((i), (l))
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#endif

898
libc/kernel/arch-mips/asm/mach-au1x00/au1000.h Normal file
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@ -0,0 +1,898 @@
/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef _AU1000_H_
#define _AU1000_H_
#ifndef _LANGUAGE_ASSEMBLY
#include <linux/delay.h>
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#include <linux/types.h>
#include <linux/io.h>
#include <linux/irq.h>
struct au1xxx_irqmap {
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
int im_irq;
int im_type;
int im_request;
};
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#endif
#define MEM_STCFG0 0xB4001000
#define MEM_STTIME0 0xB4001004
#define MEM_STADDR0 0xB4001008
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MEM_STCFG1 0xB4001010
#define MEM_STTIME1 0xB4001014
#define MEM_STADDR1 0xB4001018
#define MEM_STCFG2 0xB4001020
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MEM_STTIME2 0xB4001024
#define MEM_STADDR2 0xB4001028
#define MEM_STCFG3 0xB4001030
#define MEM_STTIME3 0xB4001034
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MEM_STADDR3 0xB4001038
#define IC0_CFG0RD 0xB0400040
#define IC0_CFG0SET 0xB0400040
#define IC0_CFG0CLR 0xB0400044
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IC0_CFG1RD 0xB0400048
#define IC0_CFG1SET 0xB0400048
#define IC0_CFG1CLR 0xB040004C
#define IC0_CFG2RD 0xB0400050
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IC0_CFG2SET 0xB0400050
#define IC0_CFG2CLR 0xB0400054
#define IC0_REQ0INT 0xB0400054
#define IC0_SRCRD 0xB0400058
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IC0_SRCSET 0xB0400058
#define IC0_SRCCLR 0xB040005C
#define IC0_REQ1INT 0xB040005C
#define IC0_ASSIGNRD 0xB0400060
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IC0_ASSIGNSET 0xB0400060
#define IC0_ASSIGNCLR 0xB0400064
#define IC0_WAKERD 0xB0400068
#define IC0_WAKESET 0xB0400068
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IC0_WAKECLR 0xB040006C
#define IC0_MASKRD 0xB0400070
#define IC0_MASKSET 0xB0400070
#define IC0_MASKCLR 0xB0400074
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IC0_RISINGRD 0xB0400078
#define IC0_RISINGCLR 0xB0400078
#define IC0_FALLINGRD 0xB040007C
#define IC0_FALLINGCLR 0xB040007C
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IC0_TESTBIT 0xB0400080
#define IC1_CFG0RD 0xB1800040
#define IC1_CFG0SET 0xB1800040
#define IC1_CFG0CLR 0xB1800044
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IC1_CFG1RD 0xB1800048
#define IC1_CFG1SET 0xB1800048
#define IC1_CFG1CLR 0xB180004C
#define IC1_CFG2RD 0xB1800050
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IC1_CFG2SET 0xB1800050
#define IC1_CFG2CLR 0xB1800054
#define IC1_REQ0INT 0xB1800054
#define IC1_SRCRD 0xB1800058
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IC1_SRCSET 0xB1800058
#define IC1_SRCCLR 0xB180005C
#define IC1_REQ1INT 0xB180005C
#define IC1_ASSIGNRD 0xB1800060
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IC1_ASSIGNSET 0xB1800060
#define IC1_ASSIGNCLR 0xB1800064
#define IC1_WAKERD 0xB1800068
#define IC1_WAKESET 0xB1800068
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IC1_WAKECLR 0xB180006C
#define IC1_MASKRD 0xB1800070
#define IC1_MASKSET 0xB1800070
#define IC1_MASKCLR 0xB1800074
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IC1_RISINGRD 0xB1800078
#define IC1_RISINGCLR 0xB1800078
#define IC1_FALLINGRD 0xB180007C
#define IC1_FALLINGCLR 0xB180007C
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IC1_TESTBIT 0xB1800080
#define INTC_INT_DISABLED 0x0
#define INTC_INT_RISE_EDGE 0x1
#define INTC_INT_FALL_EDGE 0x2
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define INTC_INT_RISE_AND_FALL_EDGE 0x3
#define INTC_INT_HIGH_LEVEL 0x5
#define INTC_INT_LOW_LEVEL 0x6
#define INTC_INT_HIGH_AND_LOW_LEVEL 0x7
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define AU1000_INTC0_INT_BASE (MIPS_CPU_IRQ_BASE + 8)
#define AU1000_INTC0_INT_LAST (AU1000_INTC0_INT_BASE + 31)
#define AU1000_INTC1_INT_BASE (AU1000_INTC0_INT_BASE + 32)
#define AU1000_INTC1_INT_LAST (AU1000_INTC1_INT_BASE + 31)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define AU1000_MAX_INTR AU1000_INTC1_INT_LAST
#define INTX 0xFF
#define SYS_BASE 0xB1900000
#define SYS_COUNTER_CNTRL (SYS_BASE + 0x14)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SYS_CNTRL_E1S (1 << 23)
#define SYS_CNTRL_T1S (1 << 20)
#define SYS_CNTRL_M21 (1 << 19)
#define SYS_CNTRL_M11 (1 << 18)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SYS_CNTRL_M01 (1 << 17)
#define SYS_CNTRL_C1S (1 << 16)
#define SYS_CNTRL_BP (1 << 14)
#define SYS_CNTRL_EN1 (1 << 13)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SYS_CNTRL_BT1 (1 << 12)
#define SYS_CNTRL_EN0 (1 << 11)
#define SYS_CNTRL_BT0 (1 << 10)
#define SYS_CNTRL_E0 (1 << 8)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SYS_CNTRL_E0S (1 << 7)
#define SYS_CNTRL_32S (1 << 5)
#define SYS_CNTRL_T0S (1 << 4)
#define SYS_CNTRL_M20 (1 << 3)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SYS_CNTRL_M10 (1 << 2)
#define SYS_CNTRL_M00 (1 << 1)
#define SYS_CNTRL_C0S (1 << 0)
#define SYS_TOYTRIM (SYS_BASE + 0)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SYS_TOYWRITE (SYS_BASE + 4)
#define SYS_TOYMATCH0 (SYS_BASE + 8)
#define SYS_TOYMATCH1 (SYS_BASE + 0xC)
#define SYS_TOYMATCH2 (SYS_BASE + 0x10)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SYS_TOYREAD (SYS_BASE + 0x40)
#define SYS_RTCTRIM (SYS_BASE + 0x44)
#define SYS_RTCWRITE (SYS_BASE + 0x48)
#define SYS_RTCMATCH0 (SYS_BASE + 0x4C)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SYS_RTCMATCH1 (SYS_BASE + 0x50)
#define SYS_RTCMATCH2 (SYS_BASE + 0x54)
#define SYS_RTCREAD (SYS_BASE + 0x58)
#define I2S_DATA 0xB1000000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define I2S_DATA_MASK 0xffffff
#define I2S_CONFIG 0xB1000004
#define I2S_CONFIG_XU (1 << 25)
#define I2S_CONFIG_XO (1 << 24)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define I2S_CONFIG_RU (1 << 23)
#define I2S_CONFIG_RO (1 << 22)
#define I2S_CONFIG_TR (1 << 21)
#define I2S_CONFIG_TE (1 << 20)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define I2S_CONFIG_TF (1 << 19)
#define I2S_CONFIG_RR (1 << 18)
#define I2S_CONFIG_RE (1 << 17)
#define I2S_CONFIG_RF (1 << 16)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define I2S_CONFIG_PD (1 << 11)
#define I2S_CONFIG_LB (1 << 10)
#define I2S_CONFIG_IC (1 << 9)
#define I2S_CONFIG_FM_BIT 7
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define I2S_CONFIG_FM_MASK (0x3 << I2S_CONFIG_FM_BIT)
#define I2S_CONFIG_FM_I2S (0x0 << I2S_CONFIG_FM_BIT)
#define I2S_CONFIG_FM_LJ (0x1 << I2S_CONFIG_FM_BIT)
#define I2S_CONFIG_FM_RJ (0x2 << I2S_CONFIG_FM_BIT)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define I2S_CONFIG_TN (1 << 6)
#define I2S_CONFIG_RN (1 << 5)
#define I2S_CONFIG_SZ_BIT 0
#define I2S_CONFIG_SZ_MASK (0x1F << I2S_CONFIG_SZ_BIT)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define I2S_CONTROL 0xB1000008
#define I2S_CONTROL_D (1 << 1)
#define I2S_CONTROL_CE (1 << 0)
#ifndef USB_OHCI_LEN
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define USB_OHCI_LEN 0x00100000
#endif
#define USBD_EP0RD 0xB0200000
#define USBD_EP0WR 0xB0200004
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define USBD_EP2WR 0xB0200008
#define USBD_EP3WR 0xB020000C
#define USBD_EP4RD 0xB0200010
#define USBD_EP5RD 0xB0200014
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define USBD_INTEN 0xB0200018
#define USBD_INTSTAT 0xB020001C
#define USBDEV_INT_SOF (1 << 12)
#define USBDEV_INT_HF_BIT 6
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define USBDEV_INT_HF_MASK (0x3f << USBDEV_INT_HF_BIT)
#define USBDEV_INT_CMPLT_BIT 0
#define USBDEV_INT_CMPLT_MASK (0x3f << USBDEV_INT_CMPLT_BIT)
#define USBD_CONFIG 0xB0200020
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define USBD_EP0CS 0xB0200024
#define USBD_EP2CS 0xB0200028
#define USBD_EP3CS 0xB020002C
#define USBD_EP4CS 0xB0200030
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define USBD_EP5CS 0xB0200034
#define USBDEV_CS_SU (1 << 14)
#define USBDEV_CS_NAK (1 << 13)
#define USBDEV_CS_ACK (1 << 12)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define USBDEV_CS_BUSY (1 << 11)
#define USBDEV_CS_TSIZE_BIT 1
#define USBDEV_CS_TSIZE_MASK (0x3ff << USBDEV_CS_TSIZE_BIT)
#define USBDEV_CS_STALL (1 << 0)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define USBD_EP0RDSTAT 0xB0200040
#define USBD_EP0WRSTAT 0xB0200044
#define USBD_EP2WRSTAT 0xB0200048
#define USBD_EP3WRSTAT 0xB020004C
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define USBD_EP4RDSTAT 0xB0200050
#define USBD_EP5RDSTAT 0xB0200054
#define USBDEV_FSTAT_FLUSH (1 << 6)
#define USBDEV_FSTAT_UF (1 << 5)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define USBDEV_FSTAT_OF (1 << 4)
#define USBDEV_FSTAT_FCNT_BIT 0
#define USBDEV_FSTAT_FCNT_MASK (0x0f << USBDEV_FSTAT_FCNT_BIT)
#define USBD_ENABLE 0xB0200058
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define USBDEV_ENABLE (1 << 1)
#define USBDEV_CE (1 << 0)
#define MAC_CONTROL 0x0
#define MAC_RX_ENABLE (1 << 2)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MAC_TX_ENABLE (1 << 3)
#define MAC_DEF_CHECK (1 << 5)
#define MAC_SET_BL(X) (((X) & 0x3) << 6)
#define MAC_AUTO_PAD (1 << 8)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MAC_DISABLE_RETRY (1 << 10)
#define MAC_DISABLE_BCAST (1 << 11)
#define MAC_LATE_COL (1 << 12)
#define MAC_HASH_MODE (1 << 13)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MAC_HASH_ONLY (1 << 15)
#define MAC_PASS_ALL (1 << 16)
#define MAC_INVERSE_FILTER (1 << 17)
#define MAC_PROMISCUOUS (1 << 18)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MAC_PASS_ALL_MULTI (1 << 19)
#define MAC_FULL_DUPLEX (1 << 20)
#define MAC_NORMAL_MODE 0
#define MAC_INT_LOOPBACK (1 << 21)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MAC_EXT_LOOPBACK (1 << 22)
#define MAC_DISABLE_RX_OWN (1 << 23)
#define MAC_BIG_ENDIAN (1 << 30)
#define MAC_RX_ALL (1 << 31)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MAC_ADDRESS_HIGH 0x4
#define MAC_ADDRESS_LOW 0x8
#define MAC_MCAST_HIGH 0xC
#define MAC_MCAST_LOW 0x10
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MAC_MII_CNTRL 0x14
#define MAC_MII_BUSY (1 << 0)
#define MAC_MII_READ 0
#define MAC_MII_WRITE (1 << 1)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MAC_SET_MII_SELECT_REG(X) (((X) & 0x1f) << 6)
#define MAC_SET_MII_SELECT_PHY(X) (((X) & 0x1f) << 11)
#define MAC_MII_DATA 0x18
#define MAC_FLOW_CNTRL 0x1C
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MAC_FLOW_CNTRL_BUSY (1 << 0)
#define MAC_FLOW_CNTRL_ENABLE (1 << 1)
#define MAC_PASS_CONTROL (1 << 2)
#define MAC_SET_PAUSE(X) (((X) & 0xffff) << 16)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MAC_VLAN1_TAG 0x20
#define MAC_VLAN2_TAG 0x24
#define MAC_EN_CLOCK_ENABLE (1 << 0)
#define MAC_EN_RESET0 (1 << 1)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MAC_EN_TOSS (0 << 2)
#define MAC_EN_CACHEABLE (1 << 3)
#define MAC_EN_RESET1 (1 << 4)
#define MAC_EN_RESET2 (1 << 5)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MAC_DMA_RESET (1 << 6)
#define MAC0_TX_DMA_ADDR 0xB4004000
#define MAC1_TX_DMA_ADDR 0xB4004200
#define MAC_TX_BUFF0_STATUS 0x0
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define TX_FRAME_ABORTED (1 << 0)
#define TX_JAB_TIMEOUT (1 << 1)
#define TX_NO_CARRIER (1 << 2)
#define TX_LOSS_CARRIER (1 << 3)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define TX_EXC_DEF (1 << 4)
#define TX_LATE_COLL_ABORT (1 << 5)
#define TX_EXC_COLL (1 << 6)
#define TX_UNDERRUN (1 << 7)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define TX_DEFERRED (1 << 8)
#define TX_LATE_COLL (1 << 9)
#define TX_COLL_CNT_MASK (0xF << 10)
#define TX_PKT_RETRY (1 << 31)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MAC_TX_BUFF0_ADDR 0x4
#define TX_DMA_ENABLE (1 << 0)
#define TX_T_DONE (1 << 1)
#define TX_GET_DMA_BUFFER(X) (((X) >> 2) & 0x3)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MAC_TX_BUFF0_LEN 0x8
#define MAC_TX_BUFF1_STATUS 0x10
#define MAC_TX_BUFF1_ADDR 0x14
#define MAC_TX_BUFF1_LEN 0x18
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MAC_TX_BUFF2_STATUS 0x20
#define MAC_TX_BUFF2_ADDR 0x24
#define MAC_TX_BUFF2_LEN 0x28
#define MAC_TX_BUFF3_STATUS 0x30
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MAC_TX_BUFF3_ADDR 0x34
#define MAC_TX_BUFF3_LEN 0x38
#define MAC0_RX_DMA_ADDR 0xB4004100
#define MAC1_RX_DMA_ADDR 0xB4004300
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MAC_RX_BUFF0_STATUS 0x0
#define RX_FRAME_LEN_MASK 0x3fff
#define RX_WDOG_TIMER (1 << 14)
#define RX_RUNT (1 << 15)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define RX_OVERLEN (1 << 16)
#define RX_COLL (1 << 17)
#define RX_ETHER (1 << 18)
#define RX_MII_ERROR (1 << 19)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define RX_DRIBBLING (1 << 20)
#define RX_CRC_ERROR (1 << 21)
#define RX_VLAN1 (1 << 22)
#define RX_VLAN2 (1 << 23)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define RX_LEN_ERROR (1 << 24)
#define RX_CNTRL_FRAME (1 << 25)
#define RX_U_CNTRL_FRAME (1 << 26)
#define RX_MCAST_FRAME (1 << 27)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define RX_BCAST_FRAME (1 << 28)
#define RX_FILTER_FAIL (1 << 29)
#define RX_PACKET_FILTER (1 << 30)
#define RX_MISSED_FRAME (1 << 31)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define RX_ERROR (RX_WDOG_TIMER | RX_RUNT | RX_OVERLEN | RX_COLL | RX_MII_ERROR | RX_CRC_ERROR | RX_LEN_ERROR | RX_U_CNTRL_FRAME | RX_MISSED_FRAME)
#define MAC_RX_BUFF0_ADDR 0x4
#define RX_DMA_ENABLE (1 << 0)
#define RX_T_DONE (1 << 1)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define RX_GET_DMA_BUFFER(X) (((X) >> 2) & 0x3)
#define RX_SET_BUFF_ADDR(X) ((X) & 0xffffffc0)
#define MAC_RX_BUFF1_STATUS 0x10
#define MAC_RX_BUFF1_ADDR 0x14
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MAC_RX_BUFF2_STATUS 0x20
#define MAC_RX_BUFF2_ADDR 0x24
#define MAC_RX_BUFF3_STATUS 0x30
#define MAC_RX_BUFF3_ADDR 0x34
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define UART_BASE UART0_ADDR
#define UART_DEBUG_BASE UART3_ADDR
#define UART_RX 0
#define UART_TX 4
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define UART_IER 8
#define UART_IIR 0xC
#define UART_FCR 0x10
#define UART_LCR 0x14
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define UART_MCR 0x18
#define UART_LSR 0x1C
#define UART_MSR 0x20
#define UART_CLK 0x28
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define UART_MOD_CNTRL 0x100
#define UART_FCR_ENABLE_FIFO 0x01
#define UART_FCR_CLEAR_RCVR 0x02
#define UART_FCR_CLEAR_XMIT 0x04
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define UART_FCR_DMA_SELECT 0x08
#define UART_FCR_TRIGGER_MASK 0xF0
#define UART_FCR_R_TRIGGER_1 0x00
#define UART_FCR_R_TRIGGER_4 0x40
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define UART_FCR_R_TRIGGER_8 0x80
#define UART_FCR_R_TRIGGER_14 0xA0
#define UART_FCR_T_TRIGGER_0 0x00
#define UART_FCR_T_TRIGGER_4 0x10
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define UART_FCR_T_TRIGGER_8 0x20
#define UART_FCR_T_TRIGGER_12 0x30
#define UART_LCR_SBC 0x40
#define UART_LCR_SPAR 0x20
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define UART_LCR_EPAR 0x10
#define UART_LCR_PARITY 0x08
#define UART_LCR_STOP 0x04
#define UART_LCR_WLEN5 0x00
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define UART_LCR_WLEN6 0x01
#define UART_LCR_WLEN7 0x02
#define UART_LCR_WLEN8 0x03
#define UART_LSR_TEMT 0x40
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define UART_LSR_THRE 0x20
#define UART_LSR_BI 0x10
#define UART_LSR_FE 0x08
#define UART_LSR_PE 0x04
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define UART_LSR_OE 0x02
#define UART_LSR_DR 0x01
#define UART_IIR_NO_INT 0x01
#define UART_IIR_ID 0x06
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define UART_IIR_MSI 0x00
#define UART_IIR_THRI 0x02
#define UART_IIR_RDI 0x04
#define UART_IIR_RLSI 0x06
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define UART_IER_MSI 0x08
#define UART_IER_RLSI 0x04
#define UART_IER_THRI 0x02
#define UART_IER_RDI 0x01
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define UART_MCR_LOOP 0x10
#define UART_MCR_OUT2 0x08
#define UART_MCR_OUT1 0x04
#define UART_MCR_RTS 0x02
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define UART_MCR_DTR 0x01
#define UART_MSR_DCD 0x80
#define UART_MSR_RI 0x40
#define UART_MSR_DSR 0x20
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define UART_MSR_CTS 0x10
#define UART_MSR_DDCD 0x08
#define UART_MSR_TERI 0x04
#define UART_MSR_DDSR 0x02
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define UART_MSR_DCTS 0x01
#define UART_MSR_ANY_DELTA 0x0F
#define SSI0_STATUS 0xB1600000
#define SSI_STATUS_BF (1 << 4)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SSI_STATUS_OF (1 << 3)
#define SSI_STATUS_UF (1 << 2)
#define SSI_STATUS_D (1 << 1)
#define SSI_STATUS_B (1 << 0)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SSI0_INT 0xB1600004
#define SSI_INT_OI (1 << 3)
#define SSI_INT_UI (1 << 2)
#define SSI_INT_DI (1 << 1)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SSI0_INT_ENABLE 0xB1600008
#define SSI_INTE_OIE (1 << 3)
#define SSI_INTE_UIE (1 << 2)
#define SSI_INTE_DIE (1 << 1)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SSI0_CONFIG 0xB1600020
#define SSI_CONFIG_AO (1 << 24)
#define SSI_CONFIG_DO (1 << 23)
#define SSI_CONFIG_ALEN_BIT 20
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SSI_CONFIG_ALEN_MASK (0x7 << 20)
#define SSI_CONFIG_DLEN_BIT 16
#define SSI_CONFIG_DLEN_MASK (0x7 << 16)
#define SSI_CONFIG_DD (1 << 11)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SSI_CONFIG_AD (1 << 10)
#define SSI_CONFIG_BM_BIT 8
#define SSI_CONFIG_BM_MASK (0x3 << 8)
#define SSI_CONFIG_CE (1 << 7)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SSI_CONFIG_DP (1 << 6)
#define SSI_CONFIG_DL (1 << 5)
#define SSI_CONFIG_EP (1 << 4)
#define SSI0_ADATA 0xB1600024
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SSI_AD_D (1 << 24)
#define SSI_AD_ADDR_BIT 16
#define SSI_AD_ADDR_MASK (0xff << 16)
#define SSI_AD_DATA_BIT 0
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SSI_AD_DATA_MASK (0xfff << 0)
#define SSI0_CLKDIV 0xB1600028
#define SSI0_CONTROL 0xB1600100
#define SSI_CONTROL_CD (1 << 1)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SSI_CONTROL_E (1 << 0)
#define SSI1_STATUS 0xB1680000
#define SSI1_INT 0xB1680004
#define SSI1_INT_ENABLE 0xB1680008
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SSI1_CONFIG 0xB1680020
#define SSI1_ADATA 0xB1680024
#define SSI1_CLKDIV 0xB1680028
#define SSI1_ENABLE 0xB1680100
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SSI_STATUS_BF (1 << 4)
#define SSI_STATUS_OF (1 << 3)
#define SSI_STATUS_UF (1 << 2)
#define SSI_STATUS_D (1 << 1)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SSI_STATUS_B (1 << 0)
#define SSI_INT_OI (1 << 3)
#define SSI_INT_UI (1 << 2)
#define SSI_INT_DI (1 << 1)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SSI_INTEN_OIE (1 << 3)
#define SSI_INTEN_UIE (1 << 2)
#define SSI_INTEN_DIE (1 << 1)
#define SSI_CONFIG_AO (1 << 24)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SSI_CONFIG_DO (1 << 23)
#define SSI_CONFIG_ALEN (7 << 20)
#define SSI_CONFIG_DLEN (15 << 16)
#define SSI_CONFIG_DD (1 << 11)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SSI_CONFIG_AD (1 << 10)
#define SSI_CONFIG_BM (3 << 8)
#define SSI_CONFIG_CE (1 << 7)
#define SSI_CONFIG_DP (1 << 6)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SSI_CONFIG_DL (1 << 5)
#define SSI_CONFIG_EP (1 << 4)
#define SSI_CONFIG_ALEN_N(N) ((N-1) << 20)
#define SSI_CONFIG_DLEN_N(N) ((N-1) << 16)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SSI_CONFIG_BM_HI (0 << 8)
#define SSI_CONFIG_BM_LO (1 << 8)
#define SSI_CONFIG_BM_CY (2 << 8)
#define SSI_ADATA_D (1 << 24)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SSI_ADATA_ADDR (0xFF << 16)
#define SSI_ADATA_DATA 0x0FFF
#define SSI_ADATA_ADDR_N(N) (N << 16)
#define SSI_ENABLE_CD (1 << 1)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SSI_ENABLE_E (1 << 0)
#define IRDA_BASE 0xB0300000
#define IR_RING_PTR_STATUS (IRDA_BASE + 0x00)
#define IR_RING_BASE_ADDR_H (IRDA_BASE + 0x04)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IR_RING_BASE_ADDR_L (IRDA_BASE + 0x08)
#define IR_RING_SIZE (IRDA_BASE + 0x0C)
#define IR_RING_PROMPT (IRDA_BASE + 0x10)
#define IR_RING_ADDR_CMPR (IRDA_BASE + 0x14)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IR_INT_CLEAR (IRDA_BASE + 0x18)
#define IR_CONFIG_1 (IRDA_BASE + 0x20)
#define IR_RX_INVERT_LED (1 << 0)
#define IR_TX_INVERT_LED (1 << 1)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IR_ST (1 << 2)
#define IR_SF (1 << 3)
#define IR_SIR (1 << 4)
#define IR_MIR (1 << 5)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IR_FIR (1 << 6)
#define IR_16CRC (1 << 7)
#define IR_TD (1 << 8)
#define IR_RX_ALL (1 << 9)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IR_DMA_ENABLE (1 << 10)
#define IR_RX_ENABLE (1 << 11)
#define IR_TX_ENABLE (1 << 12)
#define IR_LOOPBACK (1 << 14)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IR_SIR_MODE (IR_SIR | IR_DMA_ENABLE | IR_RX_ALL | IR_RX_ENABLE | IR_SF | IR_16CRC)
#define IR_SIR_FLAGS (IRDA_BASE + 0x24)
#define IR_ENABLE (IRDA_BASE + 0x28)
#define IR_RX_STATUS (1 << 9)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IR_TX_STATUS (1 << 10)
#define IR_READ_PHY_CONFIG (IRDA_BASE + 0x2C)
#define IR_WRITE_PHY_CONFIG (IRDA_BASE + 0x30)
#define IR_MAX_PKT_LEN (IRDA_BASE + 0x34)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IR_RX_BYTE_CNT (IRDA_BASE + 0x38)
#define IR_CONFIG_2 (IRDA_BASE + 0x3C)
#define IR_MODE_INV (1 << 0)
#define IR_ONE_PIN (1 << 1)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IR_INTERFACE_CONFIG (IRDA_BASE + 0x40)
#define SYS_PINFUNC 0xB190002C
#define SYS_PF_USB (1 << 15)
#define SYS_PF_U3 (1 << 14)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SYS_PF_U2 (1 << 13)
#define SYS_PF_U1 (1 << 12)
#define SYS_PF_SRC (1 << 11)
#define SYS_PF_CK5 (1 << 10)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SYS_PF_CK4 (1 << 9)
#define SYS_PF_IRF (1 << 8)
#define SYS_PF_UR3 (1 << 7)
#define SYS_PF_I2D (1 << 6)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SYS_PF_I2S (1 << 5)
#define SYS_PF_NI2 (1 << 4)
#define SYS_PF_U0 (1 << 3)
#define SYS_PF_RD (1 << 2)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SYS_PF_A97 (1 << 1)
#define SYS_PF_S0 (1 << 0)
#define SYS_PF_PC (1 << 18)
#define SYS_PF_LCD (1 << 17)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SYS_PF_CS (1 << 16)
#define SYS_PF_EX0 (1 << 9)
#define SYS_PF_PSC2_MASK (7 << 17)
#define SYS_PF_PSC2_AC97 0
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SYS_PF_PSC2_SPI 0
#define SYS_PF_PSC2_I2S (1 << 17)
#define SYS_PF_PSC2_SMBUS (3 << 17)
#define SYS_PF_PSC2_GPIO (7 << 17)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SYS_PF_PSC3_MASK (7 << 20)
#define SYS_PF_PSC3_AC97 0
#define SYS_PF_PSC3_SPI 0
#define SYS_PF_PSC3_I2S (1 << 20)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SYS_PF_PSC3_SMBUS (3 << 20)
#define SYS_PF_PSC3_GPIO (7 << 20)
#define SYS_PF_PSC1_S1 (1 << 1)
#define SYS_PF_MUST_BE_SET ((1 << 5) | (1 << 2))
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SYS_TRIOUTRD 0xB1900100
#define SYS_TRIOUTCLR 0xB1900100
#define SYS_OUTPUTRD 0xB1900108
#define SYS_OUTPUTSET 0xB1900108
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SYS_OUTPUTCLR 0xB190010C
#define SYS_PINSTATERD 0xB1900110
#define SYS_PININPUTEN 0xB1900110
#define GPIO2_BASE 0xB1700000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define GPIO2_DIR (GPIO2_BASE + 0)
#define GPIO2_OUTPUT (GPIO2_BASE + 8)
#define GPIO2_PINSTATE (GPIO2_BASE + 0xC)
#define GPIO2_INTENABLE (GPIO2_BASE + 0x10)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define GPIO2_ENABLE (GPIO2_BASE + 0x14)
#define SYS_SCRATCH0 0xB1900018
#define SYS_SCRATCH1 0xB190001C
#define SYS_WAKEMSK 0xB1900034
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SYS_ENDIAN 0xB1900038
#define SYS_POWERCTRL 0xB190003C
#define SYS_WAKESRC 0xB190005C
#define SYS_SLPPWR 0xB1900078
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SYS_SLEEP 0xB190007C
#define SYS_FREQCTRL0 0xB1900020
#define SYS_FC_FRDIV2_BIT 22
#define SYS_FC_FRDIV2_MASK (0xff << SYS_FC_FRDIV2_BIT)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SYS_FC_FE2 (1 << 21)
#define SYS_FC_FS2 (1 << 20)
#define SYS_FC_FRDIV1_BIT 12
#define SYS_FC_FRDIV1_MASK (0xff << SYS_FC_FRDIV1_BIT)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SYS_FC_FE1 (1 << 11)
#define SYS_FC_FS1 (1 << 10)
#define SYS_FC_FRDIV0_BIT 2
#define SYS_FC_FRDIV0_MASK (0xff << SYS_FC_FRDIV0_BIT)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SYS_FC_FE0 (1 << 1)
#define SYS_FC_FS0 (1 << 0)
#define SYS_FREQCTRL1 0xB1900024
#define SYS_FC_FRDIV5_BIT 22
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SYS_FC_FRDIV5_MASK (0xff << SYS_FC_FRDIV5_BIT)
#define SYS_FC_FE5 (1 << 21)
#define SYS_FC_FS5 (1 << 20)
#define SYS_FC_FRDIV4_BIT 12
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SYS_FC_FRDIV4_MASK (0xff << SYS_FC_FRDIV4_BIT)
#define SYS_FC_FE4 (1 << 11)
#define SYS_FC_FS4 (1 << 10)
#define SYS_FC_FRDIV3_BIT 2
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SYS_FC_FRDIV3_MASK (0xff << SYS_FC_FRDIV3_BIT)
#define SYS_FC_FE3 (1 << 1)
#define SYS_FC_FS3 (1 << 0)
#define SYS_CLKSRC 0xB1900028
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SYS_CS_ME1_BIT 27
#define SYS_CS_ME1_MASK (0x7 << SYS_CS_ME1_BIT)
#define SYS_CS_DE1 (1 << 26)
#define SYS_CS_CE1 (1 << 25)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SYS_CS_ME0_BIT 22
#define SYS_CS_ME0_MASK (0x7 << SYS_CS_ME0_BIT)
#define SYS_CS_DE0 (1 << 21)
#define SYS_CS_CE0 (1 << 20)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SYS_CS_MI2_BIT 17
#define SYS_CS_MI2_MASK (0x7 << SYS_CS_MI2_BIT)
#define SYS_CS_DI2 (1 << 16)
#define SYS_CS_CI2 (1 << 15)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SYS_CS_MUH_BIT 12
#define SYS_CS_MUH_MASK (0x7 << SYS_CS_MUH_BIT)
#define SYS_CS_DUH (1 << 11)
#define SYS_CS_CUH (1 << 10)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SYS_CS_MUD_BIT 7
#define SYS_CS_MUD_MASK (0x7 << SYS_CS_MUD_BIT)
#define SYS_CS_DUD (1 << 6)
#define SYS_CS_CUD (1 << 5)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SYS_CS_MIR_BIT 2
#define SYS_CS_MIR_MASK (0x7 << SYS_CS_MIR_BIT)
#define SYS_CS_DIR (1 << 1)
#define SYS_CS_CIR (1 << 0)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SYS_CS_MUX_AUX 0x1
#define SYS_CS_MUX_FQ0 0x2
#define SYS_CS_MUX_FQ1 0x3
#define SYS_CS_MUX_FQ2 0x4
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SYS_CS_MUX_FQ3 0x5
#define SYS_CS_MUX_FQ4 0x6
#define SYS_CS_MUX_FQ5 0x7
#define SYS_CPUPLL 0xB1900060
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SYS_AUXPLL 0xB1900064
#define AC97C_CONFIG 0xB0000000
#define AC97C_RECV_SLOTS_BIT 13
#define AC97C_RECV_SLOTS_MASK (0x3ff << AC97C_RECV_SLOTS_BIT)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define AC97C_XMIT_SLOTS_BIT 3
#define AC97C_XMIT_SLOTS_MASK (0x3ff << AC97C_XMIT_SLOTS_BIT)
#define AC97C_SG (1 << 2)
#define AC97C_SYNC (1 << 1)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define AC97C_RESET (1 << 0)
#define AC97C_STATUS 0xB0000004
#define AC97C_XU (1 << 11)
#define AC97C_XO (1 << 10)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define AC97C_RU (1 << 9)
#define AC97C_RO (1 << 8)
#define AC97C_READY (1 << 7)
#define AC97C_CP (1 << 6)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define AC97C_TR (1 << 5)
#define AC97C_TE (1 << 4)
#define AC97C_TF (1 << 3)
#define AC97C_RR (1 << 2)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define AC97C_RE (1 << 1)
#define AC97C_RF (1 << 0)
#define AC97C_DATA 0xB0000008
#define AC97C_CMD 0xB000000C
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define AC97C_WD_BIT 16
#define AC97C_READ (1 << 7)
#define AC97C_INDEX_MASK 0x7f
#define AC97C_CNTRL 0xB0000010
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define AC97C_RS (1 << 1)
#define AC97C_CE (1 << 0)
#define SD0_XMIT_FIFO 0xB0600000
#define SD0_RECV_FIFO 0xB0600004
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SD1_XMIT_FIFO 0xB0680000
#define SD1_RECV_FIFO 0xB0680004
#define IOPORT_RESOURCE_START 0x10000000
#define IOPORT_RESOURCE_END 0xffffffff
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IOMEM_RESOURCE_START 0x10000000
#define IOMEM_RESOURCE_END 0xffffffff
#define PCI_IO_START 0
#define PCI_IO_END 0
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PCI_MEM_START 0
#define PCI_MEM_END 0
#define PCI_FIRST_DEVFN 0
#define PCI_LAST_DEVFN 0
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#ifndef _LANGUAGE_ASSEMBLY
typedef volatile struct {
u32 toytrim;
u32 toywrite;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
u32 toymatch0;
u32 toymatch1;
u32 toymatch2;
u32 cntrctrl;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
u32 scratch0;
u32 scratch1;
u32 freqctrl0;
u32 freqctrl1;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
u32 clksrc;
u32 pinfunc;
u32 reserved0;
u32 wakemsk;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
u32 endian;
u32 powerctrl;
u32 toyread;
u32 rtctrim;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
u32 rtcwrite;
u32 rtcmatch0;
u32 rtcmatch1;
u32 rtcmatch2;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
u32 rtcread;
u32 wakesrc;
u32 cpupll;
u32 auxpll;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
u32 reserved1;
u32 reserved2;
u32 reserved3;
u32 reserved4;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
u32 slppwr;
u32 sleep;
u32 reserved5[32];
u32 trioutrd;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define trioutclr trioutrd
u32 reserved6;
u32 outputrd;
#define outputset outputrd
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
u32 outputclr;
u32 pinstaterd;
#define pininputen pinstaterd
} AU1X00_SYS;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#endif
#ifndef _LANGUAGE_ASSEMBLY
struct cpu_spec {
unsigned int prid_mask;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
unsigned int prid_value;
char *cpu_name;
unsigned char cpu_od;
unsigned char cpu_bclk;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
unsigned char cpu_pll_wo;
};
#endif
#endif
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */

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libc/kernel/arch-mips/asm/mach-au1x00/au1xxx_psc.h Normal file
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/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef _AU1000_PSC_H_
#define _AU1000_PSC_H_
#define PSC_SEL_OFFSET 0x00000000
#define PSC_CTRL_OFFSET 0x00000004
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PSC_SEL_CLK_MASK (3 << 4)
#define PSC_SEL_CLK_INTCLK (0 << 4)
#define PSC_SEL_CLK_EXTCLK (1 << 4)
#define PSC_SEL_CLK_SERCLK (2 << 4)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PSC_SEL_PS_MASK 0x00000007
#define PSC_SEL_PS_DISABLED 0
#define PSC_SEL_PS_SPIMODE 2
#define PSC_SEL_PS_I2SMODE 3
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PSC_SEL_PS_AC97MODE 4
#define PSC_SEL_PS_SMBUSMODE 5
#define PSC_CTRL_DISABLE 0
#define PSC_CTRL_SUSPEND 2
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PSC_CTRL_ENABLE 3
#define PSC_AC97CFG_OFFSET 0x00000008
#define PSC_AC97MSK_OFFSET 0x0000000c
#define PSC_AC97PCR_OFFSET 0x00000010
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PSC_AC97STAT_OFFSET 0x00000014
#define PSC_AC97EVNT_OFFSET 0x00000018
#define PSC_AC97TXRX_OFFSET 0x0000001c
#define PSC_AC97CDC_OFFSET 0x00000020
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PSC_AC97RST_OFFSET 0x00000024
#define PSC_AC97GPO_OFFSET 0x00000028
#define PSC_AC97GPI_OFFSET 0x0000002c
#define AC97_PSC_SEL (AC97_PSC_BASE + PSC_SEL_OFFSET)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define AC97_PSC_CTRL (AC97_PSC_BASE + PSC_CTRL_OFFSET)
#define PSC_AC97CFG (AC97_PSC_BASE + PSC_AC97CFG_OFFSET)
#define PSC_AC97MSK (AC97_PSC_BASE + PSC_AC97MSK_OFFSET)
#define PSC_AC97PCR (AC97_PSC_BASE + PSC_AC97PCR_OFFSET)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PSC_AC97STAT (AC97_PSC_BASE + PSC_AC97STAT_OFFSET)
#define PSC_AC97EVNT (AC97_PSC_BASE + PSC_AC97EVNT_OFFSET)
#define PSC_AC97TXRX (AC97_PSC_BASE + PSC_AC97TXRX_OFFSET)
#define PSC_AC97CDC (AC97_PSC_BASE + PSC_AC97CDC_OFFSET)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PSC_AC97RST (AC97_PSC_BASE + PSC_AC97RST_OFFSET)
#define PSC_AC97GPO (AC97_PSC_BASE + PSC_AC97GPO_OFFSET)
#define PSC_AC97GPI (AC97_PSC_BASE + PSC_AC97GPI_OFFSET)
#define PSC_AC97CFG_RT_MASK (3 << 30)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PSC_AC97CFG_RT_FIFO1 (0 << 30)
#define PSC_AC97CFG_RT_FIFO2 (1 << 30)
#define PSC_AC97CFG_RT_FIFO4 (2 << 30)
#define PSC_AC97CFG_RT_FIFO8 (3 << 30)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PSC_AC97CFG_TT_MASK (3 << 28)
#define PSC_AC97CFG_TT_FIFO1 (0 << 28)
#define PSC_AC97CFG_TT_FIFO2 (1 << 28)
#define PSC_AC97CFG_TT_FIFO4 (2 << 28)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PSC_AC97CFG_TT_FIFO8 (3 << 28)
#define PSC_AC97CFG_DD_DISABLE (1 << 27)
#define PSC_AC97CFG_DE_ENABLE (1 << 26)
#define PSC_AC97CFG_SE_ENABLE (1 << 25)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PSC_AC97CFG_LEN_MASK (0xf << 21)
#define PSC_AC97CFG_TXSLOT_MASK (0x3ff << 11)
#define PSC_AC97CFG_RXSLOT_MASK (0x3ff << 1)
#define PSC_AC97CFG_GE_ENABLE (1)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PSC_AC97CFG_TXSLOT_ENA(x) (1 << (((x) - 3) + 11))
#define PSC_AC97CFG_RXSLOT_ENA(x) (1 << (((x) - 3) + 1))
#define PSC_AC97CFG_SET_LEN(x) (((((x) - 2) / 2) & 0xf) << 21)
#define PSC_AC97CFG_GET_LEN(x) (((((x) >> 21) & 0xf) * 2) + 2)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PSC_AC97MSK_GR (1 << 25)
#define PSC_AC97MSK_CD (1 << 24)
#define PSC_AC97MSK_RR (1 << 13)
#define PSC_AC97MSK_RO (1 << 12)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PSC_AC97MSK_RU (1 << 11)
#define PSC_AC97MSK_TR (1 << 10)
#define PSC_AC97MSK_TO (1 << 9)
#define PSC_AC97MSK_TU (1 << 8)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PSC_AC97MSK_RD (1 << 5)
#define PSC_AC97MSK_TD (1 << 4)
#define PSC_AC97MSK_ALLMASK (PSC_AC97MSK_GR | PSC_AC97MSK_CD | PSC_AC97MSK_RR | PSC_AC97MSK_RO | PSC_AC97MSK_RU | PSC_AC97MSK_TR | PSC_AC97MSK_TO | PSC_AC97MSK_TU | PSC_AC97MSK_RD | PSC_AC97MSK_TD)
#define PSC_AC97PCR_RC (1 << 6)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PSC_AC97PCR_RP (1 << 5)
#define PSC_AC97PCR_RS (1 << 4)
#define PSC_AC97PCR_TC (1 << 2)
#define PSC_AC97PCR_TP (1 << 1)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PSC_AC97PCR_TS (1 << 0)
#define PSC_AC97STAT_CB (1 << 26)
#define PSC_AC97STAT_CP (1 << 25)
#define PSC_AC97STAT_CR (1 << 24)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PSC_AC97STAT_RF (1 << 13)
#define PSC_AC97STAT_RE (1 << 12)
#define PSC_AC97STAT_RR (1 << 11)
#define PSC_AC97STAT_TF (1 << 10)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PSC_AC97STAT_TE (1 << 9)
#define PSC_AC97STAT_TR (1 << 8)
#define PSC_AC97STAT_RB (1 << 5)
#define PSC_AC97STAT_TB (1 << 4)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PSC_AC97STAT_DI (1 << 2)
#define PSC_AC97STAT_DR (1 << 1)
#define PSC_AC97STAT_SR (1 << 0)
#define PSC_AC97EVNT_GR (1 << 25)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PSC_AC97EVNT_CD (1 << 24)
#define PSC_AC97EVNT_RR (1 << 13)
#define PSC_AC97EVNT_RO (1 << 12)
#define PSC_AC97EVNT_RU (1 << 11)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PSC_AC97EVNT_TR (1 << 10)
#define PSC_AC97EVNT_TO (1 << 9)
#define PSC_AC97EVNT_TU (1 << 8)
#define PSC_AC97EVNT_RD (1 << 5)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PSC_AC97EVNT_TD (1 << 4)
#define PSC_AC97CDC_RD (1 << 25)
#define PSC_AC97CDC_ID_MASK (3 << 23)
#define PSC_AC97CDC_INDX_MASK (0x7f << 16)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PSC_AC97CDC_ID(x) (((x) & 0x03) << 23)
#define PSC_AC97CDC_INDX(x) (((x) & 0x7f) << 16)
#define PSC_AC97RST_RST (1 << 1)
#define PSC_AC97RST_SNC (1 << 0)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
typedef struct psc_i2s {
u32 psc_sel;
u32 psc_ctrl;
u32 psc_i2scfg;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
u32 psc_i2smsk;
u32 psc_i2spcr;
u32 psc_i2sstat;
u32 psc_i2sevent;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
u32 psc_i2stxrx;
u32 psc_i2sudf;
} psc_i2s_t;
#define PSC_I2SCFG_OFFSET 0x08
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PSC_I2SMASK_OFFSET 0x0C
#define PSC_I2SPCR_OFFSET 0x10
#define PSC_I2SSTAT_OFFSET 0x14
#define PSC_I2SEVENT_OFFSET 0x18
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PSC_I2SRXTX_OFFSET 0x1C
#define PSC_I2SUDF_OFFSET 0x20
#define PSC_I2SCFG_RT_MASK (3 << 30)
#define PSC_I2SCFG_RT_FIFO1 (0 << 30)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PSC_I2SCFG_RT_FIFO2 (1 << 30)
#define PSC_I2SCFG_RT_FIFO4 (2 << 30)
#define PSC_I2SCFG_RT_FIFO8 (3 << 30)
#define PSC_I2SCFG_TT_MASK (3 << 28)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PSC_I2SCFG_TT_FIFO1 (0 << 28)
#define PSC_I2SCFG_TT_FIFO2 (1 << 28)
#define PSC_I2SCFG_TT_FIFO4 (2 << 28)
#define PSC_I2SCFG_TT_FIFO8 (3 << 28)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PSC_I2SCFG_DD_DISABLE (1 << 27)
#define PSC_I2SCFG_DE_ENABLE (1 << 26)
#define PSC_I2SCFG_SET_WS(x) (((((x) / 2) - 1) & 0x7f) << 16)
#define PSC_I2SCFG_WS(n) ((n & 0xFF) << 16)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PSC_I2SCFG_WS_MASK (PSC_I2SCFG_WS(0x3F))
#define PSC_I2SCFG_WI (1 << 15)
#define PSC_I2SCFG_DIV_MASK (3 << 13)
#define PSC_I2SCFG_DIV2 (0 << 13)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PSC_I2SCFG_DIV4 (1 << 13)
#define PSC_I2SCFG_DIV8 (2 << 13)
#define PSC_I2SCFG_DIV16 (3 << 13)
#define PSC_I2SCFG_BI (1 << 12)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PSC_I2SCFG_BUF (1 << 11)
#define PSC_I2SCFG_MLJ (1 << 10)
#define PSC_I2SCFG_XM (1 << 9)
#define PSC_I2SCFG_SET_LEN(x) ((((x) - 1) & 0x1f) << 4)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PSC_I2SCFG_GET_LEN(x) ((((x) >> 4) & 0x1f) + 1)
#define PSC_I2SCFG_LB (1 << 2)
#define PSC_I2SCFG_MLF (1 << 1)
#define PSC_I2SCFG_MS (1 << 0)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PSC_I2SMSK_RR (1 << 13)
#define PSC_I2SMSK_RO (1 << 12)
#define PSC_I2SMSK_RU (1 << 11)
#define PSC_I2SMSK_TR (1 << 10)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PSC_I2SMSK_TO (1 << 9)
#define PSC_I2SMSK_TU (1 << 8)
#define PSC_I2SMSK_RD (1 << 5)
#define PSC_I2SMSK_TD (1 << 4)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PSC_I2SMSK_ALLMASK (PSC_I2SMSK_RR | PSC_I2SMSK_RO | PSC_I2SMSK_RU | PSC_I2SMSK_TR | PSC_I2SMSK_TO | PSC_I2SMSK_TU | PSC_I2SMSK_RD | PSC_I2SMSK_TD)
#define PSC_I2SPCR_RC (1 << 6)
#define PSC_I2SPCR_RP (1 << 5)
#define PSC_I2SPCR_RS (1 << 4)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PSC_I2SPCR_TC (1 << 2)
#define PSC_I2SPCR_TP (1 << 1)
#define PSC_I2SPCR_TS (1 << 0)
#define PSC_I2SSTAT_RF (1 << 13)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PSC_I2SSTAT_RE (1 << 12)
#define PSC_I2SSTAT_RR (1 << 11)
#define PSC_I2SSTAT_TF (1 << 10)
#define PSC_I2SSTAT_TE (1 << 9)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PSC_I2SSTAT_TR (1 << 8)
#define PSC_I2SSTAT_RB (1 << 5)
#define PSC_I2SSTAT_TB (1 << 4)
#define PSC_I2SSTAT_DI (1 << 2)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PSC_I2SSTAT_DR (1 << 1)
#define PSC_I2SSTAT_SR (1 << 0)
#define PSC_I2SEVNT_RR (1 << 13)
#define PSC_I2SEVNT_RO (1 << 12)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PSC_I2SEVNT_RU (1 << 11)
#define PSC_I2SEVNT_TR (1 << 10)
#define PSC_I2SEVNT_TO (1 << 9)
#define PSC_I2SEVNT_TU (1 << 8)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PSC_I2SEVNT_RD (1 << 5)
#define PSC_I2SEVNT_TD (1 << 4)
typedef struct psc_spi {
u32 psc_sel;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
u32 psc_ctrl;
u32 psc_spicfg;
u32 psc_spimsk;
u32 psc_spipcr;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
u32 psc_spistat;
u32 psc_spievent;
u32 psc_spitxrx;
} psc_spi_t;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PSC_SPICFG_RT_MASK (3 << 30)
#define PSC_SPICFG_RT_FIFO1 (0 << 30)
#define PSC_SPICFG_RT_FIFO2 (1 << 30)
#define PSC_SPICFG_RT_FIFO4 (2 << 30)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PSC_SPICFG_RT_FIFO8 (3 << 30)
#define PSC_SPICFG_TT_MASK (3 << 28)
#define PSC_SPICFG_TT_FIFO1 (0 << 28)
#define PSC_SPICFG_TT_FIFO2 (1 << 28)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PSC_SPICFG_TT_FIFO4 (2 << 28)
#define PSC_SPICFG_TT_FIFO8 (3 << 28)
#define PSC_SPICFG_DD_DISABLE (1 << 27)
#define PSC_SPICFG_DE_ENABLE (1 << 26)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PSC_SPICFG_CLR_BAUD(x) ((x) & ~((0x3f) << 15))
#define PSC_SPICFG_SET_BAUD(x) (((x) & 0x3f) << 15)
#define PSC_SPICFG_SET_DIV(x) (((x) & 0x03) << 13)
#define PSC_SPICFG_DIV2 0
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PSC_SPICFG_DIV4 1
#define PSC_SPICFG_DIV8 2
#define PSC_SPICFG_DIV16 3
#define PSC_SPICFG_BI (1 << 12)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PSC_SPICFG_PSE (1 << 11)
#define PSC_SPICFG_CGE (1 << 10)
#define PSC_SPICFG_CDE (1 << 9)
#define PSC_SPICFG_CLR_LEN(x) ((x) & ~((0x1f) << 4))
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PSC_SPICFG_SET_LEN(x) (((x-1) & 0x1f) << 4)
#define PSC_SPICFG_LB (1 << 3)
#define PSC_SPICFG_MLF (1 << 1)
#define PSC_SPICFG_MO (1 << 0)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PSC_SPIMSK_MM (1 << 16)
#define PSC_SPIMSK_RR (1 << 13)
#define PSC_SPIMSK_RO (1 << 12)
#define PSC_SPIMSK_RU (1 << 11)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PSC_SPIMSK_TR (1 << 10)
#define PSC_SPIMSK_TO (1 << 9)
#define PSC_SPIMSK_TU (1 << 8)
#define PSC_SPIMSK_SD (1 << 5)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PSC_SPIMSK_MD (1 << 4)
#define PSC_SPIMSK_ALLMASK (PSC_SPIMSK_MM | PSC_SPIMSK_RR | PSC_SPIMSK_RO | PSC_SPIMSK_TO | PSC_SPIMSK_TU | PSC_SPIMSK_SD | PSC_SPIMSK_MD)
#define PSC_SPIPCR_RC (1 << 6)
#define PSC_SPIPCR_SP (1 << 5)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PSC_SPIPCR_SS (1 << 4)
#define PSC_SPIPCR_TC (1 << 2)
#define PSC_SPIPCR_MS (1 << 0)
#define PSC_SPISTAT_RF (1 << 13)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PSC_SPISTAT_RE (1 << 12)
#define PSC_SPISTAT_RR (1 << 11)
#define PSC_SPISTAT_TF (1 << 10)
#define PSC_SPISTAT_TE (1 << 9)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PSC_SPISTAT_TR (1 << 8)
#define PSC_SPISTAT_SB (1 << 5)
#define PSC_SPISTAT_MB (1 << 4)
#define PSC_SPISTAT_DI (1 << 2)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PSC_SPISTAT_DR (1 << 1)
#define PSC_SPISTAT_SR (1 << 0)
#define PSC_SPIEVNT_MM (1 << 16)
#define PSC_SPIEVNT_RR (1 << 13)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PSC_SPIEVNT_RO (1 << 12)
#define PSC_SPIEVNT_RU (1 << 11)
#define PSC_SPIEVNT_TR (1 << 10)
#define PSC_SPIEVNT_TO (1 << 9)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PSC_SPIEVNT_TU (1 << 8)
#define PSC_SPIEVNT_SD (1 << 5)
#define PSC_SPIEVNT_MD (1 << 4)
#define PSC_SPITXRX_LC (1 << 29)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PSC_SPITXRX_SR (1 << 28)
typedef struct psc_smb {
u32 psc_sel;
u32 psc_ctrl;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
u32 psc_smbcfg;
u32 psc_smbmsk;
u32 psc_smbpcr;
u32 psc_smbstat;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
u32 psc_smbevnt;
u32 psc_smbtxrx;
u32 psc_smbtmr;
} psc_smb_t;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PSC_SMBCFG_RT_MASK (3 << 30)
#define PSC_SMBCFG_RT_FIFO1 (0 << 30)
#define PSC_SMBCFG_RT_FIFO2 (1 << 30)
#define PSC_SMBCFG_RT_FIFO4 (2 << 30)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PSC_SMBCFG_RT_FIFO8 (3 << 30)
#define PSC_SMBCFG_TT_MASK (3 << 28)
#define PSC_SMBCFG_TT_FIFO1 (0 << 28)
#define PSC_SMBCFG_TT_FIFO2 (1 << 28)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PSC_SMBCFG_TT_FIFO4 (2 << 28)
#define PSC_SMBCFG_TT_FIFO8 (3 << 28)
#define PSC_SMBCFG_DD_DISABLE (1 << 27)
#define PSC_SMBCFG_DE_ENABLE (1 << 26)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PSC_SMBCFG_SET_DIV(x) (((x) & 0x03) << 13)
#define PSC_SMBCFG_DIV2 0
#define PSC_SMBCFG_DIV4 1
#define PSC_SMBCFG_DIV8 2
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PSC_SMBCFG_DIV16 3
#define PSC_SMBCFG_GCE (1 << 9)
#define PSC_SMBCFG_SFM (1 << 8)
#define PSC_SMBCFG_SET_SLV(x) (((x) & 0x7f) << 1)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PSC_SMBMSK_DN (1 << 30)
#define PSC_SMBMSK_AN (1 << 29)
#define PSC_SMBMSK_AL (1 << 28)
#define PSC_SMBMSK_RR (1 << 13)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PSC_SMBMSK_RO (1 << 12)
#define PSC_SMBMSK_RU (1 << 11)
#define PSC_SMBMSK_TR (1 << 10)
#define PSC_SMBMSK_TO (1 << 9)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PSC_SMBMSK_TU (1 << 8)
#define PSC_SMBMSK_SD (1 << 5)
#define PSC_SMBMSK_MD (1 << 4)
#define PSC_SMBMSK_ALLMASK (PSC_SMBMSK_DN | PSC_SMBMSK_AN | PSC_SMBMSK_AL | PSC_SMBMSK_RR | PSC_SMBMSK_RO | PSC_SMBMSK_TO | PSC_SMBMSK_TU | PSC_SMBMSK_SD | PSC_SMBMSK_MD)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PSC_SMBPCR_DC (1 << 2)
#define PSC_SMBPCR_MS (1 << 0)
#define PSC_SMBSTAT_BB (1 << 28)
#define PSC_SMBSTAT_RF (1 << 13)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PSC_SMBSTAT_RE (1 << 12)
#define PSC_SMBSTAT_RR (1 << 11)
#define PSC_SMBSTAT_TF (1 << 10)
#define PSC_SMBSTAT_TE (1 << 9)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PSC_SMBSTAT_TR (1 << 8)
#define PSC_SMBSTAT_SB (1 << 5)
#define PSC_SMBSTAT_MB (1 << 4)
#define PSC_SMBSTAT_DI (1 << 2)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PSC_SMBSTAT_DR (1 << 1)
#define PSC_SMBSTAT_SR (1 << 0)
#define PSC_SMBEVNT_DN (1 << 30)
#define PSC_SMBEVNT_AN (1 << 29)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PSC_SMBEVNT_AL (1 << 28)
#define PSC_SMBEVNT_RR (1 << 13)
#define PSC_SMBEVNT_RO (1 << 12)
#define PSC_SMBEVNT_RU (1 << 11)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PSC_SMBEVNT_TR (1 << 10)
#define PSC_SMBEVNT_TO (1 << 9)
#define PSC_SMBEVNT_TU (1 << 8)
#define PSC_SMBEVNT_SD (1 << 5)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PSC_SMBEVNT_MD (1 << 4)
#define PSC_SMBEVNT_ALLCLR (PSC_SMBEVNT_DN | PSC_SMBEVNT_AN | PSC_SMBEVNT_AL | PSC_SMBEVNT_RR | PSC_SMBEVNT_RO | PSC_SMBEVNT_TO | PSC_SMBEVNT_TU | PSC_SMBEVNT_SD | PSC_SMBEVNT_MD)
#define PSC_SMBTXRX_RSR (1 << 28)
#define PSC_SMBTXRX_STP (1 << 29)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PSC_SMBTXRX_DATAMASK 0xff
#define PSC_SMBTMR_SET_TH(x) (((x) & 0x03) << 30)
#define PSC_SMBTMR_SET_PS(x) (((x) & 0x1f) << 25)
#define PSC_SMBTMR_SET_PU(x) (((x) & 0x1f) << 20)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PSC_SMBTMR_SET_SH(x) (((x) & 0x1f) << 15)
#define PSC_SMBTMR_SET_SU(x) (((x) & 0x1f) << 10)
#define PSC_SMBTMR_SET_CL(x) (((x) & 0x1f) << 5)
#define PSC_SMBTMR_SET_CH(x) (((x) & 0x1f) << 0)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#endif

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/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef _ASM_MACH_GENERIC_SPACES_H
#define _ASM_MACH_GENERIC_SPACES_H
#include <linux/const.h>
#ifndef PHYS_OFFSET
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PHYS_OFFSET _AC(0, UL)
#endif
#ifndef PAGE_OFFSET
#define PAGE_OFFSET (CAC_BASE + PHYS_OFFSET)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#endif
#endif

25
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/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef __ASM_MACH_IP22_DS1286_H
#define __ASM_MACH_IP22_DS1286_H
#include <asm/sgi/hpc3.h>
#define rtc_read(reg) (hpc3c0->rtcregs[(reg)] & 0xff)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define rtc_write(data, reg) do { hpc3c0->rtcregs[(reg)] = (data); } while(0)
#endif

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/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef _ASM_MC146818RTC_H
#define _ASM_MC146818RTC_H
#include <mc146818rtc.h>
#endif
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */

363
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/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef _ASM_MIPS_BOARDS_BONITO64_H
#define _ASM_MIPS_BOARDS_BONITO64_H
#ifdef __ASSEMBLY__
#define BONITO(x) (x)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BONITO(x) *(volatile u32 *)(_pcictrl_bonito + (x))
#define BONITO_BOOT_BASE 0x1fc00000
#define BONITO_BOOT_SIZE 0x00100000
#define BONITO_BOOT_TOP (BONITO_BOOT_BASE+BONITO_BOOT_SIZE-1)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BONITO_FLASH_BASE 0x1c000000
#define BONITO_FLASH_SIZE 0x03000000
#define BONITO_FLASH_TOP (BONITO_FLASH_BASE+BONITO_FLASH_SIZE-1)
#define BONITO_SOCKET_BASE 0x1f800000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BONITO_SOCKET_SIZE 0x00400000
#define BONITO_SOCKET_TOP (BONITO_SOCKET_BASE+BONITO_SOCKET_SIZE-1)
#define BONITO_REG_BASE 0x1fe00000
#define BONITO_REG_SIZE 0x00040000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BONITO_REG_TOP (BONITO_REG_BASE+BONITO_REG_SIZE-1)
#define BONITO_DEV_BASE 0x1ff00000
#define BONITO_DEV_SIZE 0x00100000
#define BONITO_DEV_TOP (BONITO_DEV_BASE+BONITO_DEV_SIZE-1)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BONITO_PCILO_BASE 0x10000000
#define BONITO_PCILO_SIZE 0x0c000000
#define BONITO_PCILO_TOP (BONITO_PCILO_BASE+BONITO_PCILO_SIZE-1)
#define BONITO_PCILO0_BASE 0x10000000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BONITO_PCILO1_BASE 0x14000000
#define BONITO_PCILO2_BASE 0x18000000
#define BONITO_PCIHI_BASE 0x20000000
#define BONITO_PCIHI_SIZE 0x20000000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BONITO_PCIHI_TOP (BONITO_PCIHI_BASE+BONITO_PCIHI_SIZE-1)
#define BONITO_PCIIO_BASE 0x1fd00000
#define BONITO_PCIIO_SIZE 0x00100000
#define BONITO_PCIIO_TOP (BONITO_PCIIO_BASE+BONITO_PCIIO_SIZE-1)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BONITO_PCICFG_BASE 0x1fe80000
#define BONITO_PCICFG_SIZE 0x00080000
#define BONITO_PCICFG_TOP (BONITO_PCICFG_BASE+BONITO_PCICFG_SIZE-1)
#define BONITO_PCICONFIGBASE 0x00
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BONITO_REGBASE 0x100
#define BONITO_PCI_REG(x) BONITO(BONITO_PCICONFIGBASE + (x))
#define BONITO_PCIDID BONITO_PCI_REG(0x00)
#define BONITO_PCICMD BONITO_PCI_REG(0x04)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BONITO_PCICLASS BONITO_PCI_REG(0x08)
#define BONITO_PCILTIMER BONITO_PCI_REG(0x0c)
#define BONITO_PCIBASE0 BONITO_PCI_REG(0x10)
#define BONITO_PCIBASE1 BONITO_PCI_REG(0x14)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BONITO_PCIBASE2 BONITO_PCI_REG(0x18)
#define BONITO_PCIEXPRBASE BONITO_PCI_REG(0x30)
#define BONITO_PCIINT BONITO_PCI_REG(0x3c)
#define BONITO_PCICMD_PERR_CLR 0x80000000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BONITO_PCICMD_SERR_CLR 0x40000000
#define BONITO_PCICMD_MABORT_CLR 0x20000000
#define BONITO_PCICMD_MTABORT_CLR 0x10000000
#define BONITO_PCICMD_TABORT_CLR 0x08000000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BONITO_PCICMD_MPERR_CLR 0x01000000
#define BONITO_PCICMD_PERRRESPEN 0x00000040
#define BONITO_PCICMD_ASTEPEN 0x00000080
#define BONITO_PCICMD_SERREN 0x00000100
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BONITO_PCILTIMER_BUSLATENCY 0x0000ff00
#define BONITO_PCILTIMER_BUSLATENCY_SHIFT 8
#define BONITO_BONPONCFG BONITO(BONITO_REGBASE + 0x00)
#define BONITO_BONPONCFG_SYSCONTROLLERRD 0x00040000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BONITO_BONPONCFG_ROMCS1SAMP 0x00020000
#define BONITO_BONPONCFG_ROMCS0SAMP 0x00010000
#define BONITO_BONPONCFG_CPUBIGEND 0x00004000
#define BONITO_BONPONCFG_BURSTORDER 0x00001000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BONITO_BONPONCFG_CPUPARITY 0x00002000
#define BONITO_BONPONCFG_CPUTYPE 0x00000007
#define BONITO_BONPONCFG_CPUTYPE_SHIFT 0
#define BONITO_BONPONCFG_PCIRESET_OUT 0x00000008
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BONITO_BONPONCFG_IS_ARBITER 0x00000010
#define BONITO_BONPONCFG_ROMBOOT 0x000000c0
#define BONITO_BONPONCFG_ROMBOOT_SHIFT 6
#define BONITO_BONPONCFG_ROMBOOT_FLASH (0x0<<BONITO_BONPONCFG_ROMBOOT_SHIFT)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BONITO_BONPONCFG_ROMBOOT_SOCKET (0x1<<BONITO_BONPONCFG_ROMBOOT_SHIFT)
#define BONITO_BONPONCFG_ROMBOOT_SDRAM (0x2<<BONITO_BONPONCFG_ROMBOOT_SHIFT)
#define BONITO_BONPONCFG_ROMBOOT_CPURESET (0x3<<BONITO_BONPONCFG_ROMBOOT_SHIFT)
#define BONITO_BONPONCFG_ROMCS0WIDTH 0x00000100
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BONITO_BONPONCFG_ROMCS1WIDTH 0x00000200
#define BONITO_BONPONCFG_ROMCS0FAST 0x00000400
#define BONITO_BONPONCFG_ROMCS1FAST 0x00000800
#define BONITO_BONPONCFG_CONFIG_DIS 0x00000020
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BONITO_BONGENCFG_OFFSET 0x4
#define BONITO_BONGENCFG BONITO(BONITO_REGBASE + BONITO_BONGENCFG_OFFSET)
#define BONITO_BONGENCFG_DEBUGMODE 0x00000001
#define BONITO_BONGENCFG_SNOOPEN 0x00000002
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BONITO_BONGENCFG_CPUSELFRESET 0x00000004
#define BONITO_BONGENCFG_FORCE_IRQA 0x00000008
#define BONITO_BONGENCFG_IRQA_ISOUT 0x00000010
#define BONITO_BONGENCFG_IRQA_FROM_INT1 0x00000020
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BONITO_BONGENCFG_BYTESWAP 0x00000040
#define BONITO_BONGENCFG_UNCACHED 0x00000080
#define BONITO_BONGENCFG_PREFETCHEN 0x00000100
#define BONITO_BONGENCFG_WBEHINDEN 0x00000200
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BONITO_BONGENCFG_CACHEALG 0x00000c00
#define BONITO_BONGENCFG_CACHEALG_SHIFT 10
#define BONITO_BONGENCFG_PCIQUEUE 0x00001000
#define BONITO_BONGENCFG_CACHESTOP 0x00002000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BONITO_BONGENCFG_MSTRBYTESWAP 0x00004000
#define BONITO_BONGENCFG_BUSERREN 0x00008000
#define BONITO_BONGENCFG_NORETRYTIMEOUT 0x00010000
#define BONITO_BONGENCFG_SHORTCOPYTIMEOUT 0x00020000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BONITO_IODEVCFG BONITO(BONITO_REGBASE + 0x08)
#define BONITO_SDCFG BONITO(BONITO_REGBASE + 0x0c)
#define BONITO_PCIMAP BONITO(BONITO_REGBASE + 0x10)
#define BONITO_PCIMEMBASECFG BONITO(BONITO_REGBASE + 0x14)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BONITO_PCIMAP_CFG BONITO(BONITO_REGBASE + 0x18)
#define BONITO_GPIODATA_OFFSET 0x1c
#define BONITO_GPIODATA BONITO(BONITO_REGBASE + BONITO_GPIODATA_OFFSET)
#define BONITO_GPIOIE BONITO(BONITO_REGBASE + 0x20)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BONITO_INTEDGE BONITO(BONITO_REGBASE + 0x24)
#define BONITO_INTSTEER BONITO(BONITO_REGBASE + 0x28)
#define BONITO_INTPOL BONITO(BONITO_REGBASE + 0x2c)
#define BONITO_INTENSET BONITO(BONITO_REGBASE + 0x30)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BONITO_INTENCLR BONITO(BONITO_REGBASE + 0x34)
#define BONITO_INTEN BONITO(BONITO_REGBASE + 0x38)
#define BONITO_INTISR BONITO(BONITO_REGBASE + 0x3c)
#define BONITO_PCIMAIL0_OFFSET 0x40
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BONITO_PCIMAIL1_OFFSET 0x44
#define BONITO_PCIMAIL2_OFFSET 0x48
#define BONITO_PCIMAIL3_OFFSET 0x4c
#define BONITO_PCIMAIL0 BONITO(BONITO_REGBASE + 0x40)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BONITO_PCIMAIL1 BONITO(BONITO_REGBASE + 0x44)
#define BONITO_PCIMAIL2 BONITO(BONITO_REGBASE + 0x48)
#define BONITO_PCIMAIL3 BONITO(BONITO_REGBASE + 0x4c)
#define BONITO_PCICACHECTRL BONITO(BONITO_REGBASE + 0x50)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BONITO_PCICACHETAG BONITO(BONITO_REGBASE + 0x54)
#define BONITO_PCIBADADDR BONITO(BONITO_REGBASE + 0x58)
#define BONITO_PCIMSTAT BONITO(BONITO_REGBASE + 0x5c)
#define BONITO_CONFIGBASE 0x000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BONITO_BONITOBASE 0x100
#define BONITO_LDMABASE 0x200
#define BONITO_COPBASE 0x300
#define BONITO_REG_BLOCKMASK 0x300
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BONITO_LDMACTRL BONITO(BONITO_LDMABASE + 0x0)
#define BONITO_LDMASTAT BONITO(BONITO_LDMABASE + 0x0)
#define BONITO_LDMAADDR BONITO(BONITO_LDMABASE + 0x4)
#define BONITO_LDMAGO BONITO(BONITO_LDMABASE + 0x8)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BONITO_LDMADATA BONITO(BONITO_LDMABASE + 0xc)
#define BONITO_COPCTRL BONITO(BONITO_COPBASE + 0x0)
#define BONITO_COPSTAT BONITO(BONITO_COPBASE + 0x0)
#define BONITO_COPPADDR BONITO(BONITO_COPBASE + 0x4)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BONITO_COPDADDR BONITO(BONITO_COPBASE + 0x8)
#define BONITO_COPGO BONITO(BONITO_COPBASE + 0xc)
#define BONITO_IDECOPDADDR_DMA_DADDR 0x0ffffffc
#define BONITO_IDECOPDADDR_DMA_DADDR_SHIFT 2
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BONITO_IDECOPPADDR_DMA_PADDR 0xfffffffc
#define BONITO_IDECOPPADDR_DMA_PADDR_SHIFT 2
#define BONITO_IDECOPGO_DMA_SIZE 0x0000fffe
#define BONITO_IDECOPGO_DMA_SIZE_SHIFT 0
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BONITO_IDECOPGO_DMA_WRITE 0x00010000
#define BONITO_IDECOPGO_DMAWCOUNT 0x000f0000
#define BONITO_IDECOPGO_DMAWCOUNT_SHIFT 16
#define BONITO_IDECOPCTRL_DMA_STARTBIT 0x80000000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BONITO_IDECOPCTRL_DMA_RSTBIT 0x40000000
#define BONITO_SDCFG_AROWBITS 0x00000003
#define BONITO_SDCFG_AROWBITS_SHIFT 0
#define BONITO_SDCFG_ACOLBITS 0x0000000c
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BONITO_SDCFG_ACOLBITS_SHIFT 2
#define BONITO_SDCFG_ABANKBIT 0x00000010
#define BONITO_SDCFG_ASIDES 0x00000020
#define BONITO_SDCFG_AABSENT 0x00000040
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BONITO_SDCFG_AWIDTH64 0x00000080
#define BONITO_SDCFG_BROWBITS 0x00000300
#define BONITO_SDCFG_BROWBITS_SHIFT 8
#define BONITO_SDCFG_BCOLBITS 0x00000c00
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BONITO_SDCFG_BCOLBITS_SHIFT 10
#define BONITO_SDCFG_BBANKBIT 0x00001000
#define BONITO_SDCFG_BSIDES 0x00002000
#define BONITO_SDCFG_BABSENT 0x00004000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BONITO_SDCFG_BWIDTH64 0x00008000
#define BONITO_SDCFG_EXTRDDATA 0x00010000
#define BONITO_SDCFG_EXTRASCAS 0x00020000
#define BONITO_SDCFG_EXTPRECH 0x00040000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BONITO_SDCFG_EXTRASWIDTH 0x00180000
#define BONITO_SDCFG_EXTRASWIDTH_SHIFT 19
#define BONITO_SDCFG_DRAMMODESET 0x00200000
#define BONITO_SDCFG_DRAMEXTREGS 0x00400000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BONITO_SDCFG_DRAMPARITY 0x00800000
#define BONITO_SDCFG_DRAMBURSTLEN 0x03000000
#define BONITO_SDCFG_DRAMBURSTLEN_SHIFT 24
#define BONITO_SDCFG_DRAMMODESET_DONE 0x80000000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BONITO_PCICACHECTRL_CACHECMD 0x00000007
#define BONITO_PCICACHECTRL_CACHECMD_SHIFT 0
#define BONITO_PCICACHECTRL_CACHECMDLINE 0x00000018
#define BONITO_PCICACHECTRL_CACHECMDLINE_SHIFT 3
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BONITO_PCICACHECTRL_CMDEXEC 0x00000020
#define BONITO_PCICACHECTRL_IOBCCOH_PRES 0x00000100
#define BONITO_PCICACHECTRL_IOBCCOH_EN 0x00000200
#define BONITO_PCICACHECTRL_CPUCOH_PRES 0x00000400
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BONITO_PCICACHECTRL_CPUCOH_EN 0x00000800
#define BONITO_IODEVCFG_BUFFBIT_CS0 0x00000001
#define BONITO_IODEVCFG_SPEEDBIT_CS0 0x00000002
#define BONITO_IODEVCFG_MOREABITS_CS0 0x00000004
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BONITO_IODEVCFG_BUFFBIT_CS1 0x00000008
#define BONITO_IODEVCFG_SPEEDBIT_CS1 0x00000010
#define BONITO_IODEVCFG_MOREABITS_CS1 0x00000020
#define BONITO_IODEVCFG_BUFFBIT_CS2 0x00000040
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BONITO_IODEVCFG_SPEEDBIT_CS2 0x00000080
#define BONITO_IODEVCFG_MOREABITS_CS2 0x00000100
#define BONITO_IODEVCFG_BUFFBIT_CS3 0x00000200
#define BONITO_IODEVCFG_SPEEDBIT_CS3 0x00000400
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BONITO_IODEVCFG_MOREABITS_CS3 0x00000800
#define BONITO_IODEVCFG_BUFFBIT_IDE 0x00001000
#define BONITO_IODEVCFG_SPEEDBIT_IDE 0x00002000
#define BONITO_IODEVCFG_WORDSWAPBIT_IDE 0x00004000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BONITO_IODEVCFG_MODEBIT_IDE 0x00008000
#define BONITO_IODEVCFG_DMAON_IDE 0x001f0000
#define BONITO_IODEVCFG_DMAON_IDE_SHIFT 16
#define BONITO_IODEVCFG_DMAOFF_IDE 0x01e00000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BONITO_IODEVCFG_DMAOFF_IDE_SHIFT 21
#define BONITO_IODEVCFG_EPROMSPLIT 0x02000000
#define BONITO_IODEVCFG_CPUCLOCKPERIOD 0xfc000000
#define BONITO_IODEVCFG_CPUCLOCKPERIOD_SHIFT 26
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BONITO_GPIO_GPIOW 0x000003ff
#define BONITO_GPIO_GPIOW_SHIFT 0
#define BONITO_GPIO_GPIOR 0x01ff0000
#define BONITO_GPIO_GPIOR_SHIFT 16
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BONITO_GPIO_GPINR 0xfe000000
#define BONITO_GPIO_GPINR_SHIFT 25
#define BONITO_GPIO_IOW(N) (1<<(BONITO_GPIO_GPIOW_SHIFT+(N)))
#define BONITO_GPIO_IOR(N) (1<<(BONITO_GPIO_GPIOR_SHIFT+(N)))
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BONITO_GPIO_INR(N) (1<<(BONITO_GPIO_GPINR_SHIFT+(N)))
#define BONITO_ICU_MBOXES 0x0000000f
#define BONITO_ICU_MBOXES_SHIFT 0
#define BONITO_ICU_DMARDY 0x00000010
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BONITO_ICU_DMAEMPTY 0x00000020
#define BONITO_ICU_COPYRDY 0x00000040
#define BONITO_ICU_COPYEMPTY 0x00000080
#define BONITO_ICU_COPYERR 0x00000100
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BONITO_ICU_PCIIRQ 0x00000200
#define BONITO_ICU_MASTERERR 0x00000400
#define BONITO_ICU_SYSTEMERR 0x00000800
#define BONITO_ICU_DRAMPERR 0x00001000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BONITO_ICU_RETRYERR 0x00002000
#define BONITO_ICU_GPIOS 0x01ff0000
#define BONITO_ICU_GPIOS_SHIFT 16
#define BONITO_ICU_GPINS 0x7e000000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BONITO_ICU_GPINS_SHIFT 25
#define BONITO_ICU_MBOX(N) (1<<(BONITO_ICU_MBOXES_SHIFT+(N)))
#define BONITO_ICU_GPIO(N) (1<<(BONITO_ICU_GPIOS_SHIFT+(N)))
#define BONITO_ICU_GPIN(N) (1<<(BONITO_ICU_GPINS_SHIFT+(N)))
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BONITO_PCIMAP_PCIMAP_LO0 0x0000003f
#define BONITO_PCIMAP_PCIMAP_LO0_SHIFT 0
#define BONITO_PCIMAP_PCIMAP_LO1 0x00000fc0
#define BONITO_PCIMAP_PCIMAP_LO1_SHIFT 6
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BONITO_PCIMAP_PCIMAP_LO2 0x0003f000
#define BONITO_PCIMAP_PCIMAP_LO2_SHIFT 12
#define BONITO_PCIMAP_PCIMAP_2 0x00040000
#define BONITO_PCIMAP_WIN(WIN, ADDR) ((((ADDR)>>26) & BONITO_PCIMAP_PCIMAP_LO0) << ((WIN)*6))
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BONITO_PCIMAP_WINSIZE (1<<26)
#define BONITO_PCIMAP_WINOFFSET(ADDR) ((ADDR) & (BONITO_PCIMAP_WINSIZE - 1))
#define BONITO_PCIMAP_WINBASE(ADDR) ((ADDR) << 26)
#define BONITO_PCIMEMBASECFG_MASK 0xf0000000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BONITO_PCIMEMBASECFG_MEMBASE0_MASK 0x0000001f
#define BONITO_PCIMEMBASECFG_MEMBASE0_MASK_SHIFT 0
#define BONITO_PCIMEMBASECFG_MEMBASE0_TRANS 0x000003e0
#define BONITO_PCIMEMBASECFG_MEMBASE0_TRANS_SHIFT 5
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BONITO_PCIMEMBASECFG_MEMBASE0_CACHED 0x00000400
#define BONITO_PCIMEMBASECFG_MEMBASE0_IO 0x00000800
#define BONITO_PCIMEMBASECFG_MEMBASE1_MASK 0x0001f000
#define BONITO_PCIMEMBASECFG_MEMBASE1_MASK_SHIFT 12
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BONITO_PCIMEMBASECFG_MEMBASE1_TRANS 0x003e0000
#define BONITO_PCIMEMBASECFG_MEMBASE1_TRANS_SHIFT 17
#define BONITO_PCIMEMBASECFG_MEMBASE1_CACHED 0x00400000
#define BONITO_PCIMEMBASECFG_MEMBASE1_IO 0x00800000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BONITO_PCIMEMBASECFG_ASHIFT 23
#define BONITO_PCIMEMBASECFG_AMASK 0x007fffff
#define BONITO_PCIMEMBASECFGSIZE(WIN, SIZE) (((~((SIZE)-1))>>(BONITO_PCIMEMBASECFG_ASHIFT-BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT)) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK)
#define BONITO_PCIMEMBASECFGBASE(WIN, BASE) (((BASE)>>(BONITO_PCIMEMBASECFG_ASHIFT-BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS_SHIFT)) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BONITO_PCIMEMBASECFG_SIZE(WIN, CFG) (((((~(CFG)) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK)) << (BONITO_PCIMEMBASECFG_ASHIFT - BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT)) | BONITO_PCIMEMBASECFG_AMASK)
#define BONITO_PCIMEMBASECFG_ADDRMASK(WIN, CFG) ((((CFG) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK) >> BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT) << BONITO_PCIMEMBASECFG_ASHIFT)
#define BONITO_PCIMEMBASECFG_ADDRMASK(WIN, CFG) ((((CFG) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK) >> BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT) << BONITO_PCIMEMBASECFG_ASHIFT)
#define BONITO_PCIMEMBASECFG_ADDRTRANS(WIN, CFG) ((((CFG) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS) >> BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS_SHIFT) << BONITO_PCIMEMBASECFG_ASHIFT)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BONITO_PCITOPHYS(WIN, ADDR, CFG) ( (((ADDR) & (~(BONITO_PCIMEMBASECFG_MASK))) & (~(BONITO_PCIMEMBASECFG_ADDRMASK(WIN, CFG)))) | (BONITO_PCIMEMBASECFG_ADDRTRANS(WIN, CFG)) )
#define BONITO_PCICMD_MEMEN 0x00000002
#define BONITO_PCICMD_MSTREN 0x00000004
#endif
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */

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/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef __ASM_MIPS_BOARDS_GENERIC_H
#define __ASM_MIPS_BOARDS_GENERIC_H
#include <asm/addrspace.h>
#include <asm/byteorder.h>
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#include <asm/mips-boards/bonito64.h>
#define ASCII_DISPLAY_WORD_BASE 0x1f000410
#define ASCII_DISPLAY_POS_BASE 0x1f000418
#define YAMON_PROM_PRINT_ADDR 0x1fc00504
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SOFTRES_REG 0x1f000500
#define GORESET 0x42
#define MIPS_REVISION_REG 0x1fc00010
#define MIPS_REVISION_CORID_QED_RM5261 0
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MIPS_REVISION_CORID_CORE_LV 1
#define MIPS_REVISION_CORID_BONITO64 2
#define MIPS_REVISION_CORID_CORE_20K 3
#define MIPS_REVISION_CORID_CORE_FPGA 4
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MIPS_REVISION_CORID_CORE_MSC 5
#define MIPS_REVISION_CORID_CORE_EMUL 6
#define MIPS_REVISION_CORID_CORE_FPGA2 7
#define MIPS_REVISION_CORID_CORE_FPGAR2 8
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MIPS_REVISION_CORID_CORE_FPGA3 9
#define MIPS_REVISION_CORID_CORE_24K 10
#define MIPS_REVISION_CORID_CORE_FPGA4 11
#define MIPS_REVISION_CORID_CORE_FPGA5 12
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MIPS_REVISION_CORID_CORE_EMUL_BON -1
#define MIPS_REVISION_CORID_CORE_EMUL_MSC -2
#define MIPS_REVISION_CORID (((*(volatile u32 *)ioremap(MIPS_REVISION_REG, 4)) >> 10) & 0x3f)
#define MIPS_REVISION_SCON_OTHER 0
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MIPS_REVISION_SCON_SOCITSC 1
#define MIPS_REVISION_SCON_SOCITSCP 2
#define MIPS_REVISION_SCON_UNKNOWN -1
#define MIPS_REVISION_SCON_GT64120 -2
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MIPS_REVISION_SCON_BONITO -3
#define MIPS_REVISION_SCON_BRTL -4
#define MIPS_REVISION_SCON_SOCIT -5
#define MIPS_REVISION_SCON_ROCIT -6
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MIPS_REVISION_SCONID (((*(volatile u32 *)ioremap(MIPS_REVISION_REG, 4)) >> 24) & 0xff)
#define mips_pcibios_init() do { } while (0)
#endif

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/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef __ASM_MIPS_BOARDS_MALTA_H
#define __ASM_MIPS_BOARDS_MALTA_H
#include <asm/addrspace.h>
#include <asm/io.h>
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#include <asm/mips-boards/msc01_pci.h>
#include <asm/gt64120.h>
#define MIPS_MSC01_IC_REG_BASE 0x1bc40000
#define MIPS_SOCITSC_IC_REG_BASE 0x1ffa0000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MALTA_GT_PORT_BASE get_gt_port_base(GT_PCI0IOLD_OFS)
#define MALTA_BONITO_PORT_BASE ((unsigned long)ioremap (0x1fd00000, 0x10000))
#define MALTA_MSC_PORT_BASE get_msc_port_base(MSC01_PCI_SC2PIOBASL)
#define GCMP_BASE_ADDR 0x1fbf8000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define GCMP_ADDRSPACE_SZ (256 * 1024)
#define GIC_BASE_ADDR 0x1bdc0000
#define GIC_ADDRSPACE_SZ (128 * 1024)
#define MSC01_BIU_REG_BASE 0x1bc80000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MSC01_BIU_ADDRSPACE_SZ (256 * 1024)
#define MSC01_SC_CFG_OFS 0x0110
#define MSC01_SC_CFG_GICPRES_MSK 0x00000004
#define MSC01_SC_CFG_GICPRES_SHF 2
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MSC01_SC_CFG_GICENA_SHF 3
#define MALTA_RTC_ADR_REG 0x70
#define MALTA_RTC_DAT_REG 0x71
#define SMSC_CONFIG_REG 0x3f0
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SMSC_DATA_REG 0x3f1
#define SMSC_CONFIG_DEVNUM 0x7
#define SMSC_CONFIG_ACTIVATE 0x30
#define SMSC_CONFIG_ENTER 0x55
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SMSC_CONFIG_EXIT 0xaa
#define SMSC_CONFIG_DEVNUM_FLOPPY 0
#define SMSC_CONFIG_ACTIVATE_ENABLE 1
#define SMSC_WRITE(x, a) outb(x, a)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MALTA_JMPRS_REG 0x1f000210
#endif

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/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef __ASM_MIPS_BOARDS_MSC01_PCI_H
#define __ASM_MIPS_BOARDS_MSC01_PCI_H
#define MSC01_PCI_ID_OFS 0x0000
#define MSC01_PCI_SC2PMBASL_OFS 0x0208
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MSC01_PCI_SC2PMMSKL_OFS 0x0218
#define MSC01_PCI_SC2PMMAPL_OFS 0x0228
#define MSC01_PCI_SC2PIOBASL_OFS 0x0248
#define MSC01_PCI_SC2PIOMSKL_OFS 0x0258
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MSC01_PCI_SC2PIOMAPL_OFS 0x0268
#define MSC01_PCI_P2SCMSKL_OFS 0x0308
#define MSC01_PCI_P2SCMAPL_OFS 0x0318
#define MSC01_PCI_INTCFG_OFS 0x0600
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MSC01_PCI_INTSTAT_OFS 0x0608
#define MSC01_PCI_CFGADDR_OFS 0x0610
#define MSC01_PCI_CFGDATA_OFS 0x0618
#define MSC01_PCI_IACK_OFS 0x0620
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MSC01_PCI_HEAD0_OFS 0x2000
#define MSC01_PCI_HEAD1_OFS 0x2008
#define MSC01_PCI_HEAD2_OFS 0x2010
#define MSC01_PCI_HEAD3_OFS 0x2018
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MSC01_PCI_HEAD4_OFS 0x2020
#define MSC01_PCI_HEAD5_OFS 0x2028
#define MSC01_PCI_HEAD6_OFS 0x2030
#define MSC01_PCI_HEAD7_OFS 0x2038
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MSC01_PCI_HEAD8_OFS 0x2040
#define MSC01_PCI_HEAD9_OFS 0x2048
#define MSC01_PCI_HEAD10_OFS 0x2050
#define MSC01_PCI_HEAD11_OFS 0x2058
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MSC01_PCI_HEAD12_OFS 0x2060
#define MSC01_PCI_HEAD13_OFS 0x2068
#define MSC01_PCI_HEAD14_OFS 0x2070
#define MSC01_PCI_HEAD15_OFS 0x2078
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MSC01_PCI_BAR0_OFS 0x2220
#define MSC01_PCI_CFG_OFS 0x2380
#define MSC01_PCI_SWAP_OFS 0x2388
#define MSC01_PCI_ID_ID_SHF 16
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MSC01_PCI_ID_ID_MSK 0x00ff0000
#define MSC01_PCI_ID_ID_HOSTBRIDGE 82
#define MSC01_PCI_ID_MAR_SHF 8
#define MSC01_PCI_ID_MAR_MSK 0x0000ff00
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MSC01_PCI_ID_MIR_SHF 0
#define MSC01_PCI_ID_MIR_MSK 0x000000ff
#define MSC01_PCI_SC2PMBASL_BAS_SHF 24
#define MSC01_PCI_SC2PMBASL_BAS_MSK 0xff000000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MSC01_PCI_SC2PMMSKL_MSK_SHF 24
#define MSC01_PCI_SC2PMMSKL_MSK_MSK 0xff000000
#define MSC01_PCI_SC2PMMAPL_MAP_SHF 24
#define MSC01_PCI_SC2PMMAPL_MAP_MSK 0xff000000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MSC01_PCI_SC2PIOBASL_BAS_SHF 24
#define MSC01_PCI_SC2PIOBASL_BAS_MSK 0xff000000
#define MSC01_PCI_SC2PIOMSKL_MSK_SHF 24
#define MSC01_PCI_SC2PIOMSKL_MSK_MSK 0xff000000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MSC01_PCI_SC2PIOMAPL_MAP_SHF 24
#define MSC01_PCI_SC2PIOMAPL_MAP_MSK 0xff000000
#define MSC01_PCI_P2SCMSKL_MSK_SHF 24
#define MSC01_PCI_P2SCMSKL_MSK_MSK 0xff000000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MSC01_PCI_P2SCMAPL_MAP_SHF 24
#define MSC01_PCI_P2SCMAPL_MAP_MSK 0xff000000
#define MSC01_PCI_INTCFG_RST_SHF 10
#define MSC01_PCI_INTCFG_RST_MSK 0x00000400
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MSC01_PCI_INTCFG_RST_BIT 0x00000400
#define MSC01_PCI_INTCFG_MWE_SHF 9
#define MSC01_PCI_INTCFG_MWE_MSK 0x00000200
#define MSC01_PCI_INTCFG_MWE_BIT 0x00000200
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MSC01_PCI_INTCFG_DTO_SHF 8
#define MSC01_PCI_INTCFG_DTO_MSK 0x00000100
#define MSC01_PCI_INTCFG_DTO_BIT 0x00000100
#define MSC01_PCI_INTCFG_MA_SHF 7
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MSC01_PCI_INTCFG_MA_MSK 0x00000080
#define MSC01_PCI_INTCFG_MA_BIT 0x00000080
#define MSC01_PCI_INTCFG_TA_SHF 6
#define MSC01_PCI_INTCFG_TA_MSK 0x00000040
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MSC01_PCI_INTCFG_TA_BIT 0x00000040
#define MSC01_PCI_INTCFG_RTY_SHF 5
#define MSC01_PCI_INTCFG_RTY_MSK 0x00000020
#define MSC01_PCI_INTCFG_RTY_BIT 0x00000020
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MSC01_PCI_INTCFG_MWP_SHF 4
#define MSC01_PCI_INTCFG_MWP_MSK 0x00000010
#define MSC01_PCI_INTCFG_MWP_BIT 0x00000010
#define MSC01_PCI_INTCFG_MRP_SHF 3
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MSC01_PCI_INTCFG_MRP_MSK 0x00000008
#define MSC01_PCI_INTCFG_MRP_BIT 0x00000008
#define MSC01_PCI_INTCFG_SWP_SHF 2
#define MSC01_PCI_INTCFG_SWP_MSK 0x00000004
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MSC01_PCI_INTCFG_SWP_BIT 0x00000004
#define MSC01_PCI_INTCFG_SRP_SHF 1
#define MSC01_PCI_INTCFG_SRP_MSK 0x00000002
#define MSC01_PCI_INTCFG_SRP_BIT 0x00000002
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MSC01_PCI_INTCFG_SE_SHF 0
#define MSC01_PCI_INTCFG_SE_MSK 0x00000001
#define MSC01_PCI_INTCFG_SE_BIT 0x00000001
#define MSC01_PCI_INTSTAT_RST_SHF 10
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MSC01_PCI_INTSTAT_RST_MSK 0x00000400
#define MSC01_PCI_INTSTAT_RST_BIT 0x00000400
#define MSC01_PCI_INTSTAT_MWE_SHF 9
#define MSC01_PCI_INTSTAT_MWE_MSK 0x00000200
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MSC01_PCI_INTSTAT_MWE_BIT 0x00000200
#define MSC01_PCI_INTSTAT_DTO_SHF 8
#define MSC01_PCI_INTSTAT_DTO_MSK 0x00000100
#define MSC01_PCI_INTSTAT_DTO_BIT 0x00000100
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MSC01_PCI_INTSTAT_MA_SHF 7
#define MSC01_PCI_INTSTAT_MA_MSK 0x00000080
#define MSC01_PCI_INTSTAT_MA_BIT 0x00000080
#define MSC01_PCI_INTSTAT_TA_SHF 6
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MSC01_PCI_INTSTAT_TA_MSK 0x00000040
#define MSC01_PCI_INTSTAT_TA_BIT 0x00000040
#define MSC01_PCI_INTSTAT_RTY_SHF 5
#define MSC01_PCI_INTSTAT_RTY_MSK 0x00000020
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MSC01_PCI_INTSTAT_RTY_BIT 0x00000020
#define MSC01_PCI_INTSTAT_MWP_SHF 4
#define MSC01_PCI_INTSTAT_MWP_MSK 0x00000010
#define MSC01_PCI_INTSTAT_MWP_BIT 0x00000010
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MSC01_PCI_INTSTAT_MRP_SHF 3
#define MSC01_PCI_INTSTAT_MRP_MSK 0x00000008
#define MSC01_PCI_INTSTAT_MRP_BIT 0x00000008
#define MSC01_PCI_INTSTAT_SWP_SHF 2
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MSC01_PCI_INTSTAT_SWP_MSK 0x00000004
#define MSC01_PCI_INTSTAT_SWP_BIT 0x00000004
#define MSC01_PCI_INTSTAT_SRP_SHF 1
#define MSC01_PCI_INTSTAT_SRP_MSK 0x00000002
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MSC01_PCI_INTSTAT_SRP_BIT 0x00000002
#define MSC01_PCI_INTSTAT_SE_SHF 0
#define MSC01_PCI_INTSTAT_SE_MSK 0x00000001
#define MSC01_PCI_INTSTAT_SE_BIT 0x00000001
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MSC01_PCI_CFGADDR_BNUM_SHF 16
#define MSC01_PCI_CFGADDR_BNUM_MSK 0x00ff0000
#define MSC01_PCI_CFGADDR_DNUM_SHF 11
#define MSC01_PCI_CFGADDR_DNUM_MSK 0x0000f800
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MSC01_PCI_CFGADDR_FNUM_SHF 8
#define MSC01_PCI_CFGADDR_FNUM_MSK 0x00000700
#define MSC01_PCI_CFGADDR_RNUM_SHF 2
#define MSC01_PCI_CFGADDR_RNUM_MSK 0x000000fc
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MSC01_PCI_CFGDATA_DATA_SHF 0
#define MSC01_PCI_CFGDATA_DATA_MSK 0xffffffff
#define MSC01_PCI_BAR0_SIZE_SHF 4
#define MSC01_PCI_BAR0_SIZE_MSK 0xfffffff0
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MSC01_PCI_BAR0_P_SHF 3
#define MSC01_PCI_BAR0_P_MSK 0x00000008
#define MSC01_PCI_BAR0_P_BIT MSC01_PCI_BAR0_P_MSK
#define MSC01_PCI_BAR0_D_SHF 1
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MSC01_PCI_BAR0_D_MSK 0x00000006
#define MSC01_PCI_BAR0_T_SHF 0
#define MSC01_PCI_BAR0_T_MSK 0x00000001
#define MSC01_PCI_BAR0_T_BIT MSC01_PCI_BAR0_T_MSK
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MSC01_PCI_CFG_RA_SHF 17
#define MSC01_PCI_CFG_RA_MSK 0x00020000
#define MSC01_PCI_CFG_RA_BIT MSC01_PCI_CFG_RA_MSK
#define MSC01_PCI_CFG_G_SHF 16
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MSC01_PCI_CFG_G_MSK 0x00010000
#define MSC01_PCI_CFG_G_BIT MSC01_PCI_CFG_G_MSK
#define MSC01_PCI_CFG_EN_SHF 15
#define MSC01_PCI_CFG_EN_MSK 0x00008000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MSC01_PCI_CFG_EN_BIT MSC01_PCI_CFG_EN_MSK
#define MSC01_PCI_CFG_MAXRTRY_SHF 0
#define MSC01_PCI_CFG_MAXRTRY_MSK 0x00000fff
#define MSC01_PCI_SWAP_IO_SHF 18
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MSC01_PCI_SWAP_IO_MSK 0x000c0000
#define MSC01_PCI_SWAP_MEM_SHF 16
#define MSC01_PCI_SWAP_MEM_MSK 0x00030000
#define MSC01_PCI_SWAP_BAR0_SHF 0
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MSC01_PCI_SWAP_BAR0_MSK 0x00000003
#define MSC01_PCI_SWAP_NOSWAP 0
#define MSC01_PCI_SWAP_BYTESWAP 1
#define MIPS_MSC01_PCI_REG_BASE 0x1bd00000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MIPS_SOCITSC_PCI_REG_BASE 0x1ff10000
#define MSC01_PCI_REG_BASE _pcictrl_msc
#define MSC_WRITE(reg, data) do { *(volatile u32 *)(reg) = data; } while (0)
#define MSC_READ(reg, data) do { data = *(volatile u32 *)(reg); } while (0)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MSC01_PCI_ID (MSC01_PCI_REG_BASE + MSC01_PCI_ID_OFS)
#define MSC01_PCI_SC2PMBASL (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PMBASL_OFS)
#define MSC01_PCI_SC2PMMSKL (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PMMSKL_OFS)
#define MSC01_PCI_SC2PMMAPL (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PMMAPL_OFS)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MSC01_PCI_SC2PIOBASL (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PIOBASL_OFS)
#define MSC01_PCI_SC2PIOMSKL (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PIOMSKL_OFS)
#define MSC01_PCI_SC2PIOMAPL (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PIOMAPL_OFS)
#define MSC01_PCI_P2SCMSKL (MSC01_PCI_REG_BASE + MSC01_PCI_P2SCMSKL_OFS)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MSC01_PCI_P2SCMAPL (MSC01_PCI_REG_BASE + MSC01_PCI_P2SCMAPL_OFS)
#define MSC01_PCI_INTCFG (MSC01_PCI_REG_BASE + MSC01_PCI_INTCFG_OFS)
#define MSC01_PCI_INTSTAT (MSC01_PCI_REG_BASE + MSC01_PCI_INTSTAT_OFS)
#define MSC01_PCI_CFGADDR (MSC01_PCI_REG_BASE + MSC01_PCI_CFGADDR_OFS)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MSC01_PCI_CFGDATA (MSC01_PCI_REG_BASE + MSC01_PCI_CFGDATA_OFS)
#define MSC01_PCI_IACK (MSC01_PCI_REG_BASE + MSC01_PCI_IACK_OFS)
#define MSC01_PCI_HEAD0 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD0_OFS)
#define MSC01_PCI_HEAD1 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD1_OFS)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MSC01_PCI_HEAD2 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD2_OFS)
#define MSC01_PCI_HEAD3 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD3_OFS)
#define MSC01_PCI_HEAD4 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD4_OFS)
#define MSC01_PCI_HEAD5 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD5_OFS)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MSC01_PCI_HEAD6 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD6_OFS)
#define MSC01_PCI_HEAD7 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD7_OFS)
#define MSC01_PCI_HEAD8 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD8_OFS)
#define MSC01_PCI_HEAD9 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD9_OFS)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MSC01_PCI_HEAD10 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD10_OFS)
#define MSC01_PCI_HEAD11 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD11_OFS)
#define MSC01_PCI_HEAD12 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD11_OFS)
#define MSC01_PCI_HEAD13 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD11_OFS)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MSC01_PCI_HEAD14 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD11_OFS)
#define MSC01_PCI_HEAD15 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD11_OFS)
#define MSC01_PCI_BAR0 (MSC01_PCI_REG_BASE + MSC01_PCI_BAR0_OFS)
#define MSC01_PCI_CFG (MSC01_PCI_REG_BASE + MSC01_PCI_CFG_OFS)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MSC01_PCI_SWAP (MSC01_PCI_REG_BASE + MSC01_PCI_SWAP_OFS)
#endif

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libc/kernel/arch-mips/asm/mips_mt.h Normal file
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/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef __ASM_MIPS_MT_H
#define __ASM_MIPS_MT_H
#include <linux/cpumask.h>
struct class;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#endif

214
libc/kernel/arch-mips/asm/mipsmtregs.h Normal file
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/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef _ASM_MIPSMTREGS_H
#define _ASM_MIPSMTREGS_H
#include <asm/mipsregs.h>
#include <asm/war.h>
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#ifndef __ASSEMBLY__
#define read_c0_mvpcontrol() __read_32bit_c0_register($0, 1)
#define write_c0_mvpcontrol(val) __write_32bit_c0_register($0, 1, val)
#define read_c0_mvpconf0() __read_32bit_c0_register($0, 2)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define read_c0_mvpconf1() __read_32bit_c0_register($0, 3)
#define read_c0_vpecontrol() __read_32bit_c0_register($1, 1)
#define write_c0_vpecontrol(val) __write_32bit_c0_register($1, 1, val)
#define read_c0_vpeconf0() __read_32bit_c0_register($1, 2)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define write_c0_vpeconf0(val) __write_32bit_c0_register($1, 2, val)
#define read_c0_tcstatus() __read_32bit_c0_register($2, 1)
#define write_c0_tcstatus(val) __write_32bit_c0_register($2, 1, val)
#define read_c0_tcbind() __read_32bit_c0_register($2, 2)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define read_c0_tccontext() __read_32bit_c0_register($2, 5)
#define write_c0_tccontext(val) __write_32bit_c0_register($2, 5, val)
#else
#define CP0_MVPCONTROL $0, 1
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define CP0_MVPCONF0 $0, 2
#define CP0_MVPCONF1 $0, 3
#define CP0_VPECONTROL $1, 1
#define CP0_VPECONF0 $1, 2
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define CP0_VPECONF1 $1, 3
#define CP0_YQMASK $1, 4
#define CP0_VPESCHEDULE $1, 5
#define CP0_VPESCHEFBK $1, 6
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define CP0_TCSTATUS $2, 1
#define CP0_TCBIND $2, 2
#define CP0_TCRESTART $2, 3
#define CP0_TCHALT $2, 4
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define CP0_TCCONTEXT $2, 5
#define CP0_TCSCHEDULE $2, 6
#define CP0_TCSCHEFBK $2, 7
#define CP0_SRSCONF0 $6, 1
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define CP0_SRSCONF1 $6, 2
#define CP0_SRSCONF2 $6, 3
#define CP0_SRSCONF3 $6, 4
#define CP0_SRSCONF4 $6, 5
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#endif
#define MVPCONTROL_EVP (_ULCAST_(1))
#define MVPCONTROL_VPC_SHIFT 1
#define MVPCONTROL_VPC (_ULCAST_(1) << MVPCONTROL_VPC_SHIFT)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MVPCONTROL_STLB_SHIFT 2
#define MVPCONTROL_STLB (_ULCAST_(1) << MVPCONTROL_STLB_SHIFT)
#define MVPCONF0_PTC_SHIFT 0
#define MVPCONF0_PTC ( _ULCAST_(0xff))
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MVPCONF0_PVPE_SHIFT 10
#define MVPCONF0_PVPE ( _ULCAST_(0xf) << MVPCONF0_PVPE_SHIFT)
#define MVPCONF0_TCA_SHIFT 15
#define MVPCONF0_TCA ( _ULCAST_(1) << MVPCONF0_TCA_SHIFT)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MVPCONF0_PTLBE_SHIFT 16
#define MVPCONF0_PTLBE (_ULCAST_(0x3ff) << MVPCONF0_PTLBE_SHIFT)
#define MVPCONF0_TLBS_SHIFT 29
#define MVPCONF0_TLBS (_ULCAST_(1) << MVPCONF0_TLBS_SHIFT)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MVPCONF0_M_SHIFT 31
#define MVPCONF0_M (_ULCAST_(0x1) << MVPCONF0_M_SHIFT)
#define CONFIG3_MT_SHIFT 2
#define CONFIG3_MT (_ULCAST_(1) << CONFIG3_MT_SHIFT)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define VPECONTROL_TARGTC (_ULCAST_(0xff))
#define VPECONTROL_TE_SHIFT 15
#define VPECONTROL_TE (_ULCAST_(1) << VPECONTROL_TE_SHIFT)
#define VPECONTROL_EXCPT_SHIFT 16
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define VPECONTROL_EXCPT (_ULCAST_(0x7) << VPECONTROL_EXCPT_SHIFT)
#define THREX_TU 0
#define THREX_TO 1
#define THREX_IYQ 2
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define THREX_GSX 3
#define THREX_YSCH 4
#define THREX_GSSCH 5
#define VPECONTROL_GSI_SHIFT 20
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define VPECONTROL_GSI (_ULCAST_(1) << VPECONTROL_GSI_SHIFT)
#define VPECONTROL_YSI_SHIFT 21
#define VPECONTROL_YSI (_ULCAST_(1) << VPECONTROL_YSI_SHIFT)
#define VPECONF0_VPA_SHIFT 0
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define VPECONF0_VPA (_ULCAST_(1) << VPECONF0_VPA_SHIFT)
#define VPECONF0_MVP_SHIFT 1
#define VPECONF0_MVP (_ULCAST_(1) << VPECONF0_MVP_SHIFT)
#define VPECONF0_XTC_SHIFT 21
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define VPECONF0_XTC (_ULCAST_(0xff) << VPECONF0_XTC_SHIFT)
#define TCSTATUS_TASID (_ULCAST_(0xff))
#define TCSTATUS_IXMT_SHIFT 10
#define TCSTATUS_IXMT (_ULCAST_(1) << TCSTATUS_IXMT_SHIFT)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define TCSTATUS_TKSU_SHIFT 11
#define TCSTATUS_TKSU (_ULCAST_(3) << TCSTATUS_TKSU_SHIFT)
#define TCSTATUS_A_SHIFT 13
#define TCSTATUS_A (_ULCAST_(1) << TCSTATUS_A_SHIFT)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define TCSTATUS_DA_SHIFT 15
#define TCSTATUS_DA (_ULCAST_(1) << TCSTATUS_DA_SHIFT)
#define TCSTATUS_DT_SHIFT 20
#define TCSTATUS_DT (_ULCAST_(1) << TCSTATUS_DT_SHIFT)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define TCSTATUS_TDS_SHIFT 21
#define TCSTATUS_TDS (_ULCAST_(1) << TCSTATUS_TDS_SHIFT)
#define TCSTATUS_TSST_SHIFT 22
#define TCSTATUS_TSST (_ULCAST_(1) << TCSTATUS_TSST_SHIFT)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define TCSTATUS_RNST_SHIFT 23
#define TCSTATUS_RNST (_ULCAST_(3) << TCSTATUS_RNST_SHIFT)
#define TC_RUNNING 0
#define TC_WAITING 1
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define TC_YIELDING 2
#define TC_GATED 3
#define TCSTATUS_TMX_SHIFT 27
#define TCSTATUS_TMX (_ULCAST_(1) << TCSTATUS_TMX_SHIFT)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define TCBIND_CURVPE_SHIFT 0
#define TCBIND_CURVPE (_ULCAST_(0xf))
#define TCBIND_CURTC_SHIFT 21
#define TCBIND_CURTC (_ULCAST_(0xff) << TCBIND_CURTC_SHIFT)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define TCHALT_H (_ULCAST_(1))
#ifndef __ASSEMBLY__
#define EVPE_ENABLE MVPCONTROL_EVP
#define EMT_ENABLE VPECONTROL_TE
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define mftc0(rt,sel) ({ unsigned long __res; __asm__ __volatile__( " .set push \n" " .set mips32r2 \n" " .set noat \n" " # mftc0 $1, $" #rt ", " #sel " \n" " .word 0x41000800 | (" #rt " << 16) | " #sel " \n" " move %0, $1 \n" " .set pop \n" : "=r" (__res)); __res; })
#define mftgpr(rt) ({ unsigned long __res; __asm__ __volatile__( " .set push \n" " .set noat \n" " .set mips32r2 \n" " # mftgpr $1," #rt " \n" " .word 0x41000820 | (" #rt " << 16) \n" " move %0, $1 \n" " .set pop \n" : "=r" (__res)); __res; })
#define mftr(rt, u, sel) ({ unsigned long __res; __asm__ __volatile__( " mftr %0, " #rt ", " #u ", " #sel " \n" : "=r" (__res)); __res; })
#define mttgpr(rd,v) do { __asm__ __volatile__( " .set push \n" " .set mips32r2 \n" " .set noat \n" " move $1, %0 \n" " # mttgpr $1, " #rd " \n" " .word 0x41810020 | (" #rd " << 11) \n" " .set pop \n" : : "r" (v)); } while (0)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define mttc0(rd, sel, v) ({ __asm__ __volatile__( " .set push \n" " .set mips32r2 \n" " .set noat \n" " move $1, %0 \n" " # mttc0 %0," #rd ", " #sel " \n" " .word 0x41810000 | (" #rd " << 11) | " #sel " \n" " .set pop \n" : : "r" (v)); })
#define mttr(rd, u, sel, v) ({ __asm__ __volatile__( "mttr %0," #rd ", " #u ", " #sel : : "r" (v)); })
#define settc(tc) do { write_c0_vpecontrol((read_c0_vpecontrol()&~VPECONTROL_TARGTC) | (tc)); ehb(); } while (0)
#define read_vpe_c0_vpecontrol() mftc0(1, 1)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define write_vpe_c0_vpecontrol(val) mttc0(1, 1, val)
#define read_vpe_c0_vpeconf0() mftc0(1, 2)
#define write_vpe_c0_vpeconf0(val) mttc0(1, 2, val)
#define read_vpe_c0_count() mftc0(9, 0)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define write_vpe_c0_count(val) mttc0(9, 0, val)
#define read_vpe_c0_status() mftc0(12, 0)
#define write_vpe_c0_status(val) mttc0(12, 0, val)
#define read_vpe_c0_cause() mftc0(13, 0)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define write_vpe_c0_cause(val) mttc0(13, 0, val)
#define read_vpe_c0_config() mftc0(16, 0)
#define write_vpe_c0_config(val) mttc0(16, 0, val)
#define read_vpe_c0_config1() mftc0(16, 1)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define write_vpe_c0_config1(val) mttc0(16, 1, val)
#define read_vpe_c0_config7() mftc0(16, 7)
#define write_vpe_c0_config7(val) mttc0(16, 7, val)
#define read_vpe_c0_ebase() mftc0(15, 1)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define write_vpe_c0_ebase(val) mttc0(15, 1, val)
#define write_vpe_c0_compare(val) mttc0(11, 0, val)
#define read_vpe_c0_badvaddr() mftc0(8, 0)
#define read_vpe_c0_epc() mftc0(14, 0)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define write_vpe_c0_epc(val) mttc0(14, 0, val)
#define read_tc_c0_tcstatus() mftc0(2, 1)
#define write_tc_c0_tcstatus(val) mttc0(2, 1, val)
#define read_tc_c0_tcbind() mftc0(2, 2)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define write_tc_c0_tcbind(val) mttc0(2, 2, val)
#define read_tc_c0_tcrestart() mftc0(2, 3)
#define write_tc_c0_tcrestart(val) mttc0(2, 3, val)
#define read_tc_c0_tchalt() mftc0(2, 4)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define write_tc_c0_tchalt(val) mttc0(2, 4, val)
#define read_tc_c0_tccontext() mftc0(2, 5)
#define write_tc_c0_tccontext(val) mttc0(2, 5, val)
#define read_tc_gpr_sp() mftgpr(29)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define write_tc_gpr_sp(val) mttgpr(29, val)
#define read_tc_gpr_gp() mftgpr(28)
#define write_tc_gpr_gp(val) mttgpr(28, val)
#endif
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#endif

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libc/kernel/arch-mips/asm/mipsregs.h Normal file
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/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef _ASM_MIPSREGS_H
#define _ASM_MIPSREGS_H
#include <linux/linkage.h>
#include <asm/hazards.h>
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#include <asm/war.h>
#ifndef __STR
#define __STR(x) #x
#endif
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#ifndef STR
#define STR(x) __STR(x)
#endif
#ifdef __ASSEMBLY__
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define _ULCAST_
#else
#define _ULCAST_ (unsigned long)
#endif
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define CP0_INDEX $0
#define CP0_RANDOM $1
#define CP0_ENTRYLO0 $2
#define CP0_ENTRYLO1 $3
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define CP0_CONF $3
#define CP0_CONTEXT $4
#define CP0_PAGEMASK $5
#define CP0_WIRED $6
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define CP0_INFO $7
#define CP0_BADVADDR $8
#define CP0_COUNT $9
#define CP0_ENTRYHI $10
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define CP0_COMPARE $11
#define CP0_STATUS $12
#define CP0_CAUSE $13
#define CP0_EPC $14
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define CP0_PRID $15
#define CP0_CONFIG $16
#define CP0_LLADDR $17
#define CP0_WATCHLO $18
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define CP0_WATCHHI $19
#define CP0_XCONTEXT $20
#define CP0_FRAMEMASK $21
#define CP0_DIAGNOSTIC $22
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define CP0_DEBUG $23
#define CP0_DEPC $24
#define CP0_PERFORMANCE $25
#define CP0_ECC $26
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define CP0_CACHEERR $27
#define CP0_TAGLO $28
#define CP0_TAGHI $29
#define CP0_ERROREPC $30
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define CP0_DESAVE $31
#define CP0_IBASE $0
#define CP0_IBOUND $1
#define CP0_DBASE $2
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define CP0_DBOUND $3
#define CP0_CALG $17
#define CP0_IWATCH $18
#define CP0_DWATCH $19
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define CP0_S1_DERRADDR0 $26
#define CP0_S1_DERRADDR1 $27
#define CP0_S1_INTCONTROL $20
#define CP0_S2_SRSCTL $12
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define CP0_S3_SRSMAP $12
#define CP0_TX39_CACHE $7
#define CP1_REVISION $0
#define CP1_STATUS $31
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define FPU_CSR_FLUSH 0x01000000
#define FPU_CSR_COND 0x00800000
#define FPU_CSR_COND0 0x00800000
#define FPU_CSR_COND1 0x02000000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define FPU_CSR_COND2 0x04000000
#define FPU_CSR_COND3 0x08000000
#define FPU_CSR_COND4 0x10000000
#define FPU_CSR_COND5 0x20000000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define FPU_CSR_COND6 0x40000000
#define FPU_CSR_COND7 0x80000000
#define FPU_CSR_ALL_X 0x0003f000
#define FPU_CSR_UNI_X 0x00020000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define FPU_CSR_INV_X 0x00010000
#define FPU_CSR_DIV_X 0x00008000
#define FPU_CSR_OVF_X 0x00004000
#define FPU_CSR_UDF_X 0x00002000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define FPU_CSR_INE_X 0x00001000
#define FPU_CSR_ALL_E 0x00000f80
#define FPU_CSR_INV_E 0x00000800
#define FPU_CSR_DIV_E 0x00000400
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define FPU_CSR_OVF_E 0x00000200
#define FPU_CSR_UDF_E 0x00000100
#define FPU_CSR_INE_E 0x00000080
#define FPU_CSR_ALL_S 0x0000007c
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define FPU_CSR_INV_S 0x00000040
#define FPU_CSR_DIV_S 0x00000020
#define FPU_CSR_OVF_S 0x00000010
#define FPU_CSR_UDF_S 0x00000008
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define FPU_CSR_INE_S 0x00000004
#define FPU_CSR_RN 0x0
#define FPU_CSR_RZ 0x1
#define FPU_CSR_RU 0x2
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define FPU_CSR_RD 0x3
#define PM_4K 0x00000000
#define PM_16K 0x00006000
#define PM_64K 0x0001e000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PM_256K 0x0007e000
#define PM_1M 0x001fe000
#define PM_4M 0x007fe000
#define PM_16M 0x01ffe000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PM_64M 0x07ffe000
#define PM_256M 0x1fffe000
#error Bad page size configuration!
#define PL_4K 12
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PL_16K 14
#define PL_64K 16
#define PL_256K 18
#define PL_1M 20
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PL_4M 22
#define PL_16M 24
#define PL_64M 26
#define PL_256M 28
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IE_SW0 (_ULCAST_(1) << 8)
#define IE_SW1 (_ULCAST_(1) << 9)
#define IE_IRQ0 (_ULCAST_(1) << 10)
#define IE_IRQ1 (_ULCAST_(1) << 11)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IE_IRQ2 (_ULCAST_(1) << 12)
#define IE_IRQ3 (_ULCAST_(1) << 13)
#define IE_IRQ4 (_ULCAST_(1) << 14)
#define IE_IRQ5 (_ULCAST_(1) << 15)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define C_SW0 (_ULCAST_(1) << 8)
#define C_SW1 (_ULCAST_(1) << 9)
#define C_IRQ0 (_ULCAST_(1) << 10)
#define C_IRQ1 (_ULCAST_(1) << 11)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define C_IRQ2 (_ULCAST_(1) << 12)
#define C_IRQ3 (_ULCAST_(1) << 13)
#define C_IRQ4 (_ULCAST_(1) << 14)
#define C_IRQ5 (_ULCAST_(1) << 15)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define ST0_IE 0x00000001
#define ST0_EXL 0x00000002
#define ST0_ERL 0x00000004
#define ST0_KSU 0x00000018
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define KSU_USER 0x00000010
#define KSU_SUPERVISOR 0x00000008
#define KSU_KERNEL 0x00000000
#define ST0_UX 0x00000020
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define ST0_SX 0x00000040
#define ST0_KX 0x00000080
#define ST0_DE 0x00010000
#define ST0_CE 0x00020000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define ST0_CO 0x08000000
#define ST0_IEC 0x00000001
#define ST0_KUC 0x00000002
#define ST0_IEP 0x00000004
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define ST0_KUP 0x00000008
#define ST0_IEO 0x00000010
#define ST0_KUO 0x00000020
#define ST0_ISC 0x00010000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define ST0_SWC 0x00020000
#define ST0_CM 0x00080000
#define ST0_UM (_ULCAST_(1) << 4)
#define ST0_IL (_ULCAST_(1) << 23)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define ST0_DL (_ULCAST_(1) << 24)
#define ST0_MX 0x01000000
#define TX39_CONF_ICS_SHIFT 19
#define TX39_CONF_ICS_MASK 0x00380000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define TX39_CONF_ICS_1KB 0x00000000
#define TX39_CONF_ICS_2KB 0x00080000
#define TX39_CONF_ICS_4KB 0x00100000
#define TX39_CONF_ICS_8KB 0x00180000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define TX39_CONF_ICS_16KB 0x00200000
#define TX39_CONF_DCS_SHIFT 16
#define TX39_CONF_DCS_MASK 0x00070000
#define TX39_CONF_DCS_1KB 0x00000000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define TX39_CONF_DCS_2KB 0x00010000
#define TX39_CONF_DCS_4KB 0x00020000
#define TX39_CONF_DCS_8KB 0x00030000
#define TX39_CONF_DCS_16KB 0x00040000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define TX39_CONF_CWFON 0x00004000
#define TX39_CONF_WBON 0x00002000
#define TX39_CONF_RF_SHIFT 10
#define TX39_CONF_RF_MASK 0x00000c00
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define TX39_CONF_DOZE 0x00000200
#define TX39_CONF_HALT 0x00000100
#define TX39_CONF_LOCK 0x00000080
#define TX39_CONF_ICE 0x00000020
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define TX39_CONF_DCE 0x00000010
#define TX39_CONF_IRSIZE_SHIFT 2
#define TX39_CONF_IRSIZE_MASK 0x0000000c
#define TX39_CONF_DRSIZE_SHIFT 0
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define TX39_CONF_DRSIZE_MASK 0x00000003
#define ST0_IM 0x0000ff00
#define STATUSB_IP0 8
#define STATUSF_IP0 (_ULCAST_(1) << 8)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define STATUSB_IP1 9
#define STATUSF_IP1 (_ULCAST_(1) << 9)
#define STATUSB_IP2 10
#define STATUSF_IP2 (_ULCAST_(1) << 10)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define STATUSB_IP3 11
#define STATUSF_IP3 (_ULCAST_(1) << 11)
#define STATUSB_IP4 12
#define STATUSF_IP4 (_ULCAST_(1) << 12)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define STATUSB_IP5 13
#define STATUSF_IP5 (_ULCAST_(1) << 13)
#define STATUSB_IP6 14
#define STATUSF_IP6 (_ULCAST_(1) << 14)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define STATUSB_IP7 15
#define STATUSF_IP7 (_ULCAST_(1) << 15)
#define STATUSB_IP8 0
#define STATUSF_IP8 (_ULCAST_(1) << 0)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define STATUSB_IP9 1
#define STATUSF_IP9 (_ULCAST_(1) << 1)
#define STATUSB_IP10 2
#define STATUSF_IP10 (_ULCAST_(1) << 2)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define STATUSB_IP11 3
#define STATUSF_IP11 (_ULCAST_(1) << 3)
#define STATUSB_IP12 4
#define STATUSF_IP12 (_ULCAST_(1) << 4)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define STATUSB_IP13 5
#define STATUSF_IP13 (_ULCAST_(1) << 5)
#define STATUSB_IP14 6
#define STATUSF_IP14 (_ULCAST_(1) << 6)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define STATUSB_IP15 7
#define STATUSF_IP15 (_ULCAST_(1) << 7)
#define ST0_CH 0x00040000
#define ST0_SR 0x00100000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define ST0_TS 0x00200000
#define ST0_BEV 0x00400000
#define ST0_RE 0x02000000
#define ST0_FR 0x04000000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define ST0_CU 0xf0000000
#define ST0_CU0 0x10000000
#define ST0_CU1 0x20000000
#define ST0_CU2 0x40000000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define ST0_CU3 0x80000000
#define ST0_XX 0x80000000
#define CAUSEB_EXCCODE 2
#define CAUSEF_EXCCODE (_ULCAST_(31) << 2)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define CAUSEB_IP 8
#define CAUSEF_IP (_ULCAST_(255) << 8)
#define CAUSEB_IP0 8
#define CAUSEF_IP0 (_ULCAST_(1) << 8)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define CAUSEB_IP1 9
#define CAUSEF_IP1 (_ULCAST_(1) << 9)
#define CAUSEB_IP2 10
#define CAUSEF_IP2 (_ULCAST_(1) << 10)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define CAUSEB_IP3 11
#define CAUSEF_IP3 (_ULCAST_(1) << 11)
#define CAUSEB_IP4 12
#define CAUSEF_IP4 (_ULCAST_(1) << 12)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define CAUSEB_IP5 13
#define CAUSEF_IP5 (_ULCAST_(1) << 13)
#define CAUSEB_IP6 14
#define CAUSEF_IP6 (_ULCAST_(1) << 14)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define CAUSEB_IP7 15
#define CAUSEF_IP7 (_ULCAST_(1) << 15)
#define CAUSEB_IV 23
#define CAUSEF_IV (_ULCAST_(1) << 23)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define CAUSEB_CE 28
#define CAUSEF_CE (_ULCAST_(3) << 28)
#define CAUSEB_BD 31
#define CAUSEF_BD (_ULCAST_(1) << 31)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define CONF_CM_CACHABLE_NO_WA 0
#define CONF_CM_CACHABLE_WA 1
#define CONF_CM_UNCACHED 2
#define CONF_CM_CACHABLE_NONCOHERENT 3
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define CONF_CM_CACHABLE_CE 4
#define CONF_CM_CACHABLE_COW 5
#define CONF_CM_CACHABLE_CUW 6
#define CONF_CM_CACHABLE_ACCELERATED 7
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define CONF_CM_CMASK 7
#define CONF_BE (_ULCAST_(1) << 15)
#define CONF_CU (_ULCAST_(1) << 3)
#define CONF_DB (_ULCAST_(1) << 4)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define CONF_IB (_ULCAST_(1) << 5)
#define CONF_DC (_ULCAST_(7) << 6)
#define CONF_IC (_ULCAST_(7) << 9)
#define CONF_EB (_ULCAST_(1) << 13)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define CONF_EM (_ULCAST_(1) << 14)
#define CONF_SM (_ULCAST_(1) << 16)
#define CONF_SC (_ULCAST_(1) << 17)
#define CONF_EW (_ULCAST_(3) << 18)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define CONF_EP (_ULCAST_(15)<< 24)
#define CONF_EC (_ULCAST_(7) << 28)
#define CONF_CM (_ULCAST_(1) << 31)
#define R4K_CONF_SW (_ULCAST_(1) << 20)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define R4K_CONF_SS (_ULCAST_(1) << 21)
#define R4K_CONF_SB (_ULCAST_(3) << 22)
#define R5K_CONF_SE (_ULCAST_(1) << 12)
#define R5K_CONF_SS (_ULCAST_(3) << 20)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define RM7K_CONF_SE (_ULCAST_(1) << 3)
#define RM7K_CONF_TE (_ULCAST_(1) << 12)
#define RM7K_CONF_CLK (_ULCAST_(1) << 16)
#define RM7K_CONF_TC (_ULCAST_(1) << 17)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define RM7K_CONF_SI (_ULCAST_(3) << 20)
#define RM7K_CONF_SC (_ULCAST_(1) << 31)
#define R10K_CONF_DN (_ULCAST_(3) << 3)
#define R10K_CONF_CT (_ULCAST_(1) << 5)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define R10K_CONF_PE (_ULCAST_(1) << 6)
#define R10K_CONF_PM (_ULCAST_(3) << 7)
#define R10K_CONF_EC (_ULCAST_(15)<< 9)
#define R10K_CONF_SB (_ULCAST_(1) << 13)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define R10K_CONF_SK (_ULCAST_(1) << 14)
#define R10K_CONF_SS (_ULCAST_(7) << 16)
#define R10K_CONF_SC (_ULCAST_(7) << 19)
#define R10K_CONF_DC (_ULCAST_(7) << 26)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define R10K_CONF_IC (_ULCAST_(7) << 29)
#define VR41_CONF_CS (_ULCAST_(1) << 12)
#define VR41_CONF_P4K (_ULCAST_(1) << 13)
#define VR41_CONF_BP (_ULCAST_(1) << 16)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define VR41_CONF_M16 (_ULCAST_(1) << 20)
#define VR41_CONF_AD (_ULCAST_(1) << 23)
#define R30XX_CONF_FDM (_ULCAST_(1) << 19)
#define R30XX_CONF_REV (_ULCAST_(1) << 22)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define R30XX_CONF_AC (_ULCAST_(1) << 23)
#define R30XX_CONF_RF (_ULCAST_(1) << 24)
#define R30XX_CONF_HALT (_ULCAST_(1) << 25)
#define R30XX_CONF_FPINT (_ULCAST_(7) << 26)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define R30XX_CONF_DBR (_ULCAST_(1) << 29)
#define R30XX_CONF_SB (_ULCAST_(1) << 30)
#define R30XX_CONF_LOCK (_ULCAST_(1) << 31)
#define TX49_CONF_DC (_ULCAST_(1) << 16)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define TX49_CONF_IC (_ULCAST_(1) << 17)
#define TX49_CONF_HALT (_ULCAST_(1) << 18)
#define TX49_CONF_CWFON (_ULCAST_(1) << 27)
#define MIPS_CONF_MT (_ULCAST_(7) << 7)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MIPS_CONF_AR (_ULCAST_(7) << 10)
#define MIPS_CONF_AT (_ULCAST_(3) << 13)
#define MIPS_CONF_M (_ULCAST_(1) << 31)
#define MIPS_CONF1_FP (_ULCAST_(1) << 0)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MIPS_CONF1_EP (_ULCAST_(1) << 1)
#define MIPS_CONF1_CA (_ULCAST_(1) << 2)
#define MIPS_CONF1_WR (_ULCAST_(1) << 3)
#define MIPS_CONF1_PC (_ULCAST_(1) << 4)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MIPS_CONF1_MD (_ULCAST_(1) << 5)
#define MIPS_CONF1_C2 (_ULCAST_(1) << 6)
#define MIPS_CONF1_DA (_ULCAST_(7) << 7)
#define MIPS_CONF1_DL (_ULCAST_(7) << 10)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MIPS_CONF1_DS (_ULCAST_(7) << 13)
#define MIPS_CONF1_IA (_ULCAST_(7) << 16)
#define MIPS_CONF1_IL (_ULCAST_(7) << 19)
#define MIPS_CONF1_IS (_ULCAST_(7) << 22)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MIPS_CONF1_TLBS (_ULCAST_(63)<< 25)
#define MIPS_CONF2_SA (_ULCAST_(15)<< 0)
#define MIPS_CONF2_SL (_ULCAST_(15)<< 4)
#define MIPS_CONF2_SS (_ULCAST_(15)<< 8)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MIPS_CONF2_SU (_ULCAST_(15)<< 12)
#define MIPS_CONF2_TA (_ULCAST_(15)<< 16)
#define MIPS_CONF2_TL (_ULCAST_(15)<< 20)
#define MIPS_CONF2_TS (_ULCAST_(15)<< 24)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MIPS_CONF2_TU (_ULCAST_(7) << 28)
#define MIPS_CONF3_TL (_ULCAST_(1) << 0)
#define MIPS_CONF3_SM (_ULCAST_(1) << 1)
#define MIPS_CONF3_MT (_ULCAST_(1) << 2)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MIPS_CONF3_SP (_ULCAST_(1) << 4)
#define MIPS_CONF3_VINT (_ULCAST_(1) << 5)
#define MIPS_CONF3_VEIC (_ULCAST_(1) << 6)
#define MIPS_CONF3_LPA (_ULCAST_(1) << 7)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MIPS_CONF3_DSP (_ULCAST_(1) << 10)
#define MIPS_CONF3_ULRI (_ULCAST_(1) << 13)
#define MIPS_CONF7_WII (_ULCAST_(1) << 31)
#define MIPS_CONF7_RPS (_ULCAST_(1) << 2)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MIPS_FPIR_S (_ULCAST_(1) << 16)
#define MIPS_FPIR_D (_ULCAST_(1) << 17)
#define MIPS_FPIR_PS (_ULCAST_(1) << 18)
#define MIPS_FPIR_3D (_ULCAST_(1) << 19)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MIPS_FPIR_W (_ULCAST_(1) << 20)
#define MIPS_FPIR_L (_ULCAST_(1) << 21)
#define MIPS_FPIR_F64 (_ULCAST_(1) << 22)
#ifndef __ASSEMBLY__
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define read_r10k_perf_cntr(counter) ({ unsigned int __res; __asm__ __volatile__( "mfpc\t%0, %1" : "=r" (__res) : "i" (counter)); __res; })
#define write_r10k_perf_cntr(counter,val) do { __asm__ __volatile__( "mtpc\t%0, %1" : : "r" (val), "i" (counter)); } while (0)
#define read_r10k_perf_event(counter) ({ unsigned int __res; __asm__ __volatile__( "mfps\t%0, %1" : "=r" (__res) : "i" (counter)); __res; })
#define write_r10k_perf_cntl(counter,val) do { __asm__ __volatile__( "mtps\t%0, %1" : : "r" (val), "i" (counter)); } while (0)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define __read_32bit_c0_register(source, sel) ({ int __res; if (sel == 0) __asm__ __volatile__( "mfc0\t%0, " #source "\n\t" : "=r" (__res)); else __asm__ __volatile__( ".set\tmips32\n\t" "mfc0\t%0, " #source ", " #sel "\n\t" ".set\tmips0\n\t" : "=r" (__res)); __res; })
#define __read_64bit_c0_register(source, sel) ({ unsigned long long __res; if (sizeof(unsigned long) == 4) __res = __read_64bit_c0_split(source, sel); else if (sel == 0) __asm__ __volatile__( ".set\tmips3\n\t" "dmfc0\t%0, " #source "\n\t" ".set\tmips0" : "=r" (__res)); else __asm__ __volatile__( ".set\tmips64\n\t" "dmfc0\t%0, " #source ", " #sel "\n\t" ".set\tmips0" : "=r" (__res)); __res; })
#define __write_32bit_c0_register(register, sel, value) do { if (sel == 0) __asm__ __volatile__( "mtc0\t%z0, " #register "\n\t" : : "Jr" ((unsigned int)(value))); else __asm__ __volatile__( ".set\tmips32\n\t" "mtc0\t%z0, " #register ", " #sel "\n\t" ".set\tmips0" : : "Jr" ((unsigned int)(value))); } while (0)
#define __write_64bit_c0_register(register, sel, value) do { if (sizeof(unsigned long) == 4) __write_64bit_c0_split(register, sel, value); else if (sel == 0) __asm__ __volatile__( ".set\tmips3\n\t" "dmtc0\t%z0, " #register "\n\t" ".set\tmips0" : : "Jr" (value)); else __asm__ __volatile__( ".set\tmips64\n\t" "dmtc0\t%z0, " #register ", " #sel "\n\t" ".set\tmips0" : : "Jr" (value)); } while (0)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define __read_ulong_c0_register(reg, sel) ((sizeof(unsigned long) == 4) ? (unsigned long) __read_32bit_c0_register(reg, sel) : (unsigned long) __read_64bit_c0_register(reg, sel))
#define __write_ulong_c0_register(reg, sel, val) do { if (sizeof(unsigned long) == 4) __write_32bit_c0_register(reg, sel, val); else __write_64bit_c0_register(reg, sel, val); } while (0)
#define __read_32bit_c0_ctrl_register(source) ({ int __res; __asm__ __volatile__( "cfc0\t%0, " #source "\n\t" : "=r" (__res)); __res; })
#define __write_32bit_c0_ctrl_register(register, value) do { __asm__ __volatile__( "ctc0\t%z0, " #register "\n\t" : : "Jr" ((unsigned int)(value))); } while (0)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define __read_64bit_c0_split(source, sel) ({ unsigned long long __val; unsigned long __flags; local_irq_save(__flags); if (sel == 0) __asm__ __volatile__( ".set\tmips64\n\t" "dmfc0\t%M0, " #source "\n\t" "dsll\t%L0, %M0, 32\n\t" "dsrl\t%M0, %M0, 32\n\t" "dsrl\t%L0, %L0, 32\n\t" ".set\tmips0" : "=r" (__val)); else __asm__ __volatile__( ".set\tmips64\n\t" "dmfc0\t%M0, " #source ", " #sel "\n\t" "dsll\t%L0, %M0, 32\n\t" "dsrl\t%M0, %M0, 32\n\t" "dsrl\t%L0, %L0, 32\n\t" ".set\tmips0" : "=r" (__val)); local_irq_restore(__flags); __val; })
#define __write_64bit_c0_split(source, sel, val) do { unsigned long __flags; local_irq_save(__flags); if (sel == 0) __asm__ __volatile__( ".set\tmips64\n\t" "dsll\t%L0, %L0, 32\n\t" "dsrl\t%L0, %L0, 32\n\t" "dsll\t%M0, %M0, 32\n\t" "or\t%L0, %L0, %M0\n\t" "dmtc0\t%L0, " #source "\n\t" ".set\tmips0" : : "r" (val)); else __asm__ __volatile__( ".set\tmips64\n\t" "dsll\t%L0, %L0, 32\n\t" "dsrl\t%L0, %L0, 32\n\t" "dsll\t%M0, %M0, 32\n\t" "or\t%L0, %L0, %M0\n\t" "dmtc0\t%L0, " #source ", " #sel "\n\t" ".set\tmips0" : : "r" (val)); local_irq_restore(__flags); } while (0)
#define read_c0_index() __read_32bit_c0_register($0, 0)
#define write_c0_index(val) __write_32bit_c0_register($0, 0, val)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define read_c0_random() __read_32bit_c0_register($1, 0)
#define write_c0_random(val) __write_32bit_c0_register($1, 0, val)
#define read_c0_entrylo0() __read_ulong_c0_register($2, 0)
#define write_c0_entrylo0(val) __write_ulong_c0_register($2, 0, val)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define read_c0_entrylo1() __read_ulong_c0_register($3, 0)
#define write_c0_entrylo1(val) __write_ulong_c0_register($3, 0, val)
#define read_c0_conf() __read_32bit_c0_register($3, 0)
#define write_c0_conf(val) __write_32bit_c0_register($3, 0, val)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define read_c0_context() __read_ulong_c0_register($4, 0)
#define write_c0_context(val) __write_ulong_c0_register($4, 0, val)
#define read_c0_userlocal() __read_ulong_c0_register($4, 2)
#define write_c0_userlocal(val) __write_ulong_c0_register($4, 2, val)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define read_c0_pagemask() __read_32bit_c0_register($5, 0)
#define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val)
#define read_c0_wired() __read_32bit_c0_register($6, 0)
#define write_c0_wired(val) __write_32bit_c0_register($6, 0, val)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define read_c0_info() __read_32bit_c0_register($7, 0)
#define read_c0_cache() __read_32bit_c0_register($7, 0)
#define write_c0_cache(val) __write_32bit_c0_register($7, 0, val)
#define read_c0_badvaddr() __read_ulong_c0_register($8, 0)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define write_c0_badvaddr(val) __write_ulong_c0_register($8, 0, val)
#define read_c0_count() __read_32bit_c0_register($9, 0)
#define write_c0_count(val) __write_32bit_c0_register($9, 0, val)
#define read_c0_count2() __read_32bit_c0_register($9, 6)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define write_c0_count2(val) __write_32bit_c0_register($9, 6, val)
#define read_c0_count3() __read_32bit_c0_register($9, 7)
#define write_c0_count3(val) __write_32bit_c0_register($9, 7, val)
#define read_c0_entryhi() __read_ulong_c0_register($10, 0)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define write_c0_entryhi(val) __write_ulong_c0_register($10, 0, val)
#define read_c0_compare() __read_32bit_c0_register($11, 0)
#define write_c0_compare(val) __write_32bit_c0_register($11, 0, val)
#define read_c0_compare2() __read_32bit_c0_register($11, 6)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define write_c0_compare2(val) __write_32bit_c0_register($11, 6, val)
#define read_c0_compare3() __read_32bit_c0_register($11, 7)
#define write_c0_compare3(val) __write_32bit_c0_register($11, 7, val)
#define read_c0_status() __read_32bit_c0_register($12, 0)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define write_c0_status(val) __write_32bit_c0_register($12, 0, val)
#define read_c0_cause() __read_32bit_c0_register($13, 0)
#define write_c0_cause(val) __write_32bit_c0_register($13, 0, val)
#define read_c0_epc() __read_ulong_c0_register($14, 0)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define write_c0_epc(val) __write_ulong_c0_register($14, 0, val)
#define read_c0_prid() __read_32bit_c0_register($15, 0)
#define read_c0_config() __read_32bit_c0_register($16, 0)
#define read_c0_config1() __read_32bit_c0_register($16, 1)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define read_c0_config2() __read_32bit_c0_register($16, 2)
#define read_c0_config3() __read_32bit_c0_register($16, 3)
#define read_c0_config4() __read_32bit_c0_register($16, 4)
#define read_c0_config5() __read_32bit_c0_register($16, 5)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define read_c0_config6() __read_32bit_c0_register($16, 6)
#define read_c0_config7() __read_32bit_c0_register($16, 7)
#define write_c0_config(val) __write_32bit_c0_register($16, 0, val)
#define write_c0_config1(val) __write_32bit_c0_register($16, 1, val)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define write_c0_config2(val) __write_32bit_c0_register($16, 2, val)
#define write_c0_config3(val) __write_32bit_c0_register($16, 3, val)
#define write_c0_config4(val) __write_32bit_c0_register($16, 4, val)
#define write_c0_config5(val) __write_32bit_c0_register($16, 5, val)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define write_c0_config6(val) __write_32bit_c0_register($16, 6, val)
#define write_c0_config7(val) __write_32bit_c0_register($16, 7, val)
#define read_c0_watchlo0() __read_ulong_c0_register($18, 0)
#define read_c0_watchlo1() __read_ulong_c0_register($18, 1)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define read_c0_watchlo2() __read_ulong_c0_register($18, 2)
#define read_c0_watchlo3() __read_ulong_c0_register($18, 3)
#define read_c0_watchlo4() __read_ulong_c0_register($18, 4)
#define read_c0_watchlo5() __read_ulong_c0_register($18, 5)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define read_c0_watchlo6() __read_ulong_c0_register($18, 6)
#define read_c0_watchlo7() __read_ulong_c0_register($18, 7)
#define write_c0_watchlo0(val) __write_ulong_c0_register($18, 0, val)
#define write_c0_watchlo1(val) __write_ulong_c0_register($18, 1, val)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define write_c0_watchlo2(val) __write_ulong_c0_register($18, 2, val)
#define write_c0_watchlo3(val) __write_ulong_c0_register($18, 3, val)
#define write_c0_watchlo4(val) __write_ulong_c0_register($18, 4, val)
#define write_c0_watchlo5(val) __write_ulong_c0_register($18, 5, val)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define write_c0_watchlo6(val) __write_ulong_c0_register($18, 6, val)
#define write_c0_watchlo7(val) __write_ulong_c0_register($18, 7, val)
#define read_c0_watchhi0() __read_32bit_c0_register($19, 0)
#define read_c0_watchhi1() __read_32bit_c0_register($19, 1)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define read_c0_watchhi2() __read_32bit_c0_register($19, 2)
#define read_c0_watchhi3() __read_32bit_c0_register($19, 3)
#define read_c0_watchhi4() __read_32bit_c0_register($19, 4)
#define read_c0_watchhi5() __read_32bit_c0_register($19, 5)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define read_c0_watchhi6() __read_32bit_c0_register($19, 6)
#define read_c0_watchhi7() __read_32bit_c0_register($19, 7)
#define write_c0_watchhi0(val) __write_32bit_c0_register($19, 0, val)
#define write_c0_watchhi1(val) __write_32bit_c0_register($19, 1, val)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define write_c0_watchhi2(val) __write_32bit_c0_register($19, 2, val)
#define write_c0_watchhi3(val) __write_32bit_c0_register($19, 3, val)
#define write_c0_watchhi4(val) __write_32bit_c0_register($19, 4, val)
#define write_c0_watchhi5(val) __write_32bit_c0_register($19, 5, val)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define write_c0_watchhi6(val) __write_32bit_c0_register($19, 6, val)
#define write_c0_watchhi7(val) __write_32bit_c0_register($19, 7, val)
#define read_c0_xcontext() __read_ulong_c0_register($20, 0)
#define write_c0_xcontext(val) __write_ulong_c0_register($20, 0, val)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define read_c0_intcontrol() __read_32bit_c0_ctrl_register($20)
#define write_c0_intcontrol(val) __write_32bit_c0_ctrl_register($20, val)
#define read_c0_framemask() __read_32bit_c0_register($21, 0)
#define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define read_c0_perfcontrol() __read_32bit_c0_register($22, 0)
#define write_c0_perfcontrol(val) __write_32bit_c0_register($22, 0, val)
#define read_c0_diag() __read_32bit_c0_register($22, 0)
#define write_c0_diag(val) __write_32bit_c0_register($22, 0, val)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define read_c0_diag1() __read_32bit_c0_register($22, 1)
#define write_c0_diag1(val) __write_32bit_c0_register($22, 1, val)
#define read_c0_diag2() __read_32bit_c0_register($22, 2)
#define write_c0_diag2(val) __write_32bit_c0_register($22, 2, val)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define read_c0_diag3() __read_32bit_c0_register($22, 3)
#define write_c0_diag3(val) __write_32bit_c0_register($22, 3, val)
#define read_c0_diag4() __read_32bit_c0_register($22, 4)
#define write_c0_diag4(val) __write_32bit_c0_register($22, 4, val)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define read_c0_diag5() __read_32bit_c0_register($22, 5)
#define write_c0_diag5(val) __write_32bit_c0_register($22, 5, val)
#define read_c0_debug() __read_32bit_c0_register($23, 0)
#define write_c0_debug(val) __write_32bit_c0_register($23, 0, val)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define read_c0_depc() __read_ulong_c0_register($24, 0)
#define write_c0_depc(val) __write_ulong_c0_register($24, 0, val)
#define read_c0_perfctrl0() __read_32bit_c0_register($25, 0)
#define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define read_c0_perfcntr0() __read_32bit_c0_register($25, 1)
#define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val)
#define read_c0_perfctrl1() __read_32bit_c0_register($25, 2)
#define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define read_c0_perfcntr1() __read_32bit_c0_register($25, 3)
#define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val)
#define read_c0_perfctrl2() __read_32bit_c0_register($25, 4)
#define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define read_c0_perfcntr2() __read_32bit_c0_register($25, 5)
#define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val)
#define read_c0_perfctrl3() __read_32bit_c0_register($25, 6)
#define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define read_c0_perfcntr3() __read_32bit_c0_register($25, 7)
#define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val)
#define read_c0_perfcount() __read_64bit_c0_register($25, 0)
#define write_c0_perfcount(val) __write_64bit_c0_register($25, 0, val)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define read_c0_ecc() __read_32bit_c0_register($26, 0)
#define write_c0_ecc(val) __write_32bit_c0_register($26, 0, val)
#define read_c0_derraddr0() __read_ulong_c0_register($26, 1)
#define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define read_c0_cacheerr() __read_32bit_c0_register($27, 0)
#define read_c0_derraddr1() __read_ulong_c0_register($27, 1)
#define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val)
#define read_c0_taglo() __read_32bit_c0_register($28, 0)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define write_c0_taglo(val) __write_32bit_c0_register($28, 0, val)
#define read_c0_dtaglo() __read_32bit_c0_register($28, 2)
#define write_c0_dtaglo(val) __write_32bit_c0_register($28, 2, val)
#define read_c0_taghi() __read_32bit_c0_register($29, 0)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define write_c0_taghi(val) __write_32bit_c0_register($29, 0, val)
#define read_c0_errorepc() __read_ulong_c0_register($30, 0)
#define write_c0_errorepc(val) __write_ulong_c0_register($30, 0, val)
#define read_c0_hwrena() __read_32bit_c0_register($7, 0)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define write_c0_hwrena(val) __write_32bit_c0_register($7, 0, val)
#define read_c0_intctl() __read_32bit_c0_register($12, 1)
#define write_c0_intctl(val) __write_32bit_c0_register($12, 1, val)
#define read_c0_srsctl() __read_32bit_c0_register($12, 2)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define write_c0_srsctl(val) __write_32bit_c0_register($12, 2, val)
#define read_c0_srsmap() __read_32bit_c0_register($12, 3)
#define write_c0_srsmap(val) __write_32bit_c0_register($12, 3, val)
#define read_c0_ebase() __read_32bit_c0_register($15, 1)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val)
#define read_32bit_cp1_register(source) ({ int __res; __asm__ __volatile__( ".set\tpush\n\t" ".set\treorder\n\t" "cfc1\t%0,"STR(source)"\n\t" ".set\tpop" : "=r" (__res)); __res;})
#define rddsp(mask) ({ unsigned int __res; __asm__ __volatile__( " .set push \n" " .set noat \n" " # rddsp $1, %x1 \n" " .word 0x7c000cb8 | (%x1 << 16) \n" " move %0, $1 \n" " .set pop \n" : "=r" (__res) : "i" (mask)); __res; })
#define wrdsp(val, mask) do { __asm__ __volatile__( " .set push \n" " .set noat \n" " move $1, %0 \n" " # wrdsp $1, %x1 \n" " .word 0x7c2004f8 | (%x1 << 11) \n" " .set pop \n" : : "r" (val), "i" (mask)); } while (0)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define mfhi0() ({ unsigned long __treg; __asm__ __volatile__( " .set push \n" " .set noat \n" " # mfhi %0, $ac0 \n" " .word 0x00000810 \n" " move %0, $1 \n" " .set pop \n" : "=r" (__treg)); __treg; })
#define mfhi1() ({ unsigned long __treg; __asm__ __volatile__( " .set push \n" " .set noat \n" " # mfhi %0, $ac1 \n" " .word 0x00200810 \n" " move %0, $1 \n" " .set pop \n" : "=r" (__treg)); __treg; })
#define mfhi2() ({ unsigned long __treg; __asm__ __volatile__( " .set push \n" " .set noat \n" " # mfhi %0, $ac2 \n" " .word 0x00400810 \n" " move %0, $1 \n" " .set pop \n" : "=r" (__treg)); __treg; })
#define mfhi3() ({ unsigned long __treg; __asm__ __volatile__( " .set push \n" " .set noat \n" " # mfhi %0, $ac3 \n" " .word 0x00600810 \n" " move %0, $1 \n" " .set pop \n" : "=r" (__treg)); __treg; })
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define mflo0() ({ unsigned long __treg; __asm__ __volatile__( " .set push \n" " .set noat \n" " # mflo %0, $ac0 \n" " .word 0x00000812 \n" " move %0, $1 \n" " .set pop \n" : "=r" (__treg)); __treg; })
#define mflo1() ({ unsigned long __treg; __asm__ __volatile__( " .set push \n" " .set noat \n" " # mflo %0, $ac1 \n" " .word 0x00200812 \n" " move %0, $1 \n" " .set pop \n" : "=r" (__treg)); __treg; })
#define mflo2() ({ unsigned long __treg; __asm__ __volatile__( " .set push \n" " .set noat \n" " # mflo %0, $ac2 \n" " .word 0x00400812 \n" " move %0, $1 \n" " .set pop \n" : "=r" (__treg)); __treg; })
#define mflo3() ({ unsigned long __treg; __asm__ __volatile__( " .set push \n" " .set noat \n" " # mflo %0, $ac3 \n" " .word 0x00600812 \n" " move %0, $1 \n" " .set pop \n" : "=r" (__treg)); __treg; })
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define mthi0(x) do { __asm__ __volatile__( " .set push \n" " .set noat \n" " move $1, %0 \n" " # mthi $1, $ac0 \n" " .word 0x00200011 \n" " .set pop \n" : : "r" (x)); } while (0)
#define mthi1(x) do { __asm__ __volatile__( " .set push \n" " .set noat \n" " move $1, %0 \n" " # mthi $1, $ac1 \n" " .word 0x00200811 \n" " .set pop \n" : : "r" (x)); } while (0)
#define mthi2(x) do { __asm__ __volatile__( " .set push \n" " .set noat \n" " move $1, %0 \n" " # mthi $1, $ac2 \n" " .word 0x00201011 \n" " .set pop \n" : : "r" (x)); } while (0)
#define mthi3(x) do { __asm__ __volatile__( " .set push \n" " .set noat \n" " move $1, %0 \n" " # mthi $1, $ac3 \n" " .word 0x00201811 \n" " .set pop \n" : : "r" (x)); } while (0)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define mtlo0(x) do { __asm__ __volatile__( " .set push \n" " .set noat \n" " move $1, %0 \n" " # mtlo $1, $ac0 \n" " .word 0x00200013 \n" " .set pop \n" : : "r" (x)); } while (0)
#define mtlo1(x) do { __asm__ __volatile__( " .set push \n" " .set noat \n" " move $1, %0 \n" " # mtlo $1, $ac1 \n" " .word 0x00200813 \n" " .set pop \n" : : "r" (x)); } while (0)
#define mtlo2(x) do { __asm__ __volatile__( " .set push \n" " .set noat \n" " move $1, %0 \n" " # mtlo $1, $ac2 \n" " .word 0x00201013 \n" " .set pop \n" : : "r" (x)); } while (0)
#define mtlo3(x) do { __asm__ __volatile__( " .set push \n" " .set noat \n" " move $1, %0 \n" " # mtlo $1, $ac3 \n" " .word 0x00201813 \n" " .set pop \n" : : "r" (x)); } while (0)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#if MIPS34K_MISSED_ITLB_WAR
#endif
#if MIPS34K_MISSED_ITLB_WAR
#endif
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define __BUILD_SET_C0(name) static inline unsigned int set_c0_##name(unsigned int set) { unsigned int res; res = read_c0_##name(); res |= set; write_c0_##name(res); return res; } static inline unsigned int clear_c0_##name(unsigned int clear) { unsigned int res; res = read_c0_##name(); res &= ~clear; write_c0_##name(res); return res; } static inline unsigned int change_c0_##name(unsigned int change, unsigned int new) { unsigned int res; res = read_c0_##name(); res &= ~change; res |= (new & change); write_c0_##name(res); return res; }
#endif
#endif

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libc/kernel/arch-mips/asm/mman.h Normal file
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/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef _ASM_MMAN_H
#define _ASM_MMAN_H
#define PROT_NONE 0x00
#define PROT_READ 0x01
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PROT_WRITE 0x02
#define PROT_EXEC 0x04
#define PROT_SEM 0x10
#define PROT_GROWSDOWN 0x01000000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PROT_GROWSUP 0x02000000
#define MAP_SHARED 0x001
#define MAP_PRIVATE 0x002
#define MAP_TYPE 0x00f
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MAP_FIXED 0x010
#define MAP_RENAME 0x020
#define MAP_AUTOGROW 0x040
#define MAP_LOCAL 0x080
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MAP_AUTORSRV 0x100
#define MAP_NORESERVE 0x0400
#define MAP_ANONYMOUS 0x0800
#define MAP_GROWSDOWN 0x1000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MAP_DENYWRITE 0x2000
#define MAP_EXECUTABLE 0x4000
#define MAP_LOCKED 0x8000
#define MAP_POPULATE 0x10000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MAP_NONBLOCK 0x20000
#define MS_ASYNC 0x0001
#define MS_INVALIDATE 0x0002
#define MS_SYNC 0x0004
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MCL_CURRENT 1
#define MCL_FUTURE 2
#define MADV_NORMAL 0
#define MADV_RANDOM 1
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MADV_SEQUENTIAL 2
#define MADV_WILLNEED 3
#define MADV_DONTNEED 4
#define MADV_REMOVE 9
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MADV_DONTFORK 10
#define MADV_DOFORK 11
#define MAP_FILE 0
#endif
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */

23
libc/kernel/arch-mips/asm/mmu.h Normal file
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/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef __ASM_MMU_H
#define __ASM_MMU_H
typedef unsigned long mm_context_t[NR_CPUS];
#endif
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */

24
libc/kernel/arch-mips/asm/mmzone.h Normal file
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/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef _ASM_MMZONE_H_
#define _ASM_MMZONE_H_
#include <asm/page.h>
#include <mmzone.h>
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#endif

56
libc/kernel/arch-mips/asm/module.h Normal file
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/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef _ASM_MODULE_H
#define _ASM_MODULE_H
#include <linux/list.h>
#include <asm/uaccess.h>
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
struct mod_arch_specific {
struct list_head dbe_list;
const struct exception_table_entry *dbe_start;
const struct exception_table_entry *dbe_end;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
};
typedef uint8_t Elf64_Byte;
typedef struct {
Elf64_Addr r_offset;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Elf64_Word r_sym;
Elf64_Byte r_ssym;
Elf64_Byte r_type3;
Elf64_Byte r_type2;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Elf64_Byte r_type;
} Elf64_Mips_Rel;
typedef struct {
Elf64_Addr r_offset;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Elf64_Word r_sym;
Elf64_Byte r_ssym;
Elf64_Byte r_type3;
Elf64_Byte r_type2;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Elf64_Byte r_type;
Elf64_Sxword r_addend;
} Elf64_Mips_Rela;
#error MODULE_PROC_FAMILY undefined for your processor configuration
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MODULE_KERNEL_SMTC ""
#define MODULE_ARCH_VERMAGIC MODULE_PROC_FAMILY MODULE_KERNEL_TYPE MODULE_KERNEL_SMTC
#endif

38
libc/kernel/arch-mips/asm/msgbuf.h Normal file
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/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef _ASM_MSGBUF_H
#define _ASM_MSGBUF_H
struct msqid64_ds {
struct ipc64_perm msg_perm;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
__kernel_time_t msg_stime;
__kernel_time_t msg_rtime;
__kernel_time_t msg_ctime;
unsigned long msg_cbytes;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
unsigned long msg_qnum;
unsigned long msg_qbytes;
__kernel_pid_t msg_lspid;
__kernel_pid_t msg_lrpid;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
unsigned long __unused4;
unsigned long __unused5;
};
#endif
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */

19
libc/kernel/arch-mips/asm/mutex.h Normal file
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/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#include <asm-generic/mutex-dec.h>

28
libc/kernel/arch-mips/asm/page.h Normal file
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/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef _ASM_PAGE_H
#define _ASM_PAGE_H
#ifndef PAGE_SHIFT
#define PAGE_SHIFT 12
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#endif
#define PAGE_SIZE (1UL << PAGE_SHIFT)
#define PAGE_MASK (~((1 << PAGE_SHIFT) - 1))
#endif
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */

30
libc/kernel/arch-mips/asm/param.h Normal file
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@ -0,0 +1,30 @@
/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef _ASM_PARAM_H
#define _ASM_PARAM_H
#ifndef HZ
#define HZ 100
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#endif
#define EXEC_PAGESIZE 65536
#ifndef NOGROUP
#define NOGROUP (-1)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#endif
#endif

676
libc/kernel/arch-mips/asm/pci/bridge.h Normal file
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/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef _ASM_PCI_BRIDGE_H
#define _ASM_PCI_BRIDGE_H
#include <linux/types.h>
#include <linux/pci.h>
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#include <asm/xtalk/xwidget.h>
#include <asm/sn/types.h>
#define IOPFNSHIFT 12
#define IOPGSIZE (1 << IOPFNSHIFT)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IOPG(x) ((x) >> IOPFNSHIFT)
#define IOPGOFF(x) ((x) & (IOPGSIZE-1))
#define BRIDGE_ATE_RAM_SIZE 0x00000400
#define BRIDGE_CONFIG_BASE 0x20000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BRIDGE_CONFIG1_BASE 0x28000
#define BRIDGE_CONFIG_END 0x30000
#define BRIDGE_CONFIG_SLOT_SIZE 0x1000
#define BRIDGE_SSRAM_512K 0x00080000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BRIDGE_SSRAM_128K 0x00020000
#define BRIDGE_SSRAM_64K 0x00010000
#define BRIDGE_SSRAM_0K 0x00000000
#ifndef __ASSEMBLY__
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
typedef u32 bridgereg_t;
typedef u64 bridge_ate_t;
typedef volatile bridge_ate_t *bridge_ate_p;
typedef volatile struct bridge_s {
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
widget_cfg_t b_widget;
#define b_wid_id b_widget.w_id
#define b_wid_stat b_widget.w_status
#define b_wid_err_upper b_widget.w_err_upper_addr
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define b_wid_err_lower b_widget.w_err_lower_addr
#define b_wid_control b_widget.w_control
#define b_wid_req_timeout b_widget.w_req_timeout
#define b_wid_int_upper b_widget.w_intdest_upper_addr
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define b_wid_int_lower b_widget.w_intdest_lower_addr
#define b_wid_err_cmdword b_widget.w_err_cmd_word
#define b_wid_llp b_widget.w_llp_cfg
#define b_wid_tflush b_widget.w_tflush
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
bridgereg_t _pad_000058;
bridgereg_t b_wid_aux_err;
bridgereg_t _pad_000060;
bridgereg_t b_wid_resp_upper;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
bridgereg_t _pad_000068;
bridgereg_t b_wid_resp_lower;
bridgereg_t _pad_000070;
bridgereg_t b_wid_tst_pin_ctrl;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
bridgereg_t _pad_000078[2];
bridgereg_t _pad_000080;
bridgereg_t b_dir_map;
bridgereg_t _pad_000088[2];
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
bridgereg_t _pad_000090;
bridgereg_t b_ram_perr;
bridgereg_t _pad_000098[2];
bridgereg_t _pad_0000A0;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
bridgereg_t b_arb;
bridgereg_t _pad_0000A8[2];
bridgereg_t _pad_0000B0;
bridgereg_t b_nic;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
bridgereg_t _pad_0000B8[2];
bridgereg_t _pad_0000C0;
bridgereg_t b_bus_timeout;
#define b_pci_bus_timeout b_bus_timeout
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
bridgereg_t _pad_0000C8;
bridgereg_t b_pci_cfg;
bridgereg_t _pad_0000D0;
bridgereg_t b_pci_err_upper;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
bridgereg_t _pad_0000D8;
bridgereg_t b_pci_err_lower;
bridgereg_t _pad_0000E0[8];
#define b_gio_err_lower b_pci_err_lower
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define b_gio_err_upper b_pci_err_upper
bridgereg_t _pad_000100;
bridgereg_t b_int_status;
bridgereg_t _pad_000108;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
bridgereg_t b_int_enable;
bridgereg_t _pad_000110;
bridgereg_t b_int_rst_stat;
bridgereg_t _pad_000118;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
bridgereg_t b_int_mode;
bridgereg_t _pad_000120;
bridgereg_t b_int_device;
bridgereg_t _pad_000128;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
bridgereg_t b_int_host_err;
struct {
bridgereg_t __pad;
bridgereg_t addr;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
} b_int_addr[8];
bridgereg_t _pad_000170[36];
struct {
bridgereg_t __pad;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
bridgereg_t reg;
} b_device[8];
struct {
bridgereg_t __pad;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
bridgereg_t reg;
} b_wr_req_buf[8];
struct {
bridgereg_t __pad;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
bridgereg_t reg;
} b_rrb_map[2];
#define b_even_resp b_rrb_map[0].reg
#define b_odd_resp b_rrb_map[1].reg
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
bridgereg_t _pad_000290;
bridgereg_t b_resp_status;
bridgereg_t _pad_000298;
bridgereg_t b_resp_clear;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
bridgereg_t _pad_0002A0[24];
char _pad_000300[0x10000 - 0x000300];
union {
bridge_ate_t wr;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
struct {
bridgereg_t _p_pad;
bridgereg_t rd;
} hi;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
} b_int_ate_ram[128];
char _pad_010400[0x11000 - 0x010400];
struct {
bridgereg_t _p_pad;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
bridgereg_t rd;
} b_int_ate_ram_lo[128];
char _pad_011400[0x20000 - 0x011400];
union {
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
u8 c[0x1000 / 1];
u16 s[0x1000 / 2];
u32 l[0x1000 / 4];
u64 d[0x1000 / 8];
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
union {
u8 c[0x100 / 1];
u16 s[0x100 / 2];
u32 l[0x100 / 4];
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
u64 d[0x100 / 8];
} f[8];
} b_type0_cfg_dev[8];
union {
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
u8 c[0x1000 / 1];
u16 s[0x1000 / 2];
u32 l[0x1000 / 4];
u64 d[0x1000 / 8];
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
} b_type1_cfg;
char _pad_029000[0x007000];
union {
u8 c[8 / 1];
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
u16 s[8 / 2];
u32 l[8 / 4];
u64 d[8 / 8];
} b_pci_iack;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
u8 _pad_030007[0x04fff8];
bridge_ate_t b_ext_ate_ram[0x10000];
char _pad_100000[0x200000-0x100000];
union {
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
u8 c[0x100000 / 1];
u16 s[0x100000 / 2];
u32 l[0x100000 / 4];
u64 d[0x100000 / 8];
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
} b_devio_raw[10];
#define b_devio(n) b_devio_raw[((n)<2)?(n*2):(n+2)]
union {
u8 c[0x400000 / 1];
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
u16 s[0x400000 / 2];
u32 l[0x400000 / 4];
u64 d[0x400000 / 8];
} b_external_flash;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
} bridge_t;
typedef struct bridge_err_cmdword_s {
union {
u32 cmd_word;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
struct {
u32 didn:4,
sidn:4,
pactyp:4,
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
tnum:5,
coh:1,
ds:2,
gbr:1,
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
vbpm:1,
error:1,
barr:1,
rsvd:8;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
} berr_st;
} berr_un;
} bridge_err_cmdword_t;
#define berr_field berr_un.berr_st
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#endif
#define BRIDGE_WID_ID WIDGET_ID
#define BRIDGE_WID_STAT WIDGET_STATUS
#define BRIDGE_WID_ERR_UPPER WIDGET_ERR_UPPER_ADDR
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BRIDGE_WID_ERR_LOWER WIDGET_ERR_LOWER_ADDR
#define BRIDGE_WID_CONTROL WIDGET_CONTROL
#define BRIDGE_WID_REQ_TIMEOUT WIDGET_REQ_TIMEOUT
#define BRIDGE_WID_INT_UPPER WIDGET_INTDEST_UPPER_ADDR
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BRIDGE_WID_INT_LOWER WIDGET_INTDEST_LOWER_ADDR
#define BRIDGE_WID_ERR_CMDWORD WIDGET_ERR_CMD_WORD
#define BRIDGE_WID_LLP WIDGET_LLP_CFG
#define BRIDGE_WID_TFLUSH WIDGET_TFLUSH
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BRIDGE_WID_AUX_ERR 0x00005C
#define BRIDGE_WID_RESP_UPPER 0x000064
#define BRIDGE_WID_RESP_LOWER 0x00006C
#define BRIDGE_WID_TST_PIN_CTRL 0x000074
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BRIDGE_DIR_MAP 0x000084
#define BRIDGE_RAM_PERR 0x000094
#define BRIDGE_ARB 0x0000A4
#define BRIDGE_NIC 0x0000B4
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BRIDGE_BUS_TIMEOUT 0x0000C4
#define BRIDGE_PCI_BUS_TIMEOUT BRIDGE_BUS_TIMEOUT
#define BRIDGE_PCI_CFG 0x0000CC
#define BRIDGE_PCI_ERR_UPPER 0x0000D4
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BRIDGE_PCI_ERR_LOWER 0x0000DC
#define BRIDGE_INT_STATUS 0x000104
#define BRIDGE_INT_ENABLE 0x00010C
#define BRIDGE_INT_RST_STAT 0x000114
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BRIDGE_INT_MODE 0x00011C
#define BRIDGE_INT_DEVICE 0x000124
#define BRIDGE_INT_HOST_ERR 0x00012C
#define BRIDGE_INT_ADDR0 0x000134
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BRIDGE_INT_ADDR_OFF 0x000008
#define BRIDGE_INT_ADDR(x) (BRIDGE_INT_ADDR0+(x)*BRIDGE_INT_ADDR_OFF)
#define BRIDGE_DEVICE0 0x000204
#define BRIDGE_DEVICE_OFF 0x000008
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BRIDGE_DEVICE(x) (BRIDGE_DEVICE0+(x)*BRIDGE_DEVICE_OFF)
#define BRIDGE_WR_REQ_BUF0 0x000244
#define BRIDGE_WR_REQ_BUF_OFF 0x000008
#define BRIDGE_WR_REQ_BUF(x) (BRIDGE_WR_REQ_BUF0+(x)*BRIDGE_WR_REQ_BUF_OFF)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BRIDGE_EVEN_RESP 0x000284
#define BRIDGE_ODD_RESP 0x00028C
#define BRIDGE_RESP_STATUS 0x000294
#define BRIDGE_RESP_CLEAR 0x00029C
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BRIDGE_ATE_RAM 0x00010000
#define BRIDGE_TYPE0_CFG_DEV0 0x00020000
#define BRIDGE_TYPE0_CFG_SLOT_OFF 0x00001000
#define BRIDGE_TYPE0_CFG_FUNC_OFF 0x00000100
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BRIDGE_TYPE0_CFG_DEV(s) (BRIDGE_TYPE0_CFG_DEV0+ (s)*BRIDGE_TYPE0_CFG_SLOT_OFF)
#define BRIDGE_TYPE0_CFG_DEVF(s, f) (BRIDGE_TYPE0_CFG_DEV0+ (s)*BRIDGE_TYPE0_CFG_SLOT_OFF+ (f)*BRIDGE_TYPE0_CFG_FUNC_OFF)
#define BRIDGE_TYPE1_CFG 0x00028000
#define BRIDGE_PCI_IACK 0x00030000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BRIDGE_EXT_SSRAM 0x00080000
#define BRIDGE_DEV_CNT 8
#define BRIDGE_DEVIO0 0x00200000
#define BRIDGE_DEVIO1 0x00400000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BRIDGE_DEVIO2 0x00600000
#define BRIDGE_DEVIO_OFF 0x00100000
#define BRIDGE_DEVIO_2MB 0x00200000
#define BRIDGE_DEVIO_1MB 0x00100000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BRIDGE_DEVIO(x) ((x)<=1 ? BRIDGE_DEVIO0+(x)*BRIDGE_DEVIO_2MB : BRIDGE_DEVIO2+((x)-2)*BRIDGE_DEVIO_1MB)
#define BRIDGE_EXTERNAL_FLASH 0x00C00000
#define BRIDGE_WIDGET_PART_NUM 0xc002
#define XBRIDGE_WIDGET_PART_NUM 0xd002
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BRIDGE_WIDGET_MFGR_NUM 0x036
#define XBRIDGE_WIDGET_MFGR_NUM 0x024
#define BRIDGE_REV_A 0x1
#define BRIDGE_REV_B 0x2
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BRIDGE_REV_C 0x3
#define BRIDGE_REV_D 0x4
#define BRIDGE_STAT_LLP_REC_CNT (0xFFu << 24)
#define BRIDGE_STAT_LLP_TX_CNT (0xFF << 16)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BRIDGE_STAT_FLASH_SELECT (0x1 << 6)
#define BRIDGE_STAT_PCI_GIO_N (0x1 << 5)
#define BRIDGE_STAT_PENDING (0x1F << 0)
#define BRIDGE_CTRL_FLASH_WR_EN (0x1ul << 31)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BRIDGE_CTRL_EN_CLK50 (0x1 << 30)
#define BRIDGE_CTRL_EN_CLK40 (0x1 << 29)
#define BRIDGE_CTRL_EN_CLK33 (0x1 << 28)
#define BRIDGE_CTRL_RST(n) ((n) << 24)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BRIDGE_CTRL_RST_MASK (BRIDGE_CTRL_RST(0xF))
#define BRIDGE_CTRL_RST_PIN(x) (BRIDGE_CTRL_RST(0x1 << (x)))
#define BRIDGE_CTRL_IO_SWAP (0x1 << 23)
#define BRIDGE_CTRL_MEM_SWAP (0x1 << 22)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BRIDGE_CTRL_PAGE_SIZE (0x1 << 21)
#define BRIDGE_CTRL_SS_PAR_BAD (0x1 << 20)
#define BRIDGE_CTRL_SS_PAR_EN (0x1 << 19)
#define BRIDGE_CTRL_SSRAM_SIZE(n) ((n) << 17)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BRIDGE_CTRL_SSRAM_SIZE_MASK (BRIDGE_CTRL_SSRAM_SIZE(0x3))
#define BRIDGE_CTRL_SSRAM_512K (BRIDGE_CTRL_SSRAM_SIZE(0x3))
#define BRIDGE_CTRL_SSRAM_128K (BRIDGE_CTRL_SSRAM_SIZE(0x2))
#define BRIDGE_CTRL_SSRAM_64K (BRIDGE_CTRL_SSRAM_SIZE(0x1))
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BRIDGE_CTRL_SSRAM_1K (BRIDGE_CTRL_SSRAM_SIZE(0x0))
#define BRIDGE_CTRL_F_BAD_PKT (0x1 << 16)
#define BRIDGE_CTRL_LLP_XBAR_CRD(n) ((n) << 12)
#define BRIDGE_CTRL_LLP_XBAR_CRD_MASK (BRIDGE_CTRL_LLP_XBAR_CRD(0xf))
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BRIDGE_CTRL_CLR_RLLP_CNT (0x1 << 11)
#define BRIDGE_CTRL_CLR_TLLP_CNT (0x1 << 10)
#define BRIDGE_CTRL_SYS_END (0x1 << 9)
#define BRIDGE_CTRL_MAX_TRANS(n) ((n) << 4)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BRIDGE_CTRL_MAX_TRANS_MASK (BRIDGE_CTRL_MAX_TRANS(0x1f))
#define BRIDGE_CTRL_WIDGET_ID(n) ((n) << 0)
#define BRIDGE_CTRL_WIDGET_ID_MASK (BRIDGE_CTRL_WIDGET_ID(0xf))
#define BRIDGE_RESP_ERRUPPR_DEVNUM_SHFT (20)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BRIDGE_RESP_ERRUPPR_DEVNUM_MASK (0x7 << BRIDGE_RESP_ERRUPPR_DEVNUM_SHFT)
#define BRIDGE_RESP_ERRUPPR_BUFNUM_SHFT (16)
#define BRIDGE_RESP_ERRUPPR_BUFNUM_MASK (0xF << BRIDGE_RESP_ERRUPPR_BUFNUM_SHFT)
#define BRIDGE_RESP_ERRRUPPR_BUFMASK (0xFFFF)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BRIDGE_RESP_ERRUPPR_BUFNUM(x) (((x) & BRIDGE_RESP_ERRUPPR_BUFNUM_MASK) >> BRIDGE_RESP_ERRUPPR_BUFNUM_SHFT)
#define BRIDGE_RESP_ERRUPPR_DEVICE(x) (((x) & BRIDGE_RESP_ERRUPPR_DEVNUM_MASK) >> BRIDGE_RESP_ERRUPPR_DEVNUM_SHFT)
#define BRIDGE_DIRMAP_W_ID_SHFT 20
#define BRIDGE_DIRMAP_W_ID (0xf << BRIDGE_DIRMAP_W_ID_SHFT)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BRIDGE_DIRMAP_RMF_64 (0x1 << 18)
#define BRIDGE_DIRMAP_ADD512 (0x1 << 17)
#define BRIDGE_DIRMAP_OFF (0x1ffff << 0)
#define BRIDGE_DIRMAP_OFF_ADDRSHFT (31)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BRIDGE_ARB_REQ_WAIT_TICK(x) ((x) << 16)
#define BRIDGE_ARB_REQ_WAIT_TICK_MASK BRIDGE_ARB_REQ_WAIT_TICK(0x3)
#define BRIDGE_ARB_REQ_WAIT_EN(x) ((x) << 8)
#define BRIDGE_ARB_REQ_WAIT_EN_MASK BRIDGE_ARB_REQ_WAIT_EN(0xff)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BRIDGE_ARB_FREEZE_GNT (1 << 6)
#define BRIDGE_ARB_HPRI_RING_B2 (1 << 5)
#define BRIDGE_ARB_HPRI_RING_B1 (1 << 4)
#define BRIDGE_ARB_HPRI_RING_B0 (1 << 3)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BRIDGE_ARB_LPRI_RING_B2 (1 << 2)
#define BRIDGE_ARB_LPRI_RING_B1 (1 << 1)
#define BRIDGE_ARB_LPRI_RING_B0 (1 << 0)
#define BRIDGE_BUS_PCI_RETRY_HLD(x) ((x) << 16)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BRIDGE_BUS_PCI_RETRY_HLD_MASK BRIDGE_BUS_PCI_RETRY_HLD(0x1f)
#define BRIDGE_BUS_GIO_TIMEOUT (1 << 12)
#define BRIDGE_BUS_PCI_RETRY_CNT(x) ((x) << 0)
#define BRIDGE_BUS_PCI_RETRY_MASK BRIDGE_BUS_PCI_RETRY_CNT(0x3ff)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BRIDGE_ISR_MULTI_ERR (0x1u << 31)
#define BRIDGE_ISR_PMU_ESIZE_FAULT (0x1 << 30)
#define BRIDGE_ISR_UNEXP_RESP (0x1 << 29)
#define BRIDGE_ISR_BAD_XRESP_PKT (0x1 << 28)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BRIDGE_ISR_BAD_XREQ_PKT (0x1 << 27)
#define BRIDGE_ISR_RESP_XTLK_ERR (0x1 << 26)
#define BRIDGE_ISR_REQ_XTLK_ERR (0x1 << 25)
#define BRIDGE_ISR_INVLD_ADDR (0x1 << 24)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BRIDGE_ISR_UNSUPPORTED_XOP (0x1 << 23)
#define BRIDGE_ISR_XREQ_FIFO_OFLOW (0x1 << 22)
#define BRIDGE_ISR_LLP_REC_SNERR (0x1 << 21)
#define BRIDGE_ISR_LLP_REC_CBERR (0x1 << 20)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BRIDGE_ISR_LLP_RCTY (0x1 << 19)
#define BRIDGE_ISR_LLP_TX_RETRY (0x1 << 18)
#define BRIDGE_ISR_LLP_TCTY (0x1 << 17)
#define BRIDGE_ISR_SSRAM_PERR (0x1 << 16)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BRIDGE_ISR_PCI_ABORT (0x1 << 15)
#define BRIDGE_ISR_PCI_PARITY (0x1 << 14)
#define BRIDGE_ISR_PCI_SERR (0x1 << 13)
#define BRIDGE_ISR_PCI_PERR (0x1 << 12)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BRIDGE_ISR_PCI_MST_TIMEOUT (0x1 << 11)
#define BRIDGE_ISR_GIO_MST_TIMEOUT BRIDGE_ISR_PCI_MST_TIMEOUT
#define BRIDGE_ISR_PCI_RETRY_CNT (0x1 << 10)
#define BRIDGE_ISR_XREAD_REQ_TIMEOUT (0x1 << 9)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BRIDGE_ISR_GIO_B_ENBL_ERR (0x1 << 8)
#define BRIDGE_ISR_INT_MSK (0xff << 0)
#define BRIDGE_ISR_INT(x) (0x1 << (x))
#define BRIDGE_ISR_LINK_ERROR (BRIDGE_ISR_LLP_REC_SNERR|BRIDGE_ISR_LLP_REC_CBERR| BRIDGE_ISR_LLP_RCTY|BRIDGE_ISR_LLP_TX_RETRY| BRIDGE_ISR_LLP_TCTY)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BRIDGE_ISR_PCIBUS_PIOERR (BRIDGE_ISR_PCI_MST_TIMEOUT|BRIDGE_ISR_PCI_ABORT)
#define BRIDGE_ISR_PCIBUS_ERROR (BRIDGE_ISR_PCIBUS_PIOERR|BRIDGE_ISR_PCI_PERR| BRIDGE_ISR_PCI_SERR|BRIDGE_ISR_PCI_RETRY_CNT| BRIDGE_ISR_PCI_PARITY)
#define BRIDGE_ISR_XTALK_ERROR (BRIDGE_ISR_XREAD_REQ_TIMEOUT|BRIDGE_ISR_XREQ_FIFO_OFLOW| BRIDGE_ISR_UNSUPPORTED_XOP|BRIDGE_ISR_INVLD_ADDR| BRIDGE_ISR_REQ_XTLK_ERR|BRIDGE_ISR_RESP_XTLK_ERR| BRIDGE_ISR_BAD_XREQ_PKT|BRIDGE_ISR_BAD_XRESP_PKT| BRIDGE_ISR_UNEXP_RESP)
#define BRIDGE_ISR_ERRORS (BRIDGE_ISR_LINK_ERROR|BRIDGE_ISR_PCIBUS_ERROR| BRIDGE_ISR_XTALK_ERROR|BRIDGE_ISR_SSRAM_PERR| BRIDGE_ISR_PMU_ESIZE_FAULT)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BRIDGE_ISR_ERROR_FATAL ((BRIDGE_ISR_XTALK_ERROR & ~BRIDGE_ISR_XREAD_REQ_TIMEOUT)| BRIDGE_ISR_PCI_SERR|BRIDGE_ISR_PCI_PARITY )
#define BRIDGE_ISR_ERROR_DUMP (BRIDGE_ISR_PCIBUS_ERROR|BRIDGE_ISR_PMU_ESIZE_FAULT| BRIDGE_ISR_XTALK_ERROR|BRIDGE_ISR_SSRAM_PERR)
#define BRIDGE_IMR_UNEXP_RESP BRIDGE_ISR_UNEXP_RESP
#define BRIDGE_IMR_PMU_ESIZE_FAULT BRIDGE_ISR_PMU_ESIZE_FAULT
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BRIDGE_IMR_BAD_XRESP_PKT BRIDGE_ISR_BAD_XRESP_PKT
#define BRIDGE_IMR_BAD_XREQ_PKT BRIDGE_ISR_BAD_XREQ_PKT
#define BRIDGE_IMR_RESP_XTLK_ERR BRIDGE_ISR_RESP_XTLK_ERR
#define BRIDGE_IMR_REQ_XTLK_ERR BRIDGE_ISR_REQ_XTLK_ERR
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BRIDGE_IMR_INVLD_ADDR BRIDGE_ISR_INVLD_ADDR
#define BRIDGE_IMR_UNSUPPORTED_XOP BRIDGE_ISR_UNSUPPORTED_XOP
#define BRIDGE_IMR_XREQ_FIFO_OFLOW BRIDGE_ISR_XREQ_FIFO_OFLOW
#define BRIDGE_IMR_LLP_REC_SNERR BRIDGE_ISR_LLP_REC_SNERR
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BRIDGE_IMR_LLP_REC_CBERR BRIDGE_ISR_LLP_REC_CBERR
#define BRIDGE_IMR_LLP_RCTY BRIDGE_ISR_LLP_RCTY
#define BRIDGE_IMR_LLP_TX_RETRY BRIDGE_ISR_LLP_TX_RETRY
#define BRIDGE_IMR_LLP_TCTY BRIDGE_ISR_LLP_TCTY
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BRIDGE_IMR_SSRAM_PERR BRIDGE_ISR_SSRAM_PERR
#define BRIDGE_IMR_PCI_ABORT BRIDGE_ISR_PCI_ABORT
#define BRIDGE_IMR_PCI_PARITY BRIDGE_ISR_PCI_PARITY
#define BRIDGE_IMR_PCI_SERR BRIDGE_ISR_PCI_SERR
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BRIDGE_IMR_PCI_PERR BRIDGE_ISR_PCI_PERR
#define BRIDGE_IMR_PCI_MST_TIMEOUT BRIDGE_ISR_PCI_MST_TIMEOUT
#define BRIDGE_IMR_GIO_MST_TIMEOUT BRIDGE_ISR_GIO_MST_TIMEOUT
#define BRIDGE_IMR_PCI_RETRY_CNT BRIDGE_ISR_PCI_RETRY_CNT
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BRIDGE_IMR_XREAD_REQ_TIMEOUT BRIDGE_ISR_XREAD_REQ_TIMEOUT
#define BRIDGE_IMR_GIO_B_ENBL_ERR BRIDGE_ISR_GIO_B_ENBL_ERR
#define BRIDGE_IMR_INT_MSK BRIDGE_ISR_INT_MSK
#define BRIDGE_IMR_INT(x) BRIDGE_ISR_INT(x)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BRIDGE_IRR_MULTI_CLR (0x1 << 6)
#define BRIDGE_IRR_CRP_GRP_CLR (0x1 << 5)
#define BRIDGE_IRR_RESP_BUF_GRP_CLR (0x1 << 4)
#define BRIDGE_IRR_REQ_DSP_GRP_CLR (0x1 << 3)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BRIDGE_IRR_LLP_GRP_CLR (0x1 << 2)
#define BRIDGE_IRR_SSRAM_GRP_CLR (0x1 << 1)
#define BRIDGE_IRR_PCI_GRP_CLR (0x1 << 0)
#define BRIDGE_IRR_GIO_GRP_CLR (0x1 << 0)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BRIDGE_IRR_ALL_CLR 0x7f
#define BRIDGE_IRR_CRP_GRP (BRIDGE_ISR_UNEXP_RESP | BRIDGE_ISR_XREQ_FIFO_OFLOW)
#define BRIDGE_IRR_RESP_BUF_GRP (BRIDGE_ISR_BAD_XRESP_PKT | BRIDGE_ISR_RESP_XTLK_ERR | BRIDGE_ISR_XREAD_REQ_TIMEOUT)
#define BRIDGE_IRR_REQ_DSP_GRP (BRIDGE_ISR_UNSUPPORTED_XOP | BRIDGE_ISR_BAD_XREQ_PKT | BRIDGE_ISR_REQ_XTLK_ERR | BRIDGE_ISR_INVLD_ADDR)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BRIDGE_IRR_LLP_GRP (BRIDGE_ISR_LLP_REC_SNERR | BRIDGE_ISR_LLP_REC_CBERR | BRIDGE_ISR_LLP_RCTY | BRIDGE_ISR_LLP_TX_RETRY | BRIDGE_ISR_LLP_TCTY)
#define BRIDGE_IRR_SSRAM_GRP (BRIDGE_ISR_SSRAM_PERR | BRIDGE_ISR_PMU_ESIZE_FAULT)
#define BRIDGE_IRR_PCI_GRP (BRIDGE_ISR_PCI_ABORT | BRIDGE_ISR_PCI_PARITY | BRIDGE_ISR_PCI_SERR | BRIDGE_ISR_PCI_PERR | BRIDGE_ISR_PCI_MST_TIMEOUT | BRIDGE_ISR_PCI_RETRY_CNT)
#define BRIDGE_IRR_GIO_GRP (BRIDGE_ISR_GIO_B_ENBL_ERR | BRIDGE_ISR_GIO_MST_TIMEOUT)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BRIDGE_INT_DEV_SHFT(n) ((n)*3)
#define BRIDGE_INT_DEV_MASK(n) (0x7 << BRIDGE_INT_DEV_SHFT(n))
#define BRIDGE_INT_DEV_SET(_dev, _line) (_dev << BRIDGE_INT_DEV_SHFT(_line))
#define BRIDGE_INT_ADDR_HOST 0x0003FF00
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BRIDGE_INT_ADDR_FLD 0x000000FF
#define BRIDGE_TMO_PCI_RETRY_HLD_MASK 0x1f0000
#define BRIDGE_TMO_GIO_TIMEOUT_MASK 0x001000
#define BRIDGE_TMO_PCI_RETRY_CNT_MASK 0x0003ff
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BRIDGE_TMO_PCI_RETRY_CNT_MAX 0x3ff
#define BRIDGE_INT_ADDR_NASID_SHFT 8
#define BRIDGE_INT_ADDR_DEST_IO (1 << 17)
#define BRIDGE_INT_ADDR_DEST_MEM 0
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BRIDGE_INT_ADDR_MASK (1 << 17)
#define BRIDGE_DEV_ERR_LOCK_EN 0x10000000
#define BRIDGE_DEV_PAGE_CHK_DIS 0x08000000
#define BRIDGE_DEV_FORCE_PCI_PAR 0x04000000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BRIDGE_DEV_VIRTUAL_EN 0x02000000
#define BRIDGE_DEV_PMU_WRGA_EN 0x01000000
#define BRIDGE_DEV_DIR_WRGA_EN 0x00800000
#define BRIDGE_DEV_DEV_SIZE 0x00400000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BRIDGE_DEV_RT 0x00200000
#define BRIDGE_DEV_SWAP_PMU 0x00100000
#define BRIDGE_DEV_SWAP_DIR 0x00080000
#define BRIDGE_DEV_PREF 0x00040000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BRIDGE_DEV_PRECISE 0x00020000
#define BRIDGE_DEV_COH 0x00010000
#define BRIDGE_DEV_BARRIER 0x00008000
#define BRIDGE_DEV_GBR 0x00004000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BRIDGE_DEV_DEV_SWAP 0x00002000
#define BRIDGE_DEV_DEV_IO_MEM 0x00001000
#define BRIDGE_DEV_OFF_MASK 0x00000fff
#define BRIDGE_DEV_OFF_ADDR_SHFT 20
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BRIDGE_DEV_PMU_BITS (BRIDGE_DEV_PMU_WRGA_EN | BRIDGE_DEV_SWAP_PMU)
#define BRIDGE_DEV_D32_BITS (BRIDGE_DEV_DIR_WRGA_EN | BRIDGE_DEV_SWAP_DIR | BRIDGE_DEV_PREF | BRIDGE_DEV_PRECISE | BRIDGE_DEV_COH | BRIDGE_DEV_BARRIER)
#define BRIDGE_DEV_D64_BITS (BRIDGE_DEV_DIR_WRGA_EN | BRIDGE_DEV_SWAP_DIR | BRIDGE_DEV_COH | BRIDGE_DEV_BARRIER)
#define BRIDGE_ERRUPPR_DEVMASTER (0x1 << 20)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BRIDGE_ERRUPPR_PCIVDEV (0x1 << 19)
#define BRIDGE_ERRUPPR_DEVNUM_SHFT (16)
#define BRIDGE_ERRUPPR_DEVNUM_MASK (0x7 << BRIDGE_ERRUPPR_DEVNUM_SHFT)
#define BRIDGE_ERRUPPR_DEVICE(err) (((err) >> BRIDGE_ERRUPPR_DEVNUM_SHFT) & 0x7)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BRIDGE_ERRUPPR_ADDRMASK (0xFFFF)
#define BRIDGE_INTMODE_CLR_PKT_EN(x) (0x1 << (x))
#define BRIDGE_CREDIT 3
#define BRIDGE_RRB_EN 0x8
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BRIDGE_RRB_DEV 0x7
#define BRIDGE_RRB_VDEV 0x4
#define BRIDGE_RRB_PDEV 0x3
#define BRIDGE_RRB_VALID(r) (0x00010000<<(r))
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BRIDGE_RRB_INUSE(r) (0x00000001<<(r))
#define BRIDGE_RRB_CLEAR(r) (0x00000001<<(r))
#define XBOX_BRIDGE_WID 8
#define FLASH_PROM1_BASE 0xE00000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define XBOX_RPS_EXISTS 1 << 6
#define XBOX_RPS_FAIL 1 << 4
#define BRIDGE_PIO32_XTALK_ALIAS_BASE 0x000040000000L
#define BRIDGE_PIO32_XTALK_ALIAS_LIMIT 0x00007FFFFFFFL
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BRIDGE_PIO64_XTALK_ALIAS_BASE 0x000080000000L
#define BRIDGE_PIO64_XTALK_ALIAS_LIMIT 0x0000BFFFFFFFL
#define BRIDGE_PCIIO_XTALK_ALIAS_BASE 0x000100000000L
#define BRIDGE_PCIIO_XTALK_ALIAS_LIMIT 0x0001FFFFFFFFL
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BRIDGE_MIN_PIO_ADDR_MEM 0x00000000
#define BRIDGE_MAX_PIO_ADDR_MEM 0x3fffffff
#define BRIDGE_MIN_PIO_ADDR_IO 0x00000000
#define BRIDGE_MAX_PIO_ADDR_IO 0xffffffff
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BRIDGE_PCI_MEM32_BASE BRIDGE_PIO32_XTALK_ALIAS_BASE
#define BRIDGE_PCI_MEM32_LIMIT BRIDGE_PIO32_XTALK_ALIAS_LIMIT
#define BRIDGE_PCI_MEM64_BASE BRIDGE_PIO64_XTALK_ALIAS_BASE
#define BRIDGE_PCI_MEM64_LIMIT BRIDGE_PIO64_XTALK_ALIAS_LIMIT
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BRIDGE_PCI_IO_BASE BRIDGE_PCIIO_XTALK_ALIAS_BASE
#define BRIDGE_PCI_IO_LIMIT BRIDGE_PCIIO_XTALK_ALIAS_LIMIT
#define BRIDGE_LOCAL_BASE 0
#define BRIDGE_DMA_MAPPED_BASE 0x40000000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BRIDGE_DMA_MAPPED_SIZE 0x40000000
#define BRIDGE_DMA_DIRECT_BASE 0x80000000
#define BRIDGE_DMA_DIRECT_SIZE 0x80000000
#define PCI32_LOCAL_BASE BRIDGE_LOCAL_BASE
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PCI32_MAPPED_BASE BRIDGE_DMA_MAPPED_BASE
#define PCI32_DIRECT_BASE BRIDGE_DMA_DIRECT_BASE
#define IS_PCI32_LOCAL(x) ((ulong_t)(x) < PCI32_MAPPED_BASE)
#define IS_PCI32_MAPPED(x) ((ulong_t)(x) < PCI32_DIRECT_BASE && (ulong_t)(x) >= PCI32_MAPPED_BASE)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IS_PCI32_DIRECT(x) ((ulong_t)(x) >= PCI32_MAPPED_BASE)
#define IS_PCI64(x) ((ulong_t)(x) >= PCI64_BASE)
#define BRIDGE_GIO_MEM32_BASE BRIDGE_PIO32_XTALK_ALIAS_BASE
#define BRIDGE_GIO_MEM32_LIMIT BRIDGE_PIO32_XTALK_ALIAS_LIMIT
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define GIO_LOCAL_BASE BRIDGE_LOCAL_BASE
#define GIO_MAPPED_BASE BRIDGE_DMA_MAPPED_BASE
#define GIO_DIRECT_BASE BRIDGE_DMA_DIRECT_BASE
#define IS_GIO_LOCAL(x) ((ulong_t)(x) < GIO_MAPPED_BASE)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IS_GIO_MAPPED(x) ((ulong_t)(x) < GIO_DIRECT_BASE && (ulong_t)(x) >= GIO_MAPPED_BASE)
#define IS_GIO_DIRECT(x) ((ulong_t)(x) >= GIO_MAPPED_BASE)
#define BRIDGE_DIRECT_32_SEG_SIZE BRIDGE_DMA_DIRECT_SIZE
#define BRIDGE_DIRECT_32_TO_XTALK(dir_off,adr) ((dir_off) * BRIDGE_DIRECT_32_SEG_SIZE + ((adr) & (BRIDGE_DIRECT_32_SEG_SIZE - 1)) + PHYS_RAMBASE)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PCI64_ATTR_TARG_MASK 0xf000000000000000
#define PCI64_ATTR_TARG_SHFT 60
#define PCI64_ATTR_PREF 0x0800000000000000
#define PCI64_ATTR_PREC 0x0400000000000000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PCI64_ATTR_VIRTUAL 0x0200000000000000
#define PCI64_ATTR_BAR 0x0100000000000000
#define PCI64_ATTR_RMF_MASK 0x00ff000000000000
#define PCI64_ATTR_RMF_SHFT 48
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#ifndef __ASSEMBLY__
typedef union ate_u {
u64 ent;
struct ate_s {
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
u64 rmf:16;
u64 addr:36;
u64 targ:4;
u64 reserved:3;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
u64 barrier:1;
u64 prefetch:1;
u64 precise:1;
u64 coherent:1;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
u64 valid:1;
} field;
} ate_t;
#endif
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define ATE_V 0x01
#define ATE_CO 0x02
#define ATE_PREC 0x04
#define ATE_PREF 0x08
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define ATE_BAR 0x10
#define ATE_PFNSHIFT 12
#define ATE_TIDSHIFT 8
#define ATE_RMFSHIFT 48
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define mkate(xaddr, xid, attr) ((xaddr) & 0x0000fffffffff000ULL) | ((xid)<<ATE_TIDSHIFT) | (attr)
#define BRIDGE_INTERNAL_ATES 128
struct bridge_controller {
struct pci_controller pc;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
struct resource mem;
struct resource io;
bridge_t *base;
nasid_t nasid;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
unsigned int widget_id;
unsigned int irq_cpu;
dma64_addr_t baddr;
unsigned int pci_int[8];
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
};
#define BRIDGE_CONTROLLER(bus) ((struct bridge_controller *)((bus)->sysdata))
#endif

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libc/kernel/arch-mips/asm/percpu.h Normal file
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/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef __ASM_PERCPU_H
#define __ASM_PERCPU_H
#include <asm-generic/percpu.h>
#endif
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */

29
libc/kernel/arch-mips/asm/pgalloc.h Normal file
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/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef _ASM_PGALLOC_H
#define _ASM_PGALLOC_H
#include <linux/highmem.h>
#include <linux/mm.h>
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#include <linux/sched.h>
#define pmd_pgtable(pmd) pmd_page(pmd)
#define __pte_free_tlb(tlb,pte) do { pgtable_page_dtor(pte); tlb_remove_page((tlb), pte); } while (0)
#define check_pgt_cache() do { } while (0)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#endif

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libc/kernel/arch-mips/asm/pgtable-bits.h Normal file
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/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef _ASM_PGTABLE_BITS_H
#define _ASM_PGTABLE_BITS_H
#define _PAGE_PRESENT (1<<0)
#define _PAGE_READ (1<<1)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define _PAGE_WRITE (1<<2)
#define _PAGE_ACCESSED (1<<3)
#define _PAGE_MODIFIED (1<<4)
#define _PAGE_FILE (1<<4)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define _PAGE_R4KBUG (1<<5)
#define _PAGE_GLOBAL (1<<6)
#define _PAGE_VALID (1<<7)
#define _PAGE_SILENT_READ (1<<7)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define _PAGE_DIRTY (1<<8)
#define _PAGE_SILENT_WRITE (1<<8)
#define _CACHE_SHIFT 9
#define _CACHE_MASK (7<<9)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define _CACHE_CACHABLE_NO_WA (0<<_CACHE_SHIFT)
#define _CACHE_CACHABLE_WA (1<<_CACHE_SHIFT)
#define _CACHE_UNCACHED (2<<_CACHE_SHIFT)
#define _CACHE_CACHABLE_NONCOHERENT (3<<_CACHE_SHIFT)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define _CACHE_CACHABLE_CE (4<<_CACHE_SHIFT)
#define _CACHE_CACHABLE_COW (5<<_CACHE_SHIFT)
#define _CACHE_CACHABLE_COHERENT (5<<_CACHE_SHIFT)
#define _CACHE_CACHABLE_CUW (6<<_CACHE_SHIFT)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define _CACHE_UNCACHED_ACCELERATED (7<<_CACHE_SHIFT)
#define __READABLE (_PAGE_READ | _PAGE_SILENT_READ | _PAGE_ACCESSED)
#define __WRITEABLE (_PAGE_WRITE | _PAGE_SILENT_WRITE | _PAGE_MODIFIED)
#define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_MODIFIED | _CACHE_MASK)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#endif

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libc/kernel/arch-mips/asm/pgtable.h Normal file
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/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef _ASM_PGTABLE_H
#define _ASM_PGTABLE_H
#include <asm/io.h>
#include <asm/pgtable-bits.h>
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
struct mm_struct;
struct vm_area_struct;
#define PAGE_NONE __pgprot(_PAGE_PRESENT | _CACHE_CACHABLE_NONCOHERENT)
#define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | _page_cachable_default)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PAGE_COPY __pgprot(_PAGE_PRESENT | _PAGE_READ | _page_cachable_default)
#define PAGE_READONLY __pgprot(_PAGE_PRESENT | _PAGE_READ | _page_cachable_default)
#define PAGE_KERNEL __pgprot(_PAGE_PRESENT | __READABLE | __WRITEABLE | _PAGE_GLOBAL | _page_cachable_default)
#define PAGE_USERIO __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | _page_cachable_default)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PAGE_KERNEL_UNCACHED __pgprot(_PAGE_PRESENT | __READABLE | __WRITEABLE | _PAGE_GLOBAL | _CACHE_UNCACHED)
#define __P000 __pgprot(0)
#define __P001 __pgprot(0)
#define __P010 __pgprot(0)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define __P011 __pgprot(0)
#define __P100 __pgprot(0)
#define __P101 __pgprot(0)
#define __P110 __pgprot(0)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define __P111 __pgprot(0)
#define __S000 __pgprot(0)
#define __S001 __pgprot(0)
#define __S010 __pgprot(0)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define __S011 __pgprot(0)
#define __S100 __pgprot(0)
#define __S101 __pgprot(0)
#define __S110 __pgprot(0)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define __S111 __pgprot(0)
#define ZERO_PAGE(vaddr) (virt_to_page((void *)(empty_zero_page + (((unsigned long)(vaddr)) & zero_page_mask))))
#define pmd_phys(pmd) virt_to_phys((void *)pmd_val(pmd))
#define pmd_page(pmd) (pfn_to_page(pmd_phys(pmd) >> PAGE_SHIFT))
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define pmd_page_vaddr(pmd) pmd_val(pmd)
#define pte_none(pte) (!(pte_val(pte) & ~_PAGE_GLOBAL))
#define pte_present(pte) (pte_val(pte) & _PAGE_PRESENT)
#define set_pte_at(mm, addr, ptep, pteval) set_pte(ptep, pteval)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define set_pmd(pmdptr, pmdval) do { *(pmdptr) = (pmdval); } while(0)
#define PGD_T_LOG2 (__builtin_ffs(sizeof(pgd_t)) - 1)
#define PMD_T_LOG2 (__builtin_ffs(sizeof(pmd_t)) - 1)
#define PTE_T_LOG2 (__builtin_ffs(sizeof(pte_t)) - 1)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define pgprot_noncached pgprot_noncached
#define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot))
#define kern_addr_valid(addr) (1)
#define io_remap_pfn_range(vma, vaddr, pfn, size, prot) remap_pfn_range(vma, vaddr, pfn, size, prot)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#include <asm-generic/pgtable.h>
#define HAVE_ARCH_UNMAPPED_AREA
#define pgtable_cache_init() do { } while (0)
#endif
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */

25
libc/kernel/arch-mips/asm/poll.h Normal file
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/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef __ASM_POLL_H
#define __ASM_POLL_H
#define POLLWRNORM POLLOUT
#define POLLWRBAND 0x0100
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#include <asm-generic/poll.h>
#endif

95
libc/kernel/arch-mips/asm/posix_types.h Normal file
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/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef _ASM_POSIX_TYPES_H
#define _ASM_POSIX_TYPES_H
#include <asm/sgidefs.h>
typedef unsigned long __kernel_ino_t;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
typedef unsigned int __kernel_mode_t;
#if _MIPS_SZLONG == 32
typedef unsigned long __kernel_nlink_t;
#endif
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#if _MIPS_SZLONG == 64
typedef unsigned int __kernel_nlink_t;
#endif
typedef long __kernel_off_t;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
typedef int __kernel_pid_t;
typedef int __kernel_ipc_pid_t;
typedef unsigned int __kernel_uid_t;
typedef unsigned int __kernel_gid_t;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#if _MIPS_SZLONG == 32
typedef unsigned int __kernel_size_t;
typedef int __kernel_ssize_t;
typedef int __kernel_ptrdiff_t;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#endif
#if _MIPS_SZLONG == 64
typedef unsigned long __kernel_size_t;
typedef long __kernel_ssize_t;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
typedef long __kernel_ptrdiff_t;
#endif
typedef long __kernel_time_t;
typedef long __kernel_suseconds_t;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
typedef long __kernel_clock_t;
typedef int __kernel_timer_t;
typedef int __kernel_clockid_t;
typedef long __kernel_daddr_t;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
typedef char * __kernel_caddr_t;
typedef unsigned short __kernel_uid16_t;
typedef unsigned short __kernel_gid16_t;
typedef unsigned int __kernel_uid32_t;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
typedef unsigned int __kernel_gid32_t;
typedef __kernel_uid_t __kernel_old_uid_t;
typedef __kernel_gid_t __kernel_old_gid_t;
typedef unsigned int __kernel_old_dev_t;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#ifdef __GNUC__
typedef long long __kernel_loff_t;
#endif
typedef struct {
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#if _MIPS_SZLONG == 32
long val[2];
#endif
#if _MIPS_SZLONG == 64
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
int val[2];
#endif
} __kernel_fsid_t;
#if !defined(__GLIBC__) || __GLIBC__ < 2
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#undef __FD_SET
#define __FD_SET(fd, fdsetp) (((fd_set *)(fdsetp))->fds_bits[(fd) >> 5] |= (1<<((fd) & 31)))
#undef __FD_CLR
#define __FD_CLR(fd, fdsetp) (((fd_set *)(fdsetp))->fds_bits[(fd) >> 5] &= ~(1<<((fd) & 31)))
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#undef __FD_ISSET
#define __FD_ISSET(fd, fdsetp) ((((fd_set *)(fdsetp))->fds_bits[(fd) >> 5] & (1<<((fd) & 31))) != 0)
#undef __FD_ZERO
#define __FD_ZERO(fdsetp) (memset (fdsetp, 0, sizeof (*(fd_set *)(fdsetp))))
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#endif
#endif

34
libc/kernel/arch-mips/asm/prefetch.h Normal file
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/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef __ASM_PREFETCH_H
#define __ASM_PREFETCH_H
#define Pref_Load 0
#define Pref_Store 1
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define Pref_LoadStreamed 4
#define Pref_StoreStreamed 5
#define Pref_LoadRetained 6
#define Pref_StoreRetained 7
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define Pref_WriteBackInvalidate 25
#define Pref_PrepareForStore 30
#ifdef __ASSEMBLY__
#endif
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#endif

89
libc/kernel/arch-mips/asm/processor.h Normal file
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/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef _ASM_PROCESSOR_H
#define _ASM_PROCESSOR_H
#include <linux/cpumask.h>
#include <linux/threads.h>
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#include <asm/cachectl.h>
#include <asm/cpu.h>
#include <asm/cpu-info.h>
#include <asm/mipsregs.h>
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#include <asm/prefetch.h>
#include <asm/system.h>
#define current_text_addr() ({ __label__ _l; _l: &&_l;})
#define NUM_FPU_REGS 32
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
typedef __u64 fpureg_t;
struct mips_fpu_struct {
fpureg_t fpr[NUM_FPU_REGS];
unsigned int fcr31;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
};
#define NUM_DSP_REGS 6
typedef __u32 dspreg_t;
struct mips_dsp_state {
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
dspreg_t dspr[NUM_DSP_REGS];
unsigned int dspcontrol;
};
#define INIT_CPUMASK { {0,} }
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
typedef struct {
unsigned long seg;
} mm_segment_t;
#define ARCH_MIN_TASKALIGN 8
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
struct mips_abi;
struct thread_struct {
unsigned long reg16;
unsigned long reg17, reg18, reg19, reg20, reg21, reg22, reg23;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
unsigned long reg29, reg30, reg31;
unsigned long cp0_status;
struct mips_fpu_struct fpu;
struct mips_dsp_state dsp;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
unsigned long cp0_badvaddr;
unsigned long cp0_baduaddr;
unsigned long error_code;
unsigned long trap_no;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
unsigned long irix_trampoline;
unsigned long irix_oldctx;
struct mips_abi *abi;
};
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define FPAFF_INIT
#define INIT_THREAD { .reg16 = 0, .reg17 = 0, .reg18 = 0, .reg19 = 0, .reg20 = 0, .reg21 = 0, .reg22 = 0, .reg23 = 0, .reg29 = 0, .reg30 = 0, .reg31 = 0, .cp0_status = 0, .fpu = { .fpr = {0,}, .fcr31 = 0, }, FPAFF_INIT .dsp = { .dspr = {0, }, .dspcontrol = 0, }, .cp0_badvaddr = 0, .cp0_baduaddr = 0, .error_code = 0, .trap_no = 0, .irix_trampoline = 0, .irix_oldctx = 0, }
struct task_struct;
#define release_thread(thread) do { } while(0)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define prepare_to_copy(tsk) do { } while (0)
#define __KSTK_TOS(tsk) ((unsigned long)task_stack_page(tsk) + THREAD_SIZE - 32)
#define task_pt_regs(tsk) ((struct pt_regs *)__KSTK_TOS(tsk) - 1)
#define KSTK_EIP(tsk) (task_pt_regs(tsk)->cp0_epc)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define KSTK_ESP(tsk) (task_pt_regs(tsk)->regs[29])
#define KSTK_STATUS(tsk) (task_pt_regs(tsk)->cp0_status)
#define cpu_relax() barrier()
#define return_address() ({__asm__ __volatile__("":::"$31");__builtin_return_address(0);})
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#endif

61
libc/kernel/arch-mips/asm/ptrace.h Normal file
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/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef _ASM_PTRACE_H
#define _ASM_PTRACE_H
#define FPR_BASE 32
#define PC 64
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define CAUSE 65
#define BADVADDR 66
#define MMHI 67
#define MMLO 68
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define FPC_CSR 69
#define FPC_EIR 70
#define DSP_BASE 71
#define DSP_CONTROL 77
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define ACX 78
struct pt_regs {
unsigned long regs[32];
unsigned long cp0_status;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
unsigned long hi;
unsigned long lo;
unsigned long cp0_badvaddr;
unsigned long cp0_cause;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
unsigned long cp0_epc;
} __attribute__ ((aligned (8)));
#define PTRACE_GETREGS 12
#define PTRACE_SETREGS 13
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PTRACE_GETFPREGS 14
#define PTRACE_SETFPREGS 15
#define PTRACE_OLDSETOPTIONS 21
#define PTRACE_GET_THREAD_AREA 25
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PTRACE_SET_THREAD_AREA 26
#define PTRACE_PEEKTEXT_3264 0xc0
#define PTRACE_PEEKDATA_3264 0xc1
#define PTRACE_POKETEXT_3264 0xc2
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PTRACE_POKEDATA_3264 0xc3
#define PTRACE_GET_THREAD_AREA_3264 0xc4
#endif

74
libc/kernel/arch-mips/asm/reg.h Normal file
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/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef __ASM_MIPS_REG_H
#define __ASM_MIPS_REG_H
#ifdef WANT_COMPAT_REG_H
#define EF_R0 6
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define EF_R1 7
#define EF_R2 8
#define EF_R3 9
#define EF_R4 10
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define EF_R5 11
#define EF_R6 12
#define EF_R7 13
#define EF_R8 14
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define EF_R9 15
#define EF_R10 16
#define EF_R11 17
#define EF_R12 18
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define EF_R13 19
#define EF_R14 20
#define EF_R15 21
#define EF_R16 22
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define EF_R17 23
#define EF_R18 24
#define EF_R19 25
#define EF_R20 26
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define EF_R21 27
#define EF_R22 28
#define EF_R23 29
#define EF_R24 30
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define EF_R25 31
#define EF_R26 32
#define EF_R27 33
#define EF_R28 34
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define EF_R29 35
#define EF_R30 36
#define EF_R31 37
#define EF_LO 38
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define EF_HI 39
#define EF_CP0_EPC 40
#define EF_CP0_BADVADDR 41
#define EF_CP0_STATUS 42
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define EF_CP0_CAUSE 43
#define EF_UNUSED0 44
#define EF_SIZE 180
#endif
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#endif

118
libc/kernel/arch-mips/asm/regdef.h Normal file
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/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef _ASM_REGDEF_H
#define _ASM_REGDEF_H
#include <asm/sgidefs.h>
#if _MIPS_SIM == _MIPS_SIM_ABI32
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define zero $0
#define AT $1
#define v0 $2
#define v1 $3
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define a0 $4
#define a1 $5
#define a2 $6
#define a3 $7
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define t0 $8
#define t1 $9
#define t2 $10
#define t3 $11
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define t4 $12
#define t5 $13
#define t6 $14
#define t7 $15
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define s0 $16
#define s1 $17
#define s2 $18
#define s3 $19
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define s4 $20
#define s5 $21
#define s6 $22
#define s7 $23
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define t8 $24
#define t9 $25
#define jp $25
#define k0 $26
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define k1 $27
#define gp $28
#define sp $29
#define fp $30
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define s8 $30
#define ra $31
#endif
#if _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define zero $0
#define AT $at
#define v0 $2
#define v1 $3
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define a0 $4
#define a1 $5
#define a2 $6
#define a3 $7
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define a4 $8
#define ta0 $8
#define a5 $9
#define ta1 $9
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define a6 $10
#define ta2 $10
#define a7 $11
#define ta3 $11
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define t0 $12
#define t1 $13
#define t2 $14
#define t3 $15
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define s0 $16
#define s1 $17
#define s2 $18
#define s3 $19
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define s4 $20
#define s5 $21
#define s6 $22
#define s7 $23
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define t8 $24
#define t9 $25
#define jp $25
#define k0 $26
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define k1 $27
#define gp $28
#define sp $29
#define fp $30
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define s8 $30
#define ra $31
#endif
#endif
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */

29
libc/kernel/arch-mips/asm/resource.h Normal file
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@ -0,0 +1,29 @@
/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef _ASM_RESOURCE_H
#define _ASM_RESOURCE_H
#define RLIMIT_NOFILE 5
#define RLIMIT_AS 6
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define RLIMIT_RSS 7
#define RLIMIT_NPROC 8
#define RLIMIT_MEMLOCK 9
#include <asm-generic/resource.h>
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#endif

34
libc/kernel/arch-mips/asm/scatterlist.h Normal file
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@ -0,0 +1,34 @@
/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef __ASM_SCATTERLIST_H
#define __ASM_SCATTERLIST_H
#include <asm/types.h>
struct scatterlist {
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
unsigned long page_link;
unsigned int offset;
dma_addr_t dma_address;
unsigned int length;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
};
#define sg_dma_address(sg) ((sg)->dma_address)
#define sg_dma_len(sg) ((sg)->length)
#define ISA_DMA_THRESHOLD (0x00ffffffUL)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#endif

23
libc/kernel/arch-mips/asm/sections.h Normal file
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@ -0,0 +1,23 @@
/****************************************************************************
****************************************************************************
***
*** This header was automatically generated from a Linux kernel header
*** of the same name, to make information necessary for userspace to
*** call into the kernel available to libc. It contains only constants,
*** structures, and macros generated from the original header, and thus,
*** contains no copyrightable information.
***
*** To edit the content of this header, modify the corresponding
*** source file (e.g. under external/kernel-headers/original/) then
*** run bionic/libc/kernel/tools/update_all.py
***
*** Any manual change here will be lost the next time this script will
*** be run. You've been warned!
***
****************************************************************************
****************************************************************************/
#ifndef _ASM_SECTIONS_H
#define _ASM_SECTIONS_H
#include <asm-generic/sections.h>
#endif
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */

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