am 8657eafc: Merge "Adjust memcpy for ARM Cortex A9 cache line size"
* commit '8657eafc3552f36c176667c1591beab255308da6': Adjust memcpy for ARM Cortex A9 cache line size
This commit is contained in:
commit
e636e1f2c1
libc
@ -477,6 +477,14 @@ ifeq ($(TARGET_ARCH),arm)
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ifeq ($(ARCH_ARM_HAVE_TLS_REGISTER),true)
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ifeq ($(ARCH_ARM_HAVE_TLS_REGISTER),true)
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libc_common_cflags += -DHAVE_ARM_TLS_REGISTER
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libc_common_cflags += -DHAVE_ARM_TLS_REGISTER
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endif
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endif
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#
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# Define HAVE_32_BYTE_CACHE_LINES to indicate to C
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# library it should use to 32-byte version of memcpy, and not
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# the 64-byte version.
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#
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ifeq ($(ARCH_ARM_HAVE_32_BYTE_CACHE_LINES),true)
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libc_common_cflags += -DHAVE_32_BYTE_CACHE_LINE
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endif
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else # !arm
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else # !arm
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ifeq ($(TARGET_ARCH),x86)
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ifeq ($(TARGET_ARCH),x86)
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libc_crt_target_cflags :=
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libc_crt_target_cflags :=
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@ -34,23 +34,28 @@
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.text
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.text
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.fpu neon
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.fpu neon
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#ifdef HAVE_32_BYTE_CACHE_LINE
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/* a prefetch distance of 2 cache-lines */
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#define CACHE_LINE_SIZE 32
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#define PREFETCH_DISTANCE (CACHE_LINE_SIZE*2)
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#else
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/* a prefetch distance of 4 cache-lines works best experimentally */
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/* a prefetch distance of 4 cache-lines works best experimentally */
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#define CACHE_LINE_SIZE 64
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#define CACHE_LINE_SIZE 64
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#define PREFETCH_DISTANCE (CACHE_LINE_SIZE*4)
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#define PREFETCH_DISTANCE (CACHE_LINE_SIZE*4)
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#endif
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ENTRY(memcpy)
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ENTRY(memcpy)
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.save {r0, lr}
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.save {r0, lr}
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stmfd sp!, {r0, lr}
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/* start preloading as early as possible */
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/* start preloading as early as possible */
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pld [r1, #(CACHE_LINE_SIZE*0)]
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pld [r1, #(CACHE_LINE_SIZE*0)]
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stmfd sp!, {r0, lr}
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pld [r1, #(CACHE_LINE_SIZE*1)]
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pld [r1, #(CACHE_LINE_SIZE*1)]
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/* do we have at least 16-bytes to copy (needed for alignment below) */
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/* do we have at least 16-bytes to copy (needed for alignment below) */
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cmp r2, #16
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cmp r2, #16
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blo 5f
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blo 5f
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/* align destination to half cache-line for the write-buffer */
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/* align destination to cache-line for the write-buffer */
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rsb r3, r0, #0
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rsb r3, r0, #0
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ands r3, r3, #0xF
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ands r3, r3, #0xF
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beq 0f
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beq 0f
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@ -79,6 +84,26 @@ ENTRY(memcpy)
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pld [r1, #(CACHE_LINE_SIZE*0)]
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pld [r1, #(CACHE_LINE_SIZE*0)]
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pld [r1, #(CACHE_LINE_SIZE*1)]
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pld [r1, #(CACHE_LINE_SIZE*1)]
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#ifdef HAVE_32_BYTE_CACHE_LINE
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/* make sure we have at least 32 bytes to copy */
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subs r2, r2, #32
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blo 4f
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/* preload all the cache lines we need.
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* NOTE: the number of pld below depends on PREFETCH_DISTANCE,
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* ideally would would increase the distance in the main loop to
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* avoid the goofy code below. In practice this doesn't seem to make
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* a big difference.
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*/
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pld [r1, #(PREFETCH_DISTANCE)]
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1: /* The main loop copies 32 bytes at a time */
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vld1.8 {d0 - d3}, [r1]!
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pld [r1, #(PREFETCH_DISTANCE)]
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subs r2, r2, #32
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vst1.8 {d0 - d3}, [r0, :128]!
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bhs 1b
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#else
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/* make sure we have at least 64 bytes to copy */
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/* make sure we have at least 64 bytes to copy */
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subs r2, r2, #64
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subs r2, r2, #64
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blo 2f
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blo 2f
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@ -112,7 +137,7 @@ ENTRY(memcpy)
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subs r2, r2, #32
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subs r2, r2, #32
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vst1.8 {d0 - d3}, [r0, :128]!
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vst1.8 {d0 - d3}, [r0, :128]!
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bhs 3b
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bhs 3b
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#endif
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4: /* less than 32 left */
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4: /* less than 32 left */
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add r2, r2, #32
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add r2, r2, #32
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tst r2, #0x10
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tst r2, #0x10
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