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Introduce a new ARM header file <machine/cpu-features.h>

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Introduce a new header file containing ARM-specific feature
test macros (e.g. __ARM_HAVE_PAIR_LOAD_STORE corresponding
to ldrd/strd instructions). Also modify a few files in our
system to use the macros in order to build for ARMv4T.
This commit is contained in:
Jean-Baptiste Queru 2008-12-04 12:02:39 -08:00
parent 39c8f369ef
commit e0055e0f99
5 changed files with 201 additions and 25 deletions
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19
libc/arch-arm/bionic/memcmp.S
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@ -25,6 +25,9 @@
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#include <machine/cpu-features.h>
.text
.global memcmp
@ -41,8 +44,8 @@
*/
memcmp:
pld [r0, #0]
pld [r1, #0]
PLD (r0, #0)
PLD (r1, #0)
/* take of the case where length is 0 or the buffers are the same */
cmp r0, r1
@ -53,8 +56,8 @@ memcmp:
/* save registers */
stmfd sp!, {r4, lr}
pld [r0, #32]
pld [r1, #32]
PLD (r0, #32)
PLD (r1, #32)
/* since r0 hold the result, move the first source
* pointer somewhere else
@ -104,8 +107,8 @@ memcmp:
subs r2, r2, #(32 + 4)
bmi 1f
0: pld [r4, #64]
pld [r1, #64]
0: PLD (r4, #64)
PLD (r1, #64)
ldr r0, [r4], #4
ldr lr, [r1, #4]!
eors r0, r0, ip
@ -192,8 +195,8 @@ memcmp:
bic r1, r1, #3
ldr lr, [r1], #4
6: pld [r1, #64]
pld [r4, #64]
6: PLD (r1, #64)
PLD (r4, #64)
mov ip, lr, lsr #16
ldr lr, [r1], #4
ldr r0, [r4], #4

19
libc/arch-arm/bionic/memcmp16.S
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@ -25,6 +25,9 @@
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#include <machine/cpu-features.h>
.text
.global __memcmp16
@ -41,8 +44,8 @@
*/
__memcmp16:
pld [r0, #0]
pld [r1, #0]
PLD (r0, #0)
PLD (r1, #0)
/* take of the case where length is nul or the buffers are the same */
cmp r0, r1
@ -64,8 +67,8 @@ __memcmp16:
bpl 0f
/* small blocks (less then 12 words) */
pld [r0, #32]
pld [r1, #32]
PLD (r0, #32)
PLD (r1, #32)
1: ldrh r0, [r3], #2
ldrh ip, [r1], #2
@ -113,8 +116,8 @@ __memcmp16:
bmi 1f
0:
pld [r3, #64]
pld [r1, #64]
PLD (r3, #64)
PLD (r1, #64)
ldr r0, [r3], #4
ldr lr, [r1, #4]!
eors r0, r0, ip
@ -195,8 +198,8 @@ __memcmp16:
sub r2, r2, #8
6:
pld [r3, #64]
pld [r1, #64]
PLD (r3, #64)
PLD (r1, #64)
mov ip, lr, lsr #16
ldr lr, [r1], #4
ldr r0, [r3], #4

21
libc/arch-arm/bionic/memcpy.S
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@ -25,6 +25,9 @@
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#include <machine/cpu-features.h>
.text
.global memcpy
@ -52,9 +55,9 @@ memcpy:
// preload the destination because we'll align it to a cache line
// with small writes. Also start the source "pump".
pld [r0, #0]
pld [r1, #0]
pld [r1, #32]
PLD (r0, #0)
PLD (r1, #0)
PLD (r1, #32)
/* it simplifies things to take care of len<4 early */
cmp r2, #4
@ -141,8 +144,8 @@ cached_aligned32:
bic r12, r1, #0x1F
add r12, r12, #64
1: ldmia r1!, { r4-r11 }
pld [r12, #64]
1: ldmia r1!, { r4-r11 }
PLD (r12, #64)
subs r2, r2, #32
// NOTE: if r12 is more than 64 ahead of r1, the following ldrhi
@ -263,8 +266,8 @@ loop16:
ldr r12, [r1], #4
1: mov r4, r12
ldmia r1!, { r5,r6,r7, r8,r9,r10,r11}
pld [r1, #64]
subs r2, r2, #32
PLD (r1, #64)
subs r2, r2, #32
ldrhs r12, [r1], #4
orr r3, r3, r4, lsl #16
mov r4, r4, lsr #16
@ -290,7 +293,7 @@ loop8:
ldr r12, [r1], #4
1: mov r4, r12
ldmia r1!, { r5,r6,r7, r8,r9,r10,r11}
pld [r1, #64]
PLD (r1, #64)
subs r2, r2, #32
ldrhs r12, [r1], #4
orr r3, r3, r4, lsl #24
@ -317,7 +320,7 @@ loop24:
ldr r12, [r1], #4
1: mov r4, r12
ldmia r1!, { r5,r6,r7, r8,r9,r10,r11}
pld [r1, #64]
PLD (r1, #64)
subs r2, r2, #32
ldrhs r12, [r1], #4
orr r3, r3, r4, lsl #8

3
libc/arch-arm/bionic/strlen.c
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@ -27,6 +27,7 @@
*/
#include <string.h>
#include <stdint.h>
#include <machine/cpu-features.h>
size_t strlen(const char *s)
{
@ -62,7 +63,9 @@ size_t strlen(const char *s)
"ldr %[v], [ %[s] ], #4 \n"
"sub %[l], %[l], %[s] \n"
"0: \n"
#if __ARM_HAVE_PLD
"pld [ %[s], #64 ] \n"
#endif
"sub %[t], %[v], %[mask], lsr #7\n"
"and %[t], %[t], %[mask] \n"
"bics %[t], %[t], %[v] \n"

164
libc/arch-arm/include/machine/cpu-features.h Normal file
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@ -0,0 +1,164 @@
/*
* Copyright (C) 2008 The Android Open Source Project
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#ifndef _ARM_MACHINE_CPU_FEATURES_H
#define _ARM_MACHINE_CPU_FEATURES_H
/* The purpose of this file is to define several macros corresponding
* to CPU features that may or may not be available at build time on
* on the target CPU.
*
* This is done to abstract us from the various ARM Architecture
* quirks and alphabet soup.
*
* IMPORTANT: We have no intention to support anything below an ARMv4T !
*/
/* _ARM_ARCH_REVISION is a number corresponding to the ARM revision
* we're going to support
*
* it looks like our toolchain doesn't define __ARM_ARCH__
* so try to guess it.
*
*
*
*/
#ifndef __ARM_ARCH__
# if defined __ARM_ARCH_7__ || defined __ARM_ARCH_7A__ || \
defined __ARM_ARCH_7R__ || defined __ARM_ARCH_7M__
# define __ARM_ARCH__ 7
# elif defined __ARM_ARCH_6__ || defined __ARM_ARCH_6J__ || \
defined __ARM_ARCH_6K__ || defined __ARM_ARCH_6Z__ || \
defined __ARM_ARCH_6KZ__ || defined __ARM_ARCH_6T2__
#
# define __ARM_ARCH__ 6
#
# elif defined __ARM_ARCH_5__ || defined __ARM_ARCH_5T__ || \
defined __ARM_ARCH_5TE__ || defined __ARM_ARCH_5TEJ__
#
# define __ARM_ARCH__ 5
#
# elif defined __ARM_ARCH_4T__
#
# define __ARM_ARCH__ 4
#
# elif defined __ARM_ARCH_4__
# error ARMv4 is not supported, please use ARMv4T at a minimum
# else
# error Unknown or unsupported ARM architecture
# endif
#endif
/* experimental feature used to check that our ARMv4 workarounds
* work correctly without a real ARMv4 machine */
#ifdef BIONIC_EXPERIMENTAL_FORCE_ARMV4
# undef __ARM_ARCH__
# define __ARM_ARCH__ 4
#endif
/* define __ARM_HAVE_5TE if we have the ARMv5TE instructions */
#if __ARM_ARCH__ > 5
# define __ARM_HAVE_5TE 1
#elif __ARM_ARCH__ == 5
# if defined __ARM_ARCH_5TE__ || defined __ARM_ARCH_5TEJ__
# define __ARM_HAVE_5TE 1
# endif
#endif
/* instructions introduced in ARMv5 */
#if __ARM_ARCH__ >= 5
# define __ARM_HAVE_BLX 1
# define __ARM_HAVE_CLZ 1
# define __ARM_HAVE_LDC2 1
# define __ARM_HAVE_MCR2 1
# define __ARM_HAVE_MRC2 1
# define __ARM_HAVE_STC2 1
#endif
/* ARMv5TE introduces a few instructions */
#if __ARM_HAVE_5TE
# define __ARM_HAVE_PLD 1
# define __ARM_HAVE_MCRR 1
# define __ARM_HAVE_MRRC 1
#endif
/* define __ARM_HAVE_HALFWORD_MULTIPLY when half-word multiply instructions
* this means variants of: smul, smulw, smla, smlaw, smlal
*/
#if __ARM_HAVE_5TE
# define __ARM_HAVE_HALFWORD_MULTIPLY 1
#endif
/* define __ARM_HAVE_PAIR_LOAD_STORE when 64-bit memory loads and stored
* into/from a pair of 32-bit registers is supported throuhg 'ldrd' and 'strd'
*/
#if __ARM_HAVE_5TE
# define __ARM_HAVE_PAIR_LOAD_STORE 1
#endif
/* define __ARM_HAVE_SATURATED_ARITHMETIC is you have the saturated integer
* arithmetic instructions: qdd, qdadd, qsub, qdsub
*/
#if __ARM_HAVE_5TE
# define __ARM_HAVE_SATURATED_ARITHMETIC 1
#endif
/* define __ARM_HAVE_PC_INTERWORK when a direct assignment to the
* pc register will switch into thumb/ARM mode depending on bit 0
* of the new instruction address. Before ARMv5, this was not the
* case, and you have to write:
*
* mov r0, [<some address>]
* bx r0
*
* instead of:
*
* ldr pc, [<some address>]
*
* note that this affects any instruction that explicitely changes the
* value of the pc register, including ldm { ...,pc } or 'add pc, #offset'
*/
#if __ARM_ARCH__ >= 5
# define __ARM_HAVE_PC_INTERWORK
#endif
/* Assembly-only macros */
/* define a handy PLD(address) macro since the cache preload
* is an optional opcode
*/
#if __ARM_HAVE_PLD
# define PLD(reg,offset) pld [reg, offset]
#else
# define PLD(reg,offset) /* nothing */
#endif
#endif /* _ARM_MACHINE_CPU_FEATURES_H */