Clean up trailing whitespace in the kernel headers.
And fix the scripts so they stop letting trailing whitespace through. Change-Id: Ie109fbe1f63321e565ba0fa60fee8e9cf3a61cfc
This commit is contained in:
Elliott Hughes
@@ -24,19 +24,19 @@
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struct hpc_dma_desc {
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u32 pbuf;
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u32 cntinfo;
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#define HPCDMA_EOX 0x80000000
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#define HPCDMA_EOX 0x80000000
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define HPCDMA_EOR 0x80000000
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#define HPCDMA_EOXP 0x40000000
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#define HPCDMA_EORP 0x40000000
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#define HPCDMA_XIE 0x20000000
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#define HPCDMA_EOR 0x80000000
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#define HPCDMA_EOXP 0x40000000
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#define HPCDMA_EORP 0x40000000
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#define HPCDMA_XIE 0x20000000
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define HPCDMA_XIU 0x01000000
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#define HPCDMA_EIPC 0x00ff0000
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#define HPCDMA_ETXD 0x00008000
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#define HPCDMA_OWN 0x00004000
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#define HPCDMA_XIU 0x01000000
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#define HPCDMA_EIPC 0x00ff0000
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#define HPCDMA_ETXD 0x00008000
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#define HPCDMA_OWN 0x00004000
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define HPCDMA_BCNT 0x00003fff
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#define HPCDMA_BCNT 0x00003fff
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u32 pnext;
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};
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struct hpc3_pbus_dmacregs {
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@@ -46,19 +46,19 @@ struct hpc3_pbus_dmacregs {
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u32 _unused0[0x1000/4 - 2];
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volatile u32 pbdma_ctrl;
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define HPC3_PDMACTRL_INT 0x00000001
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#define HPC3_PDMACTRL_ISACT 0x00000002
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#define HPC3_PDMACTRL_SEL 0x00000002
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#define HPC3_PDMACTRL_RCV 0x00000004
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#define HPC3_PDMACTRL_INT 0x00000001
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#define HPC3_PDMACTRL_ISACT 0x00000002
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#define HPC3_PDMACTRL_SEL 0x00000002
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#define HPC3_PDMACTRL_RCV 0x00000004
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define HPC3_PDMACTRL_FLSH 0x00000008
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#define HPC3_PDMACTRL_ACT 0x00000010
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#define HPC3_PDMACTRL_LD 0x00000020
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#define HPC3_PDMACTRL_RT 0x00000040
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#define HPC3_PDMACTRL_FLSH 0x00000008
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#define HPC3_PDMACTRL_ACT 0x00000010
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#define HPC3_PDMACTRL_LD 0x00000020
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#define HPC3_PDMACTRL_RT 0x00000040
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define HPC3_PDMACTRL_HW 0x0000ff00
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#define HPC3_PDMACTRL_FB 0x003f0000
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#define HPC3_PDMACTRL_FE 0x3f000000
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#define HPC3_PDMACTRL_HW 0x0000ff00
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#define HPC3_PDMACTRL_FB 0x003f0000
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#define HPC3_PDMACTRL_FE 0x3f000000
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u32 _unused1[0x1000/4 - 1];
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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};
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@@ -68,48 +68,48 @@ struct hpc3_scsiregs {
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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u32 _unused0[0x1000/4 - 2];
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volatile u32 bcd;
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#define HPC3_SBCD_BCNTMSK 0x00003fff
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#define HPC3_SBCD_XIE 0x00004000
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#define HPC3_SBCD_BCNTMSK 0x00003fff
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#define HPC3_SBCD_XIE 0x00004000
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define HPC3_SBCD_EOX 0x00008000
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#define HPC3_SBCD_EOX 0x00008000
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volatile u32 ctrl;
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#define HPC3_SCTRL_IRQ 0x01
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#define HPC3_SCTRL_ENDIAN 0x02
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#define HPC3_SCTRL_IRQ 0x01
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#define HPC3_SCTRL_ENDIAN 0x02
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define HPC3_SCTRL_DIR 0x04
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#define HPC3_SCTRL_FLUSH 0x08
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#define HPC3_SCTRL_ACTIVE 0x10
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#define HPC3_SCTRL_AMASK 0x20
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#define HPC3_SCTRL_DIR 0x04
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#define HPC3_SCTRL_FLUSH 0x08
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#define HPC3_SCTRL_ACTIVE 0x10
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#define HPC3_SCTRL_AMASK 0x20
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define HPC3_SCTRL_CRESET 0x40
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#define HPC3_SCTRL_PERR 0x80
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#define HPC3_SCTRL_CRESET 0x40
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#define HPC3_SCTRL_PERR 0x80
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volatile u32 gfptr;
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volatile u32 dfptr;
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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volatile u32 dconfig;
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#define HPC3_SDCFG_HCLK 0x00001
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#define HPC3_SDCFG_D1 0x00006
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#define HPC3_SDCFG_D2 0x00038
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#define HPC3_SDCFG_HCLK 0x00001
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#define HPC3_SDCFG_D1 0x00006
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#define HPC3_SDCFG_D2 0x00038
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define HPC3_SDCFG_D3 0x001c0
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#define HPC3_SDCFG_HWAT 0x00e00
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#define HPC3_SDCFG_HW 0x01000
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#define HPC3_SDCFG_SWAP 0x02000
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#define HPC3_SDCFG_D3 0x001c0
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#define HPC3_SDCFG_HWAT 0x00e00
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#define HPC3_SDCFG_HW 0x01000
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#define HPC3_SDCFG_SWAP 0x02000
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define HPC3_SDCFG_EPAR 0x04000
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#define HPC3_SDCFG_POLL 0x08000
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#define HPC3_SDCFG_ERLY 0x30000
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#define HPC3_SDCFG_EPAR 0x04000
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#define HPC3_SDCFG_POLL 0x08000
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#define HPC3_SDCFG_ERLY 0x30000
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volatile u32 pconfig;
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define HPC3_SPCFG_P3 0x0003
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#define HPC3_SPCFG_P2W 0x001c
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#define HPC3_SPCFG_P2R 0x01e0
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#define HPC3_SPCFG_P1 0x0e00
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#define HPC3_SPCFG_P3 0x0003
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#define HPC3_SPCFG_P2W 0x001c
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#define HPC3_SPCFG_P2R 0x01e0
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#define HPC3_SPCFG_P1 0x0e00
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define HPC3_SPCFG_HW 0x1000
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#define HPC3_SPCFG_SWAP 0x2000
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#define HPC3_SPCFG_EPAR 0x4000
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#define HPC3_SPCFG_FUJI 0x8000
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#define HPC3_SPCFG_HW 0x1000
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#define HPC3_SPCFG_SWAP 0x2000
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#define HPC3_SPCFG_EPAR 0x4000
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#define HPC3_SPCFG_FUJI 0x8000
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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u32 _unused1[0x1000/4 - 6];
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};
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@@ -119,46 +119,46 @@ struct hpc3_ethregs {
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volatile u32 rx_ndptr;
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u32 _unused0[0x1000/4 - 2];
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volatile u32 rx_bcd;
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#define HPC3_ERXBCD_BCNTMSK 0x00003fff
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#define HPC3_ERXBCD_BCNTMSK 0x00003fff
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define HPC3_ERXBCD_XIE 0x20000000
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#define HPC3_ERXBCD_EOX 0x80000000
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#define HPC3_ERXBCD_XIE 0x20000000
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#define HPC3_ERXBCD_EOX 0x80000000
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volatile u32 rx_ctrl;
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#define HPC3_ERXCTRL_STAT50 0x0000003f
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#define HPC3_ERXCTRL_STAT50 0x0000003f
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define HPC3_ERXCTRL_STAT6 0x00000040
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#define HPC3_ERXCTRL_STAT7 0x00000080
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#define HPC3_ERXCTRL_ENDIAN 0x00000100
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#define HPC3_ERXCTRL_ACTIVE 0x00000200
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#define HPC3_ERXCTRL_STAT6 0x00000040
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#define HPC3_ERXCTRL_STAT7 0x00000080
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#define HPC3_ERXCTRL_ENDIAN 0x00000100
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#define HPC3_ERXCTRL_ACTIVE 0x00000200
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define HPC3_ERXCTRL_AMASK 0x00000400
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#define HPC3_ERXCTRL_RBO 0x00000800
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#define HPC3_ERXCTRL_AMASK 0x00000400
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#define HPC3_ERXCTRL_RBO 0x00000800
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volatile u32 rx_gfptr;
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volatile u32 rx_dfptr;
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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u32 _unused1;
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volatile u32 reset;
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#define HPC3_ERST_CRESET 0x1
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#define HPC3_ERST_CLRIRQ 0x2
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#define HPC3_ERST_CRESET 0x1
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#define HPC3_ERST_CLRIRQ 0x2
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define HPC3_ERST_LBACK 0x4
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#define HPC3_ERST_LBACK 0x4
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volatile u32 dconfig;
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#define HPC3_EDCFG_D1 0x0000f
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#define HPC3_EDCFG_D2 0x000f0
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#define HPC3_EDCFG_D1 0x0000f
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#define HPC3_EDCFG_D2 0x000f0
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define HPC3_EDCFG_D3 0x00f00
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#define HPC3_EDCFG_WCTRL 0x01000
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#define HPC3_EDCFG_FRXDC 0x02000
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#define HPC3_EDCFG_FEOP 0x04000
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#define HPC3_EDCFG_D3 0x00f00
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#define HPC3_EDCFG_WCTRL 0x01000
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#define HPC3_EDCFG_FRXDC 0x02000
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#define HPC3_EDCFG_FEOP 0x04000
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define HPC3_EDCFG_FIRQ 0x08000
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#define HPC3_EDCFG_PTO 0x30000
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#define HPC3_EDCFG_FIRQ 0x08000
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#define HPC3_EDCFG_PTO 0x30000
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volatile u32 pconfig;
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#define HPC3_EPCFG_P1 0x000f
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#define HPC3_EPCFG_P1 0x000f
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define HPC3_EPCFG_P2 0x00f0
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#define HPC3_EPCFG_P3 0x0f00
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#define HPC3_EPCFG_TST 0x1000
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#define HPC3_EPCFG_P2 0x00f0
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#define HPC3_EPCFG_P3 0x0f00
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#define HPC3_EPCFG_TST 0x1000
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u32 _unused2[0x1000/4 - 8];
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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volatile u32 tx_cbptr;
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@@ -166,20 +166,20 @@ struct hpc3_ethregs {
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u32 _unused3[0x1000/4 - 2];
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volatile u32 tx_bcd;
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define HPC3_ETXBCD_BCNTMSK 0x00003fff
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#define HPC3_ETXBCD_ESAMP 0x10000000
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#define HPC3_ETXBCD_XIE 0x20000000
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#define HPC3_ETXBCD_EOP 0x40000000
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#define HPC3_ETXBCD_BCNTMSK 0x00003fff
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#define HPC3_ETXBCD_ESAMP 0x10000000
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#define HPC3_ETXBCD_XIE 0x20000000
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#define HPC3_ETXBCD_EOP 0x40000000
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define HPC3_ETXBCD_EOX 0x80000000
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#define HPC3_ETXBCD_EOX 0x80000000
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volatile u32 tx_ctrl;
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#define HPC3_ETXCTRL_STAT30 0x0000000f
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#define HPC3_ETXCTRL_STAT4 0x00000010
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#define HPC3_ETXCTRL_STAT30 0x0000000f
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#define HPC3_ETXCTRL_STAT4 0x00000010
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define HPC3_ETXCTRL_STAT75 0x000000e0
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#define HPC3_ETXCTRL_ENDIAN 0x00000100
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#define HPC3_ETXCTRL_ACTIVE 0x00000200
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#define HPC3_ETXCTRL_AMASK 0x00000400
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#define HPC3_ETXCTRL_STAT75 0x000000e0
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#define HPC3_ETXCTRL_ENDIAN 0x00000100
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#define HPC3_ETXCTRL_ACTIVE 0x00000200
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#define HPC3_ETXCTRL_AMASK 0x00000400
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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volatile u32 tx_gfptr;
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volatile u32 tx_dfptr;
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@@ -193,28 +193,28 @@ struct hpc3_regs {
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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u32 _unused0[0x18000/4];
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volatile u32 istat0;
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#define HPC3_ISTAT_PBIMASK 0x0ff
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#define HPC3_ISTAT_SC0MASK 0x100
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#define HPC3_ISTAT_PBIMASK 0x0ff
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#define HPC3_ISTAT_SC0MASK 0x100
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define HPC3_ISTAT_SC1MASK 0x200
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#define HPC3_ISTAT_SC1MASK 0x200
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volatile u32 gio_misc;
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#define HPC3_GIOMISC_ERTIME 0x1
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#define HPC3_GIOMISC_DENDIAN 0x2
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#define HPC3_GIOMISC_ERTIME 0x1
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#define HPC3_GIOMISC_DENDIAN 0x2
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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u32 eeprom;
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#define HPC3_EEPROM_EPROT 0x01
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#define HPC3_EEPROM_CSEL 0x02
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#define HPC3_EEPROM_ECLK 0x04
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#define HPC3_EEPROM_EPROT 0x01
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#define HPC3_EEPROM_CSEL 0x02
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#define HPC3_EEPROM_ECLK 0x04
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define HPC3_EEPROM_DATO 0x08
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#define HPC3_EEPROM_DATI 0x10
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#define HPC3_EEPROM_DATO 0x08
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#define HPC3_EEPROM_DATI 0x10
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volatile u32 istat1;
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volatile u32 bestat;
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define HPC3_BESTAT_BLMASK 0x000ff
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#define HPC3_BESTAT_CTYPE 0x00100
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#define HPC3_BESTAT_BLMASK 0x000ff
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#define HPC3_BESTAT_CTYPE 0x00100
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#define HPC3_BESTAT_PIDSHIFT 9
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#define HPC3_BESTAT_PIDMASK 0x3f700
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#define HPC3_BESTAT_PIDMASK 0x3f700
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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u32 _unused1[0x14000/4 - 5];
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volatile u32 scsi0_ext[256];
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@@ -269,22 +269,22 @@ struct hpc3_regs {
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#define HPC3_PIOCFG_DS16 0x40000
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#define HPC3_PIOCFG_EVENHI 0x80000
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volatile u32 pbus_promwe;
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#define HPC3_PROM_WENAB 0x1
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#define HPC3_PROM_WENAB 0x1
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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u32 _unused5[0x0800/4 - 1];
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volatile u32 pbus_promswap;
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#define HPC3_PROM_SWAP 0x1
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#define HPC3_PROM_SWAP 0x1
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u32 _unused6[0x0800/4 - 1];
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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volatile u32 pbus_gout;
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#define HPC3_PROM_STAT 0x1
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#define HPC3_PROM_STAT 0x1
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u32 _unused7[0x1000/4 - 1];
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volatile u32 rtcregs[14];
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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u32 _unused8[50];
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volatile u32 bbram[8192-50-14];
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};
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#define HPC3_CHIP0_BASE 0x1fb80000
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#define HPC3_CHIP0_BASE 0x1fb80000
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define HPC3_CHIP1_BASE 0x1fb00000
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#define HPC3_CHIP1_BASE 0x1fb00000
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#endif
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