Update kernel uapi headers to v3.16.1.
Other changes to support the new headers: - Remove the flock64 structure it is defined in the new headers. - Update the syscalls to correspond with the headers. Change-Id: I49a6b07e8b2bfffb67be71b07b58e4e6848fcc09
This commit is contained in:
Christopher Ferris
31
libc/kernel/uapi/asm-x86/asm/kvm_perf.h
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31
libc/kernel/uapi/asm-x86/asm/kvm_perf.h
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@@ -0,0 +1,31 @@
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/****************************************************************************
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****************************************************************************
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***
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*** This header was automatically generated from a Linux kernel header
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*** of the same name, to make information necessary for userspace to
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*** call into the kernel available to libc. It contains only constants,
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*** structures, and macros generated from the original header, and thus,
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*** contains no copyrightable information.
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***
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*** To edit the content of this header, modify the corresponding
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*** source file (e.g. under external/kernel-headers/original/) then
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*** run bionic/libc/kernel/tools/update_all.py
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***
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*** Any manual change here will be lost the next time this script will
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*** be run. You've been warned!
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***
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****************************************************************************
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****************************************************************************/
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#ifndef _ASM_X86_KVM_PERF_H
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#define _ASM_X86_KVM_PERF_H
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#include <asm/svm.h>
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#include <asm/vmx.h>
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#include <asm/kvm.h>
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#define DECODE_STR_LEN 20
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#define VCPU_ID "vcpu_id"
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#define KVM_ENTRY_TRACE "kvm:kvm_entry"
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define KVM_EXIT_TRACE "kvm:kvm_exit"
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#define KVM_EXIT_REASON "exit_reason"
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#endif
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@@ -302,263 +302,295 @@
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#define MSR_IA32_FEATURE_CONTROL 0x0000003a
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define MSR_IA32_TSC_ADJUST 0x0000003b
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#define MSR_IA32_BNDCFGS 0x00000d90
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#define FEATURE_CONTROL_LOCKED (1<<0)
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#define FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX (1<<1)
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#define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2)
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2)
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#define MSR_IA32_APICBASE 0x0000001b
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#define MSR_IA32_APICBASE_BSP (1<<8)
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#define MSR_IA32_APICBASE_ENABLE (1<<11)
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#define MSR_IA32_APICBASE_BASE (0xfffff<<12)
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define MSR_IA32_APICBASE_BASE (0xfffff<<12)
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#define MSR_IA32_TSCDEADLINE 0x000006e0
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#define MSR_IA32_UCODE_WRITE 0x00000079
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#define MSR_IA32_UCODE_REV 0x0000008b
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#define MSR_IA32_PERF_STATUS 0x00000198
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define MSR_IA32_PERF_STATUS 0x00000198
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#define MSR_IA32_PERF_CTL 0x00000199
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#define MSR_AMD_PSTATE_DEF_BASE 0xc0010064
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#define MSR_AMD_PERF_STATUS 0xc0010063
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#define MSR_AMD_PERF_CTL 0xc0010062
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define MSR_AMD_PERF_CTL 0xc0010062
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#define MSR_IA32_MPERF 0x000000e7
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#define MSR_IA32_APERF 0x000000e8
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#define MSR_IA32_THERM_CONTROL 0x0000019a
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#define MSR_IA32_THERM_INTERRUPT 0x0000019b
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define MSR_IA32_THERM_INTERRUPT 0x0000019b
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#define THERM_INT_HIGH_ENABLE (1 << 0)
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#define THERM_INT_LOW_ENABLE (1 << 1)
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#define THERM_INT_PLN_ENABLE (1 << 24)
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#define MSR_IA32_THERM_STATUS 0x0000019c
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define MSR_IA32_THERM_STATUS 0x0000019c
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#define THERM_STATUS_PROCHOT (1 << 0)
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#define THERM_STATUS_POWER_LIMIT (1 << 10)
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#define MSR_THERM2_CTL 0x0000019d
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#define MSR_THERM2_CTL_TM_SELECT (1ULL << 16)
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define MSR_THERM2_CTL_TM_SELECT (1ULL << 16)
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#define MSR_IA32_MISC_ENABLE 0x000001a0
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#define MSR_IA32_TEMPERATURE_TARGET 0x000001a2
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#define MSR_IA32_ENERGY_PERF_BIAS 0x000001b0
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#define ENERGY_PERF_BIAS_PERFORMANCE 0
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define ENERGY_PERF_BIAS_PERFORMANCE 0
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#define ENERGY_PERF_BIAS_NORMAL 6
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#define ENERGY_PERF_BIAS_POWERSAVE 15
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#define MSR_IA32_PACKAGE_THERM_STATUS 0x000001b1
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#define PACKAGE_THERM_STATUS_PROCHOT (1 << 0)
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define PACKAGE_THERM_STATUS_PROCHOT (1 << 0)
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#define PACKAGE_THERM_STATUS_POWER_LIMIT (1 << 10)
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#define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001b2
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#define PACKAGE_THERM_INT_HIGH_ENABLE (1 << 0)
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#define PACKAGE_THERM_INT_LOW_ENABLE (1 << 1)
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define PACKAGE_THERM_INT_LOW_ENABLE (1 << 1)
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#define PACKAGE_THERM_INT_PLN_ENABLE (1 << 24)
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#define THERM_INT_THRESHOLD0_ENABLE (1 << 15)
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#define THERM_SHIFT_THRESHOLD0 8
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#define THERM_MASK_THRESHOLD0 (0x7f << THERM_SHIFT_THRESHOLD0)
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define THERM_MASK_THRESHOLD0 (0x7f << THERM_SHIFT_THRESHOLD0)
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#define THERM_INT_THRESHOLD1_ENABLE (1 << 23)
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#define THERM_SHIFT_THRESHOLD1 16
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#define THERM_MASK_THRESHOLD1 (0x7f << THERM_SHIFT_THRESHOLD1)
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#define THERM_STATUS_THRESHOLD0 (1 << 6)
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define THERM_STATUS_THRESHOLD0 (1 << 6)
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#define THERM_LOG_THRESHOLD0 (1 << 7)
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#define THERM_STATUS_THRESHOLD1 (1 << 8)
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#define THERM_LOG_THRESHOLD1 (1 << 9)
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#define MSR_IA32_MISC_ENABLE_FAST_STRING (1ULL << 0)
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define MSR_IA32_MISC_ENABLE_TCC (1ULL << 1)
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#define MSR_IA32_MISC_ENABLE_EMON (1ULL << 7)
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#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL (1ULL << 11)
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#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL (1ULL << 12)
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#define MSR_IA32_MISC_ENABLE_FAST_STRING_BIT 0
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#define MSR_IA32_MISC_ENABLE_FAST_STRING (1ULL << MSR_IA32_MISC_ENABLE_FAST_STRING_BIT)
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#define MSR_IA32_MISC_ENABLE_TCC_BIT 1
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#define MSR_IA32_MISC_ENABLE_TCC (1ULL << MSR_IA32_MISC_ENABLE_TCC_BIT)
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP (1ULL << 16)
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#define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << 18)
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#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID (1ULL << 22)
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#define MSR_IA32_MISC_ENABLE_XTPR_DISABLE (1ULL << 23)
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#define MSR_IA32_MISC_ENABLE_EMON_BIT 7
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#define MSR_IA32_MISC_ENABLE_EMON (1ULL << MSR_IA32_MISC_ENABLE_EMON_BIT)
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#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL_BIT 11
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#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL (1ULL << MSR_IA32_MISC_ENABLE_BTS_UNAVAIL_BIT)
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define MSR_IA32_MISC_ENABLE_XD_DISABLE (1ULL << 34)
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#define MSR_IA32_MISC_ENABLE_X87_COMPAT (1ULL << 2)
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#define MSR_IA32_MISC_ENABLE_TM1 (1ULL << 3)
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#define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE (1ULL << 4)
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#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL_BIT 12
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#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL (1ULL << MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL_BIT)
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#define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP_BIT 16
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#define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP (1ULL << MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP_BIT)
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE (1ULL << 6)
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#define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK (1ULL << 8)
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#define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE (1ULL << 9)
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#define MSR_IA32_MISC_ENABLE_FERR (1ULL << 10)
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#define MSR_IA32_MISC_ENABLE_MWAIT_BIT 18
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#define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << MSR_IA32_MISC_ENABLE_MWAIT_BIT)
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#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT 22
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#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID (1ULL << MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT)
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX (1ULL << 10)
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#define MSR_IA32_MISC_ENABLE_TM2 (1ULL << 13)
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#define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE (1ULL << 19)
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#define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK (1ULL << 20)
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#define MSR_IA32_MISC_ENABLE_XTPR_DISABLE_BIT 23
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#define MSR_IA32_MISC_ENABLE_XTPR_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_XTPR_DISABLE_BIT)
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#define MSR_IA32_MISC_ENABLE_XD_DISABLE_BIT 34
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#define MSR_IA32_MISC_ENABLE_XD_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_XD_DISABLE_BIT)
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define MSR_IA32_MISC_ENABLE_L1D_CONTEXT (1ULL << 24)
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#define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE (1ULL << 37)
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#define MSR_IA32_MISC_ENABLE_TURBO_DISABLE (1ULL << 38)
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#define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE (1ULL << 39)
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#define MSR_IA32_MISC_ENABLE_X87_COMPAT_BIT 2
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#define MSR_IA32_MISC_ENABLE_X87_COMPAT (1ULL << MSR_IA32_MISC_ENABLE_X87_COMPAT_BIT)
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#define MSR_IA32_MISC_ENABLE_TM1_BIT 3
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#define MSR_IA32_MISC_ENABLE_TM1 (1ULL << MSR_IA32_MISC_ENABLE_TM1_BIT)
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE_BIT 4
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#define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE_BIT)
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#define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE_BIT 6
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#define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE_BIT)
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK_BIT 8
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#define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK (1ULL << MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK_BIT)
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#define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT 9
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#define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT)
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define MSR_IA32_MISC_ENABLE_FERR_BIT 10
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#define MSR_IA32_MISC_ENABLE_FERR (1ULL << MSR_IA32_MISC_ENABLE_FERR_BIT)
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#define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX_BIT 10
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#define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX (1ULL << MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX_BIT)
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define MSR_IA32_MISC_ENABLE_TM2_BIT 13
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#define MSR_IA32_MISC_ENABLE_TM2 (1ULL << MSR_IA32_MISC_ENABLE_TM2_BIT)
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#define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE_BIT 19
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#define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE_BIT)
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK_BIT 20
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#define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK (1ULL << MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK_BIT)
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#define MSR_IA32_MISC_ENABLE_L1D_CONTEXT_BIT 24
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#define MSR_IA32_MISC_ENABLE_L1D_CONTEXT (1ULL << MSR_IA32_MISC_ENABLE_L1D_CONTEXT_BIT)
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE_BIT 37
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#define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE_BIT)
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#define MSR_IA32_MISC_ENABLE_TURBO_DISABLE_BIT 38
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||||
#define MSR_IA32_MISC_ENABLE_TURBO_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_TURBO_DISABLE_BIT)
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT 39
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#define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT)
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#define MSR_IA32_TSC_DEADLINE 0x000006E0
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#define MSR_IA32_MCG_EAX 0x00000180
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define MSR_IA32_MCG_EBX 0x00000181
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||||
#define MSR_IA32_MCG_ECX 0x00000182
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||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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||||
#define MSR_IA32_MCG_EDX 0x00000183
|
||||
#define MSR_IA32_MCG_ESI 0x00000184
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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||||
#define MSR_IA32_MCG_EDI 0x00000185
|
||||
#define MSR_IA32_MCG_EBP 0x00000186
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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||||
#define MSR_IA32_MCG_ESP 0x00000187
|
||||
#define MSR_IA32_MCG_EFLAGS 0x00000188
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define MSR_IA32_MCG_EIP 0x00000189
|
||||
#define MSR_IA32_MCG_RESERVED 0x0000018a
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define MSR_P4_BPU_PERFCTR0 0x00000300
|
||||
#define MSR_P4_BPU_PERFCTR1 0x00000301
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define MSR_P4_BPU_PERFCTR2 0x00000302
|
||||
#define MSR_P4_BPU_PERFCTR3 0x00000303
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define MSR_P4_MS_PERFCTR0 0x00000304
|
||||
#define MSR_P4_MS_PERFCTR1 0x00000305
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define MSR_P4_MS_PERFCTR2 0x00000306
|
||||
#define MSR_P4_MS_PERFCTR3 0x00000307
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define MSR_P4_FLAME_PERFCTR0 0x00000308
|
||||
#define MSR_P4_FLAME_PERFCTR1 0x00000309
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define MSR_P4_FLAME_PERFCTR2 0x0000030a
|
||||
#define MSR_P4_FLAME_PERFCTR3 0x0000030b
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define MSR_P4_IQ_PERFCTR0 0x0000030c
|
||||
#define MSR_P4_IQ_PERFCTR1 0x0000030d
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define MSR_P4_IQ_PERFCTR2 0x0000030e
|
||||
#define MSR_P4_IQ_PERFCTR3 0x0000030f
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define MSR_P4_IQ_PERFCTR4 0x00000310
|
||||
#define MSR_P4_IQ_PERFCTR5 0x00000311
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define MSR_P4_BPU_CCCR0 0x00000360
|
||||
#define MSR_P4_BPU_CCCR1 0x00000361
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define MSR_P4_BPU_CCCR2 0x00000362
|
||||
#define MSR_P4_BPU_CCCR3 0x00000363
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define MSR_P4_MS_CCCR0 0x00000364
|
||||
#define MSR_P4_MS_CCCR1 0x00000365
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define MSR_P4_MS_CCCR2 0x00000366
|
||||
#define MSR_P4_MS_CCCR3 0x00000367
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define MSR_P4_FLAME_CCCR0 0x00000368
|
||||
#define MSR_P4_FLAME_CCCR1 0x00000369
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define MSR_P4_FLAME_CCCR2 0x0000036a
|
||||
#define MSR_P4_FLAME_CCCR3 0x0000036b
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define MSR_P4_IQ_CCCR0 0x0000036c
|
||||
#define MSR_P4_IQ_CCCR1 0x0000036d
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define MSR_P4_IQ_CCCR2 0x0000036e
|
||||
#define MSR_P4_IQ_CCCR3 0x0000036f
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define MSR_P4_IQ_CCCR4 0x00000370
|
||||
#define MSR_P4_IQ_CCCR5 0x00000371
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define MSR_P4_ALF_ESCR0 0x000003ca
|
||||
#define MSR_P4_ALF_ESCR1 0x000003cb
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define MSR_P4_BPU_ESCR0 0x000003b2
|
||||
#define MSR_P4_BPU_ESCR1 0x000003b3
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define MSR_P4_BSU_ESCR0 0x000003a0
|
||||
#define MSR_P4_BSU_ESCR1 0x000003a1
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define MSR_P4_CRU_ESCR0 0x000003b8
|
||||
#define MSR_P4_CRU_ESCR1 0x000003b9
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define MSR_P4_CRU_ESCR2 0x000003cc
|
||||
#define MSR_P4_CRU_ESCR3 0x000003cd
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define MSR_P4_CRU_ESCR4 0x000003e0
|
||||
#define MSR_P4_CRU_ESCR5 0x000003e1
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define MSR_P4_DAC_ESCR0 0x000003a8
|
||||
#define MSR_P4_DAC_ESCR1 0x000003a9
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define MSR_P4_FIRM_ESCR0 0x000003a4
|
||||
#define MSR_P4_FIRM_ESCR1 0x000003a5
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define MSR_P4_FLAME_ESCR0 0x000003a6
|
||||
#define MSR_P4_FLAME_ESCR1 0x000003a7
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define MSR_P4_FSB_ESCR0 0x000003a2
|
||||
#define MSR_P4_FSB_ESCR1 0x000003a3
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define MSR_P4_IQ_ESCR0 0x000003ba
|
||||
#define MSR_P4_IQ_ESCR1 0x000003bb
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define MSR_P4_IS_ESCR0 0x000003b4
|
||||
#define MSR_P4_IS_ESCR1 0x000003b5
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define MSR_P4_ITLB_ESCR0 0x000003b6
|
||||
#define MSR_P4_ITLB_ESCR1 0x000003b7
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define MSR_P4_IX_ESCR0 0x000003c8
|
||||
#define MSR_P4_IX_ESCR1 0x000003c9
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define MSR_P4_MOB_ESCR0 0x000003aa
|
||||
#define MSR_P4_MOB_ESCR1 0x000003ab
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define MSR_P4_MS_ESCR0 0x000003c0
|
||||
#define MSR_P4_MS_ESCR1 0x000003c1
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define MSR_P4_PMH_ESCR0 0x000003ac
|
||||
#define MSR_P4_PMH_ESCR1 0x000003ad
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define MSR_P4_RAT_ESCR0 0x000003bc
|
||||
#define MSR_P4_RAT_ESCR1 0x000003bd
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define MSR_P4_SAAT_ESCR0 0x000003ae
|
||||
#define MSR_P4_SAAT_ESCR1 0x000003af
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define MSR_P4_SSU_ESCR0 0x000003be
|
||||
#define MSR_P4_SSU_ESCR1 0x000003bf
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define MSR_P4_TBPU_ESCR0 0x000003c2
|
||||
#define MSR_P4_TBPU_ESCR1 0x000003c3
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define MSR_P4_TC_ESCR0 0x000003c4
|
||||
#define MSR_P4_TC_ESCR1 0x000003c5
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define MSR_P4_U2L_ESCR0 0x000003b0
|
||||
#define MSR_P4_U2L_ESCR1 0x000003b1
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define MSR_P4_PEBS_MATRIX_VERT 0x000003f2
|
||||
#define MSR_CORE_PERF_FIXED_CTR0 0x00000309
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define MSR_CORE_PERF_FIXED_CTR1 0x0000030a
|
||||
#define MSR_CORE_PERF_FIXED_CTR2 0x0000030b
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define MSR_CORE_PERF_FIXED_CTR_CTRL 0x0000038d
|
||||
#define MSR_CORE_PERF_GLOBAL_STATUS 0x0000038e
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define MSR_CORE_PERF_GLOBAL_CTRL 0x0000038f
|
||||
#define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x00000390
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define MSR_GEODE_BUSCONT_CONF0 0x00001900
|
||||
#define MSR_IA32_VMX_BASIC 0x00000480
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define MSR_IA32_VMX_PINBASED_CTLS 0x00000481
|
||||
#define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define MSR_IA32_VMX_EXIT_CTLS 0x00000483
|
||||
#define MSR_IA32_VMX_ENTRY_CTLS 0x00000484
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define MSR_IA32_VMX_MISC 0x00000485
|
||||
#define MSR_IA32_VMX_CR0_FIXED0 0x00000486
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define MSR_IA32_VMX_CR0_FIXED1 0x00000487
|
||||
#define MSR_IA32_VMX_CR4_FIXED0 0x00000488
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define MSR_IA32_VMX_CR4_FIXED1 0x00000489
|
||||
#define MSR_IA32_VMX_VMCS_ENUM 0x0000048a
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b
|
||||
#define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048d
|
||||
#define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048f
|
||||
#define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define MSR_IA32_VMX_VMFUNC 0x00000491
|
||||
#define VMX_BASIC_VMCS_SIZE_SHIFT 32
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define VMX_BASIC_64 0x0001000000000000LLU
|
||||
#define VMX_BASIC_MEM_TYPE_SHIFT 50
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define VMX_BASIC_MEM_TYPE_MASK 0x003c000000000000LLU
|
||||
#define VMX_BASIC_MEM_TYPE_WB 6LLU
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define VMX_BASIC_INOUT 0x0040000000000000LLU
|
||||
#define MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS (1ULL << 29)
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define MSR_IA32_VMX_MISC_PREEMPTION_TIMER_SCALE 0x1F
|
||||
#define MSR_VM_CR 0xc0010114
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define MSR_VM_IGNNE 0xc0010115
|
||||
#define MSR_VM_HSAVE_PA 0xc0010117
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#endif
|
||||
|
||||
@@ -454,5 +454,6 @@
|
||||
#define __NR_finit_module 350
|
||||
#define __NR_sched_setattr 351
|
||||
#define __NR_sched_getattr 352
|
||||
#endif
|
||||
#define __NR_renameat2 353
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#endif
|
||||
|
||||
@@ -413,4 +413,6 @@
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define __NR_sched_setattr 314
|
||||
#define __NR_sched_getattr 315
|
||||
#define __NR_renameat2 316
|
||||
#endif
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
|
||||
@@ -247,157 +247,158 @@
|
||||
#define __NR_sched_setaffinity (__X32_SYSCALL_BIT + 203)
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define __NR_sched_getaffinity (__X32_SYSCALL_BIT + 204)
|
||||
#define __NR_io_setup (__X32_SYSCALL_BIT + 206)
|
||||
#define __NR_io_destroy (__X32_SYSCALL_BIT + 207)
|
||||
#define __NR_io_getevents (__X32_SYSCALL_BIT + 208)
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define __NR_io_submit (__X32_SYSCALL_BIT + 209)
|
||||
#define __NR_io_cancel (__X32_SYSCALL_BIT + 210)
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define __NR_lookup_dcookie (__X32_SYSCALL_BIT + 212)
|
||||
#define __NR_epoll_create (__X32_SYSCALL_BIT + 213)
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define __NR_remap_file_pages (__X32_SYSCALL_BIT + 216)
|
||||
#define __NR_getdents64 (__X32_SYSCALL_BIT + 217)
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define __NR_set_tid_address (__X32_SYSCALL_BIT + 218)
|
||||
#define __NR_restart_syscall (__X32_SYSCALL_BIT + 219)
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define __NR_semtimedop (__X32_SYSCALL_BIT + 220)
|
||||
#define __NR_fadvise64 (__X32_SYSCALL_BIT + 221)
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define __NR_timer_settime (__X32_SYSCALL_BIT + 223)
|
||||
#define __NR_timer_gettime (__X32_SYSCALL_BIT + 224)
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define __NR_timer_getoverrun (__X32_SYSCALL_BIT + 225)
|
||||
#define __NR_timer_delete (__X32_SYSCALL_BIT + 226)
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define __NR_clock_settime (__X32_SYSCALL_BIT + 227)
|
||||
#define __NR_clock_gettime (__X32_SYSCALL_BIT + 228)
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define __NR_clock_getres (__X32_SYSCALL_BIT + 229)
|
||||
#define __NR_clock_nanosleep (__X32_SYSCALL_BIT + 230)
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define __NR_exit_group (__X32_SYSCALL_BIT + 231)
|
||||
#define __NR_epoll_wait (__X32_SYSCALL_BIT + 232)
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define __NR_epoll_ctl (__X32_SYSCALL_BIT + 233)
|
||||
#define __NR_tgkill (__X32_SYSCALL_BIT + 234)
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define __NR_utimes (__X32_SYSCALL_BIT + 235)
|
||||
#define __NR_mbind (__X32_SYSCALL_BIT + 237)
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define __NR_set_mempolicy (__X32_SYSCALL_BIT + 238)
|
||||
#define __NR_get_mempolicy (__X32_SYSCALL_BIT + 239)
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define __NR_mq_open (__X32_SYSCALL_BIT + 240)
|
||||
#define __NR_mq_unlink (__X32_SYSCALL_BIT + 241)
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define __NR_mq_timedsend (__X32_SYSCALL_BIT + 242)
|
||||
#define __NR_mq_timedreceive (__X32_SYSCALL_BIT + 243)
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define __NR_mq_getsetattr (__X32_SYSCALL_BIT + 245)
|
||||
#define __NR_add_key (__X32_SYSCALL_BIT + 248)
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define __NR_request_key (__X32_SYSCALL_BIT + 249)
|
||||
#define __NR_keyctl (__X32_SYSCALL_BIT + 250)
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define __NR_ioprio_set (__X32_SYSCALL_BIT + 251)
|
||||
#define __NR_ioprio_get (__X32_SYSCALL_BIT + 252)
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define __NR_inotify_init (__X32_SYSCALL_BIT + 253)
|
||||
#define __NR_inotify_add_watch (__X32_SYSCALL_BIT + 254)
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define __NR_inotify_rm_watch (__X32_SYSCALL_BIT + 255)
|
||||
#define __NR_migrate_pages (__X32_SYSCALL_BIT + 256)
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define __NR_openat (__X32_SYSCALL_BIT + 257)
|
||||
#define __NR_mkdirat (__X32_SYSCALL_BIT + 258)
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define __NR_mknodat (__X32_SYSCALL_BIT + 259)
|
||||
#define __NR_fchownat (__X32_SYSCALL_BIT + 260)
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define __NR_futimesat (__X32_SYSCALL_BIT + 261)
|
||||
#define __NR_newfstatat (__X32_SYSCALL_BIT + 262)
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define __NR_unlinkat (__X32_SYSCALL_BIT + 263)
|
||||
#define __NR_renameat (__X32_SYSCALL_BIT + 264)
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define __NR_linkat (__X32_SYSCALL_BIT + 265)
|
||||
#define __NR_symlinkat (__X32_SYSCALL_BIT + 266)
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define __NR_readlinkat (__X32_SYSCALL_BIT + 267)
|
||||
#define __NR_fchmodat (__X32_SYSCALL_BIT + 268)
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define __NR_faccessat (__X32_SYSCALL_BIT + 269)
|
||||
#define __NR_pselect6 (__X32_SYSCALL_BIT + 270)
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define __NR_ppoll (__X32_SYSCALL_BIT + 271)
|
||||
#define __NR_unshare (__X32_SYSCALL_BIT + 272)
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define __NR_splice (__X32_SYSCALL_BIT + 275)
|
||||
#define __NR_tee (__X32_SYSCALL_BIT + 276)
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define __NR_sync_file_range (__X32_SYSCALL_BIT + 277)
|
||||
#define __NR_utimensat (__X32_SYSCALL_BIT + 280)
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define __NR_epoll_pwait (__X32_SYSCALL_BIT + 281)
|
||||
#define __NR_signalfd (__X32_SYSCALL_BIT + 282)
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define __NR_timerfd_create (__X32_SYSCALL_BIT + 283)
|
||||
#define __NR_eventfd (__X32_SYSCALL_BIT + 284)
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define __NR_fallocate (__X32_SYSCALL_BIT + 285)
|
||||
#define __NR_timerfd_settime (__X32_SYSCALL_BIT + 286)
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define __NR_timerfd_gettime (__X32_SYSCALL_BIT + 287)
|
||||
#define __NR_accept4 (__X32_SYSCALL_BIT + 288)
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define __NR_signalfd4 (__X32_SYSCALL_BIT + 289)
|
||||
#define __NR_eventfd2 (__X32_SYSCALL_BIT + 290)
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define __NR_epoll_create1 (__X32_SYSCALL_BIT + 291)
|
||||
#define __NR_dup3 (__X32_SYSCALL_BIT + 292)
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define __NR_pipe2 (__X32_SYSCALL_BIT + 293)
|
||||
#define __NR_inotify_init1 (__X32_SYSCALL_BIT + 294)
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define __NR_perf_event_open (__X32_SYSCALL_BIT + 298)
|
||||
#define __NR_fanotify_init (__X32_SYSCALL_BIT + 300)
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define __NR_fanotify_mark (__X32_SYSCALL_BIT + 301)
|
||||
#define __NR_prlimit64 (__X32_SYSCALL_BIT + 302)
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define __NR_name_to_handle_at (__X32_SYSCALL_BIT + 303)
|
||||
#define __NR_open_by_handle_at (__X32_SYSCALL_BIT + 304)
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define __NR_clock_adjtime (__X32_SYSCALL_BIT + 305)
|
||||
#define __NR_syncfs (__X32_SYSCALL_BIT + 306)
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define __NR_setns (__X32_SYSCALL_BIT + 308)
|
||||
#define __NR_getcpu (__X32_SYSCALL_BIT + 309)
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define __NR_kcmp (__X32_SYSCALL_BIT + 312)
|
||||
#define __NR_finit_module (__X32_SYSCALL_BIT + 313)
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define __NR_sched_setattr (__X32_SYSCALL_BIT + 314)
|
||||
#define __NR_sched_getattr (__X32_SYSCALL_BIT + 315)
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define __NR_renameat2 (__X32_SYSCALL_BIT + 316)
|
||||
#define __NR_rt_sigaction (__X32_SYSCALL_BIT + 512)
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define __NR_rt_sigreturn (__X32_SYSCALL_BIT + 513)
|
||||
#define __NR_ioctl (__X32_SYSCALL_BIT + 514)
|
||||
#define __NR_readv (__X32_SYSCALL_BIT + 515)
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define __NR_writev (__X32_SYSCALL_BIT + 516)
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define __NR_recvfrom (__X32_SYSCALL_BIT + 517)
|
||||
#define __NR_sendmsg (__X32_SYSCALL_BIT + 518)
|
||||
#define __NR_recvmsg (__X32_SYSCALL_BIT + 519)
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define __NR_execve (__X32_SYSCALL_BIT + 520)
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define __NR_ptrace (__X32_SYSCALL_BIT + 521)
|
||||
#define __NR_rt_sigpending (__X32_SYSCALL_BIT + 522)
|
||||
#define __NR_rt_sigtimedwait (__X32_SYSCALL_BIT + 523)
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define __NR_rt_sigqueueinfo (__X32_SYSCALL_BIT + 524)
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define __NR_sigaltstack (__X32_SYSCALL_BIT + 525)
|
||||
#define __NR_timer_create (__X32_SYSCALL_BIT + 526)
|
||||
#define __NR_mq_notify (__X32_SYSCALL_BIT + 527)
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define __NR_kexec_load (__X32_SYSCALL_BIT + 528)
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define __NR_waitid (__X32_SYSCALL_BIT + 529)
|
||||
#define __NR_set_robust_list (__X32_SYSCALL_BIT + 530)
|
||||
#define __NR_get_robust_list (__X32_SYSCALL_BIT + 531)
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define __NR_vmsplice (__X32_SYSCALL_BIT + 532)
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define __NR_move_pages (__X32_SYSCALL_BIT + 533)
|
||||
#define __NR_preadv (__X32_SYSCALL_BIT + 534)
|
||||
#define __NR_pwritev (__X32_SYSCALL_BIT + 535)
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define __NR_rt_tgsigqueueinfo (__X32_SYSCALL_BIT + 536)
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define __NR_recvmmsg (__X32_SYSCALL_BIT + 537)
|
||||
#define __NR_sendmmsg (__X32_SYSCALL_BIT + 538)
|
||||
#define __NR_process_vm_readv (__X32_SYSCALL_BIT + 539)
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define __NR_process_vm_writev (__X32_SYSCALL_BIT + 540)
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define __NR_setsockopt (__X32_SYSCALL_BIT + 541)
|
||||
#define __NR_getsockopt (__X32_SYSCALL_BIT + 542)
|
||||
#endif
|
||||
#define __NR_io_setup (__X32_SYSCALL_BIT + 543)
|
||||
#define __NR_io_submit (__X32_SYSCALL_BIT + 544)
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#endif
|
||||
|
||||
@@ -24,11 +24,6 @@ enum vsyscall_num {
|
||||
__NR_vtime,
|
||||
__NR_vgetcpu,
|
||||
};
|
||||
#define VSYSCALL_START (-10UL << 20)
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define VSYSCALL_SIZE 1024
|
||||
#define VSYSCALL_END (-2UL << 20)
|
||||
#define VSYSCALL_MAPPED_PAGES 1
|
||||
#define VSYSCALL_ADDR(vsyscall_nr) (VSYSCALL_START+VSYSCALL_SIZE*(vsyscall_nr))
|
||||
#define VSYSCALL_ADDR (-10UL << 20)
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#endif
|
||||
|
||||
Reference in New Issue
Block a user