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am d520c95e: am bb4f6dc2: Merge "ARM: Change dmb domain for bionic_atomic_barrier()"

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* commit 'd520c95e457fb81522491b7e50dc736e81e9bbd1':
  ARM: Change dmb domain for bionic_atomic_barrier()
This commit is contained in:
Elliott Hughes 2013-12-19 19:51:14 +00:00 committed by Android Git Automerger
commit b0ad47e20d
4 changed files with 5 additions and 5 deletions
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2
libc/private/bionic_atomic_aarch64.h
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@ -17,7 +17,7 @@
#define BIONIC_ATOMIC_AARCH64_H #define BIONIC_ATOMIC_AARCH64_H
/* For ARMv8, we can use the 'dmb' instruction directly */ /* For ARMv8, we can use the 'dmb' instruction directly */
__ATOMIC_INLINE__ void __bionic_memory_barrier(void) { __ATOMIC_INLINE__ void __bionic_memory_barrier() {
__asm__ __volatile__ ( "dmb ish" : : : "memory" ); __asm__ __volatile__ ( "dmb ish" : : : "memory" );
} }

4
libc/private/bionic_atomic_arm.h
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@ -16,9 +16,9 @@
#ifndef BIONIC_ATOMIC_ARM_H #ifndef BIONIC_ATOMIC_ARM_H
#define BIONIC_ATOMIC_ARM_H #define BIONIC_ATOMIC_ARM_H
__ATOMIC_INLINE__ void __bionic_memory_barrier(void) { __ATOMIC_INLINE__ void __bionic_memory_barrier() {
#if defined(ANDROID_SMP) && ANDROID_SMP == 1 #if defined(ANDROID_SMP) && ANDROID_SMP == 1
__asm__ __volatile__ ( "dmb" : : : "memory" ); __asm__ __volatile__ ( "dmb ish" : : : "memory" );
#else #else
/* A simple compiler barrier. */ /* A simple compiler barrier. */
__asm__ __volatile__ ( "" : : : "memory" ); __asm__ __volatile__ ( "" : : : "memory" );

2
libc/private/bionic_atomic_gcc_builtin.h
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@ -25,7 +25,7 @@
* the architecture-specific assembler versions. * the architecture-specific assembler versions.
*/ */
__ATOMIC_INLINE__ void __bionic_memory_barrier(void) { __ATOMIC_INLINE__ void __bionic_memory_barrier() {
__sync_synchronize(); __sync_synchronize();
} }

2
libc/private/bionic_atomic_inline.h
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@ -25,7 +25,7 @@
* *
* Macros defined in this header: * Macros defined in this header:
* *
* void ANDROID_MEMBAR_FULL(void) * void ANDROID_MEMBAR_FULL()
* Full memory barrier. Provides a compiler reordering barrier, and * Full memory barrier. Provides a compiler reordering barrier, and
* on SMP systems emits an appropriate instruction. * on SMP systems emits an appropriate instruction.
*/ */