* commit 'd520c95e457fb81522491b7e50dc736e81e9bbd1': ARM: Change dmb domain for bionic_atomic_barrier()
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commit
b0ad47e20d
@ -17,7 +17,7 @@
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#define BIONIC_ATOMIC_AARCH64_H
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/* For ARMv8, we can use the 'dmb' instruction directly */
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__ATOMIC_INLINE__ void __bionic_memory_barrier(void) {
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__ATOMIC_INLINE__ void __bionic_memory_barrier() {
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__asm__ __volatile__ ( "dmb ish" : : : "memory" );
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}
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@ -16,9 +16,9 @@
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#ifndef BIONIC_ATOMIC_ARM_H
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#define BIONIC_ATOMIC_ARM_H
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__ATOMIC_INLINE__ void __bionic_memory_barrier(void) {
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__ATOMIC_INLINE__ void __bionic_memory_barrier() {
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#if defined(ANDROID_SMP) && ANDROID_SMP == 1
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__asm__ __volatile__ ( "dmb" : : : "memory" );
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__asm__ __volatile__ ( "dmb ish" : : : "memory" );
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#else
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/* A simple compiler barrier. */
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__asm__ __volatile__ ( "" : : : "memory" );
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@ -25,7 +25,7 @@
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* the architecture-specific assembler versions.
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*/
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__ATOMIC_INLINE__ void __bionic_memory_barrier(void) {
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__ATOMIC_INLINE__ void __bionic_memory_barrier() {
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__sync_synchronize();
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}
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@ -25,7 +25,7 @@
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*
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* Macros defined in this header:
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*
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* void ANDROID_MEMBAR_FULL(void)
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* void ANDROID_MEMBAR_FULL()
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* Full memory barrier. Provides a compiler reordering barrier, and
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* on SMP systems emits an appropriate instruction.
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*/
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