* commit 'c0aba7c5ad7535ca5edd0a6683dd4a483701fee9': Remove remaining bionic support for TARGET_CPU_SMP being false.
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		@@ -548,13 +548,6 @@ ifneq ($(BOARD_MALLOC_ALIGNMENT),)
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  libc_common_cflags += -DMALLOC_ALIGNMENT=$(BOARD_MALLOC_ALIGNMENT)
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					  libc_common_cflags += -DMALLOC_ALIGNMENT=$(BOARD_MALLOC_ALIGNMENT)
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endif
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					endif
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# Define ANDROID_SMP appropriately.
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ifeq ($(TARGET_CPU_SMP),true)
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    libc_common_cflags += -DANDROID_SMP=1
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else
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    libc_common_cflags += -DANDROID_SMP=0
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endif
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# Define some common conlyflags
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					# Define some common conlyflags
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libc_common_conlyflags := \
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					libc_common_conlyflags := \
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    -std=gnu99
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					    -std=gnu99
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@@ -17,12 +17,7 @@
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#define BIONIC_ATOMIC_ARM_H
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					#define BIONIC_ATOMIC_ARM_H
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__ATOMIC_INLINE__ void __bionic_memory_barrier() {
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					__ATOMIC_INLINE__ void __bionic_memory_barrier() {
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#if defined(ANDROID_SMP) && ANDROID_SMP == 1
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  __asm__ __volatile__ ( "dmb ish" : : : "memory" );
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					  __asm__ __volatile__ ( "dmb ish" : : : "memory" );
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#else
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  /* A simple compiler barrier. */
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  __asm__ __volatile__ ( "" : : : "memory" );
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#endif
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}
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					}
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/* Compare-and-swap, without any explicit barriers. Note that this function
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					/* Compare-and-swap, without any explicit barriers. Note that this function
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@@ -30,10 +30,6 @@
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 *   on SMP systems emits an appropriate instruction.
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					 *   on SMP systems emits an appropriate instruction.
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 */
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					 */
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#if !defined(ANDROID_SMP)
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# error "Must define ANDROID_SMP before including atomic-inline.h"
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#endif
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#ifdef __cplusplus
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					#ifdef __cplusplus
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extern "C" {
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					extern "C" {
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#endif
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					#endif
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@@ -21,12 +21,7 @@
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 */
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					 */
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__ATOMIC_INLINE__ void __bionic_memory_barrier() {
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					__ATOMIC_INLINE__ void __bionic_memory_barrier() {
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#if defined(ANDROID_SMP) && ANDROID_SMP == 1
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  __asm__ __volatile__ ( "sync" : : : "memory" );
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					  __asm__ __volatile__ ( "sync" : : : "memory" );
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#else
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  /* A simple compiler barrier. */
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  __asm__ __volatile__ ( "" : : : "memory" );
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#endif
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}
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					}
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/* Compare-and-swap, without any explicit barriers. Note that this function
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					/* Compare-and-swap, without any explicit barriers. Note that this function
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@@ -20,12 +20,7 @@
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 * platform for a multi-core device.
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					 * platform for a multi-core device.
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 */
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					 */
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__ATOMIC_INLINE__ void __bionic_memory_barrier() {
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					__ATOMIC_INLINE__ void __bionic_memory_barrier() {
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#if defined(ANDROID_SMP) && ANDROID_SMP == 1
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  __asm__ __volatile__ ( "mfence" : : : "memory" );
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					  __asm__ __volatile__ ( "mfence" : : : "memory" );
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#else
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  /* A simple compiler barrier. */
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  __asm__ __volatile__ ( "" : : : "memory" );
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#endif
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}
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					}
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/* Compare-and-swap, without any explicit barriers. Note that this function
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					/* Compare-and-swap, without any explicit barriers. Note that this function
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