am d518a6d3
: Merge "Fix the 16 bit/32 bit instruction check for arm."
* commit 'd518a6d3bccc82cffb61fb7615b8ba09a564dec0': Fix the 16 bit/32 bit instruction check for arm.
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@ -90,15 +90,22 @@ static _Unwind_Reason_Code trace_function(__unwind_context* context, void* arg)
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// Modify the pc to point at the real function.
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if (ip != 0) {
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#if defined(__arm__)
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// We need to do a quick check here to find out if the previous
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// instruction is a Thumb-mode BLX(2). If so subtract 2 otherwise
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// 4 from PC.
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short* ptr = reinterpret_cast<short*>(ip);
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// Thumb BLX(2)
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if ((*(ptr-1) & 0xff80) == 0x4780) {
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ip -= 2;
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} else {
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ip -= 4;
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// If the ip is suspiciously low, do nothing to avoid a segfault trying
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// to access this memory.
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if (ip >= 4096) {
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// Check bits [15:11] of the first halfword assuming the instruction
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// is 32 bits long. If the bits are any of these values, then our
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// assumption was correct:
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// b11101
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// b11110
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// b11111
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// Otherwise, this is a 16 bit instruction.
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uint16_t value = (*reinterpret_cast<uint16_t*>(ip - 2)) >> 11;
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if (value == 0x1f || value == 0x1e || value == 0x1d) {
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ip -= 4;
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} else {
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ip -= 2;
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}
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}
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#elif defined(__aarch64__)
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// All instructions are 4 bytes long, skip back one instruction.
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