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[MIPS64] libc/libm support

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libc/libm support for MIPS64 targets

Change-Id: I8271941d418612a286be55495f0e95822f90004f
Signed-off-by: Chris Dearman <chris.dearman@imgtec.com>
Signed-off-by: Raghu Gandham <raghu.gandham@imgtec.com>
This commit is contained in:
Chris Dearman
2014-02-05 18:51:43 -08:00
committed by Elliott Hughes
parent 5036935c41
commit 645d0312c2
38 changed files with 3901 additions and 38 deletions
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305
libc/arch-mips64/include/machine/asm.h Normal file
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/* $OpenBSD: asm.h,v 1.7 2004/10/20 12:49:15 pefo Exp $ */
/*
* Copyright (c) 2001-2002 Opsycon AB (www.opsycon.se / www.opsycon.com)
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
*/
#ifndef _MIPS64_ASM_H
#define _MIPS64_ASM_H
#include <machine/regdef.h>
#ifdef NEED_OLD_RM7KFIX
#define ITLBNOPFIX nop;nop;nop;nop;nop;nop;nop;nop;nop;nop;
#else
#define ITLBNOPFIX nop;nop;nop;nop
#endif
#define _MIPS_ISA_MIPS1 1 /* R2000/R3000 */
#define _MIPS_ISA_MIPS2 2 /* R4000/R6000 */
#define _MIPS_ISA_MIPS3 3 /* R4000 */
#define _MIPS_ISA_MIPS4 4 /* TFP (R1x000) */
#ifdef __linux__
#define _MIPS_ISA_MIPS5 5
#define _MIPS_ISA_MIPS32 6
#define _MIPS_ISA_MIPS64 7
#else
#define _MIPS_ISA_MIPS32 32 /* MIPS32 */
#endif
#if !defined(ABICALLS) && !defined(_NO_ABICALLS)
#define ABICALLS .abicalls
#endif
#if defined(ABICALLS) && !defined(_KERNEL)
ABICALLS
#endif
#define _C_LABEL(x) x /* XXX Obsolete but keep for a while */
#if !defined(__MIPSEL__) && !defined(__MIPSEB__)
#error "__MIPSEL__ or __MIPSEB__ must be defined"
#endif
/*
* Define how to access unaligned data word
*/
#if defined(__MIPSEL__)
#define LWLO lwl
#define LWHI lwr
#define SWLO swl
#define SWHI swr
#define LDLO ldl
#define LDHI ldr
#define SDLO sdl
#define SDHI sdr
#endif
#if defined(__MIPSEB__)
#define LWLO lwr
#define LWHI lwl
#define SWLO swr
#define SWHI swl
#define LDLO ldr
#define LDHI ldl
#define SDLO sdr
#define SDHI sdl
#endif
/*
* Define programming environment for ABI.
*/
#if defined(ABICALLS) && !defined(_KERNEL) && !defined(_STANDALONE)
#ifndef _MIPS_SIM
#define _MIPS_SIM 1
#define _ABIO32 1
#endif
#ifndef _MIPS_ISA
#define _MIPS_ISA 2
#define _MIPS_ISA_MIPS2 2
#endif
#if (_MIPS_SIM == _ABIO32) || (_MIPS_SIM == _ABI32)
#define NARGSAVE 4
#define SETUP_GP \
.set noreorder; \
.cpload t9; \
.set reorder;
#define SAVE_GP(x) \
.cprestore x
#define SETUP_GP64(gpoff, name)
#define RESTORE_GP64
#endif
#if (_MIPS_SIM == _ABI64) || (_MIPS_SIM == _ABIN32)
#define NARGSAVE 0
#define SETUP_GP
#define SAVE_GP(x)
#define SETUP_GP64(gpoff, name) \
.cpsetup t9, gpoff, name
#define RESTORE_GP64 \
.cpreturn
#endif
#define MKFSIZ(narg,locals) (((narg+locals)*REGSZ+31)&(~31))
#else /* defined(ABICALLS) && !defined(_KERNEL) */
#define NARGSAVE 4
#define SETUP_GP
#define SAVE_GP(x)
#define ALIGNSZ 16 /* Stack layout alignment */
#define FRAMESZ(sz) (((sz) + (ALIGNSZ-1)) & ~(ALIGNSZ-1))
#endif
/*
* Basic register operations based on selected ISA
*/
#if (_MIPS_ISA == _MIPS_ISA_MIPS1 || _MIPS_ISA == _MIPS_ISA_MIPS2 || _MIPS_ISA == _MIPS_ISA_MIPS32)
#define REGSZ 4 /* 32 bit mode register size */
#define LOGREGSZ 2 /* log rsize */
#define REG_S sw
#define REG_L lw
#define CF_SZ 24 /* Call frame size */
#define CF_ARGSZ 16 /* Call frame arg size */
#define CF_RA_OFFS 20 /* Call ra save offset */
#endif
#if (_MIPS_ISA == _MIPS_ISA_MIPS3 || _MIPS_ISA == _MIPS_ISA_MIPS4 || _MIPS_ISA == _MIPS_ISA_MIPS64)
#define REGSZ 8 /* 64 bit mode register size */
#define LOGREGSZ 3 /* log rsize */
#define REG_S sd
#define REG_L ld
#define CF_SZ 48 /* Call frame size (multiple of ALIGNSZ) */
#define CF_ARGSZ 32 /* Call frame arg size */
#define CF_RA_OFFS 40 /* Call ra save offset */
#endif
#define REGSZ_FP 8 /* 64 bit FP register size */
#ifndef __LP64__
#define PTR_L lw
#define PTR_S sw
#define PTR_SUB sub
#define PTR_ADD add
#define PTR_SUBU subu
#define PTR_ADDU addu
#define LI li
#define LA la
#define PTR_SLL sll
#define PTR_SRL srl
#define PTR_VAL .word
#else
#define PTR_L ld
#define PTR_S sd
#define PTR_ADD dadd
#define PTR_SUB dsub
#define PTR_SUBU dsubu
#define PTR_ADDU daddu
#define LI dli
#define LA dla
#define PTR_SLL dsll
#define PTR_SRL dsrl
#define PTR_VAL .dword
#endif
/*
* Define -pg profile entry code.
*/
#if defined(XGPROF) || defined(XPROF)
#define MCOUNT \
PTR_SUBU sp, sp, 64; \
SAVE_GP(16); \
sd ra, 56(sp); \
sd gp, 48(sp); \
.set noat; \
.set noreorder; \
move AT, ra; \
jal _mcount; \
PTR_SUBU sp, sp, 16; \
ld ra, 56(sp); \
PTR_ADDU sp, sp, 64; \
.set reorder; \
.set at;
#else
#define MCOUNT
#endif
/*
* LEAF(x, fsize)
*
* Declare a leaf routine.
*/
#define LEAF(x, fsize) \
.align 3; \
.globl x; \
.ent x, 0; \
x: ; \
.frame sp, fsize, ra; \
SETUP_GP \
MCOUNT
#define ALEAF(x) \
.globl x; \
x:
/*
* NLEAF(x)
*
* Declare a non-profiled leaf routine.
*/
#define NLEAF(x, fsize) \
.align 3; \
.globl x; \
.ent x, 0; \
x: ; \
.frame sp, fsize, ra; \
SETUP_GP
/*
* NON_LEAF(x)
*
* Declare a non-leaf routine (a routine that makes other C calls).
*/
#define NON_LEAF(x, fsize, retpc) \
.align 3; \
.globl x; \
.ent x, 0; \
x: ; \
.frame sp, fsize, retpc; \
SETUP_GP \
MCOUNT
/*
* NNON_LEAF(x)
*
* Declare a non-profiled non-leaf routine
* (a routine that makes other C calls).
*/
#define NNON_LEAF(x, fsize, retpc) \
.align 3; \
.globl x; \
.ent x, 0; \
x: ; \
.frame sp, fsize, retpc \
SETUP_GP
/*
* END(x)
*
* Mark end of a procedure.
*/
#define END(x) \
.end x
/*
* Macros to panic and printf from assembly language.
*/
#define PANIC(msg) \
LA a0, 9f; \
jal panic; \
nop ; \
MSG(msg)
#define PRINTF(msg) \
LA a0, 9f; \
jal printf; \
nop ; \
MSG(msg)
#define MSG(msg) \
.rdata; \
9: .asciiz msg; \
.text
#define ASMSTR(str) \
.asciiz str; \
.align 3
#endif /* !_MIPS_ASM_H */

196
libc/arch-mips64/include/machine/elf_machdep.h Normal file
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/* $NetBSD: elf_machdep.h,v 1.15 2011/03/15 07:39:22 matt Exp $ */
#ifndef _MIPS_ELF_MACHDEP_H_
#define _MIPS_ELF_MACHDEP_H_
#ifdef _LP64
#define ARCH_ELFSIZE 64 /* MD native binary size */
#else
#define ARCH_ELFSIZE 32 /* MD native binary size */
#endif
#if ELFSIZE == 32
#define ELF32_MACHDEP_ID_CASES \
case EM_MIPS: \
break;
#define ELF32_MACHDEP_ID EM_MIPS
#elif ELFSIZE == 64
#define ELF64_MACHDEP_ID_CASES \
case EM_MIPS: \
break;
#define ELF64_MACHDEP_ID EM_MIPS
#endif
/* mips relocs. */
#define R_MIPS_NONE 0
#define R_MIPS_16 1
#define R_MIPS_32 2
#define R_MIPS_REL32 3
#define R_MIPS_REL R_MIPS_REL32
#define R_MIPS_26 4
#define R_MIPS_HI16 5 /* high 16 bits of symbol value */
#define R_MIPS_LO16 6 /* low 16 bits of symbol value */
#define R_MIPS_GPREL16 7 /* GP-relative reference */
#define R_MIPS_LITERAL 8 /* Reference to literal section */
#define R_MIPS_GOT16 9 /* Reference to global offset table */
#define R_MIPS_GOT R_MIPS_GOT16
#define R_MIPS_PC16 10 /* 16 bit PC relative reference */
#define R_MIPS_CALL16 11 /* 16 bit call thru glbl offset tbl */
#define R_MIPS_CALL R_MIPS_CALL16
#define R_MIPS_GPREL32 12
/* 13, 14, 15 are not defined at this point. */
#define R_MIPS_UNUSED1 13
#define R_MIPS_UNUSED2 14
#define R_MIPS_UNUSED3 15
/*
* The remaining relocs are apparently part of the 64-bit Irix ELF ABI.
*/
#define R_MIPS_SHIFT5 16
#define R_MIPS_SHIFT6 17
#define R_MIPS_64 18
#define R_MIPS_GOT_DISP 19
#define R_MIPS_GOT_PAGE 20
#define R_MIPS_GOT_OFST 21
#define R_MIPS_GOT_HI16 22
#define R_MIPS_GOT_LO16 23
#define R_MIPS_SUB 24
#define R_MIPS_INSERT_A 25
#define R_MIPS_INSERT_B 26
#define R_MIPS_DELETE 27
#define R_MIPS_HIGHER 28
#define R_MIPS_HIGHEST 29
#define R_MIPS_CALL_HI16 30
#define R_MIPS_CALL_LO16 31
#define R_MIPS_SCN_DISP 32
#define R_MIPS_REL16 33
#define R_MIPS_ADD_IMMEDIATE 34
#define R_MIPS_PJUMP 35
#define R_MIPS_RELGOT 36
#define R_MIPS_JALR 37
/* TLS relocations */
#define R_MIPS_TLS_DTPMOD32 38 /* Module number 32 bit */
#define R_MIPS_TLS_DTPREL32 39 /* Module-relative offset 32 bit */
#define R_MIPS_TLS_DTPMOD64 40 /* Module number 64 bit */
#define R_MIPS_TLS_DTPREL64 41 /* Module-relative offset 64 bit */
#define R_MIPS_TLS_GD 42 /* 16 bit GOT offset for GD */
#define R_MIPS_TLS_LDM 43 /* 16 bit GOT offset for LDM */
#define R_MIPS_TLS_DTPREL_HI16 44 /* Module-relative offset, high 16 bits */
#define R_MIPS_TLS_DTPREL_LO16 45 /* Module-relative offset, low 16 bits */
#define R_MIPS_TLS_GOTTPREL 46 /* 16 bit GOT offset for IE */
#define R_MIPS_TLS_TPREL32 47 /* TP-relative offset, 32 bit */
#define R_MIPS_TLS_TPREL64 48 /* TP-relative offset, 64 bit */
#define R_MIPS_TLS_TPREL_HI16 49 /* TP-relative offset, high 16 bits */
#define R_MIPS_TLS_TPREL_LO16 50 /* TP-relative offset, low 16 bits */
#define R_MIPS_max 51
#define R_TYPE(name) __CONCAT(R_MIPS_,name)
#define R_MIPS16_min 100
#define R_MIPS16_26 100
#define R_MIPS16_GPREL 101
#define R_MIPS16_GOT16 102
#define R_MIPS16_CALL16 103
#define R_MIPS16_HI16 104
#define R_MIPS16_LO16 105
#define R_MIPS16_max 106
/* mips dynamic tags */
#define DT_MIPS_RLD_VERSION 0x70000001
#define DT_MIPS_TIME_STAMP 0x70000002
#define DT_MIPS_ICHECKSUM 0x70000003
#define DT_MIPS_IVERSION 0x70000004
#define DT_MIPS_FLAGS 0x70000005
#define DT_MIPS_BASE_ADDRESS 0x70000006
#define DT_MIPS_CONFLICT 0x70000008
#define DT_MIPS_LIBLIST 0x70000009
#define DT_MIPS_CONFLICTNO 0x7000000b
#define DT_MIPS_LOCAL_GOTNO 0x7000000a /* number of local got ents */
#define DT_MIPS_LIBLISTNO 0x70000010
#define DT_MIPS_SYMTABNO 0x70000011 /* number of .dynsym entries */
#define DT_MIPS_UNREFEXTNO 0x70000012
#define DT_MIPS_GOTSYM 0x70000013 /* first dynamic sym in got */
#define DT_MIPS_HIPAGENO 0x70000014
#define DT_MIPS_RLD_MAP 0x70000016 /* address of loader map */
/*
* ELF Flags
*/
#define EF_MIPS_PIC 0x00000002 /* Contains PIC code */
#define EF_MIPS_CPIC 0x00000004 /* STD PIC calling sequence */
#define EF_MIPS_ABI2 0x00000020 /* N32 */
#define EF_MIPS_ARCH_ASE 0x0f000000 /* Architectural extensions */
#define EF_MIPS_ARCH_MDMX 0x08000000 /* MDMX multimedia extension */
#define EF_MIPS_ARCH_M16 0x04000000 /* MIPS-16 ISA extensions */
#define EF_MIPS_ARCH 0xf0000000 /* Architecture field */
#define EF_MIPS_ARCH_1 0x00000000 /* -mips1 code */
#define EF_MIPS_ARCH_2 0x10000000 /* -mips2 code */
#define EF_MIPS_ARCH_3 0x20000000 /* -mips3 code */
#define EF_MIPS_ARCH_4 0x30000000 /* -mips4 code */
#define EF_MIPS_ARCH_5 0x40000000 /* -mips5 code */
#define EF_MIPS_ARCH_32 0x50000000 /* -mips32 code */
#define EF_MIPS_ARCH_64 0x60000000 /* -mips64 code */
#define EF_MIPS_ARCH_32R2 0x70000000 /* -mips32r2 code */
#define EF_MIPS_ARCH_64R2 0x80000000 /* -mips64r2 code */
#define EF_MIPS_ABI 0x0000f000
#define EF_MIPS_ABI_O32 0x00001000
#define EF_MIPS_ABI_O64 0x00002000
#define EF_MIPS_ABI_EABI32 0x00003000
#define EF_MIPS_ABI_EABI64 0x00004000
#if defined(__MIPSEB__)
#define ELF32_MACHDEP_ENDIANNESS ELFDATA2MSB
#define ELF64_MACHDEP_ENDIANNESS ELFDATA2MSB
#elif defined(__MIPSEL__)
#define ELF32_MACHDEP_ENDIANNESS ELFDATA2LSB
#define ELF64_MACHDEP_ENDIANNESS ELFDATA2LSB
#elif !defined(HAVE_NBTOOL_CONFIG_H)
#error neither __MIPSEL__ nor __MIPSEB__ are defined.
#endif
#ifdef _KERNEL
#ifdef _KERNEL_OPT
#include "opt_compat_netbsd.h"
#endif
#ifdef COMPAT_16
/*
* Up to 1.6, the ELF dynamic loader (ld.elf_so) was not relocatable.
* Tell the kernel ELF exec code not to try relocating the interpreter
* for dynamically-linked ELF binaries.
*/
#define ELF_INTERP_NON_RELOCATABLE
#endif /* COMPAT_16 */
/*
* We need to be able to include the ELF header so we can pick out the
* ABI being used.
*/
#ifdef ELFSIZE
#define ELF_MD_PROBE_FUNC ELFNAME2(mips_netbsd,probe)
#define ELF_MD_COREDUMP_SETUP ELFNAME2(coredump,setup)
#endif
struct exec_package;
int mips_netbsd_elf32_probe(struct lwp *, struct exec_package *, void *, char *,
vaddr_t *);
void coredump_elf32_setup(struct lwp *, void *);
int mips_netbsd_elf64_probe(struct lwp *, struct exec_package *, void *, char *,
vaddr_t *);
void coredump_elf64_setup(struct lwp *, void *);
#endif /* _KERNEL */
#endif /* _MIPS_ELF_MACHDEP_H_ */

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libc/arch-mips64/include/machine/endian.h Normal file
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/* $OpenBSD: endian.h,v 1.5 2006/02/27 23:35:59 miod Exp $ */
/*
* Copyright (c) 2001-2002 Opsycon AB (www.opsycon.se / www.opsycon.com)
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
*/
#ifndef _MIPS64_ENDIAN_H_
#define _MIPS64_ENDIAN_H_
#ifdef __GNUC__
#if defined(__mips_isa_rev) && (__mips_isa_rev >= 2)
#define __swap16md(x) ({ \
register uint16_t _x = (x); \
register uint16_t _r; \
__asm volatile ("wsbh %0, %1" : "=r" (_r) : "r" (_x)); \
_r; \
})
#define __swap32md(x) ({ \
register uint32_t _x = (x); \
register uint32_t _r; \
__asm volatile ("wsbh %0, %1; rotr %0, %0, 16" : "=r" (_r) : "r" (_x)); \
_r; \
})
#define __swap64md(x) ({ \
uint64_t _swap64md_x = (x); \
(uint64_t) __swap32md(_swap64md_x >> 32) | \
(uint64_t) __swap32md(_swap64md_x & 0xffffffff) << 32; \
})
/* Tell sys/endian.h we have MD variants of the swap macros. */
#define MD_SWAP
#endif /* __mips32r2__ */
#endif /* __GNUC__ */
#if defined(__MIPSEB__)
#define _BYTE_ORDER _BIG_ENDIAN
#else
#define _BYTE_ORDER _LITTLE_ENDIAN
#endif
#define __STRICT_ALIGNMENT
#include <sys/types.h>
#include <sys/endian.h>
#endif /* _MIPS64_ENDIAN_H_ */

188
libc/arch-mips64/include/machine/exec.h Normal file
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/* $OpenBSD: exec.h,v 1.1 2004/10/18 19:05:36 grange Exp $ */
/*
* Copyright (c) 1996-2004 Per Fogelstrom, Opsycon AB
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
*/
#ifndef _MIPS64_EXEC_H_
#define _MIPS64_EXEC_H_
#define __LDPGSZ 4096
/*
* Define what exec "formats" we should handle.
*/
#define NATIVE_EXEC_ELF
#define NATIVE_ELFSIZE 64
#define EXEC_SCRIPT
/*
* If included from sys/exec.h define kernels ELF format.
*/
#ifdef __LP64__
#define ARCH_ELFSIZE 64
#define DB_ELFSIZE 64
#define ELF_TARG_CLASS ELFCLASS64
#else
#define ARCH_ELFSIZE 32
#define DB_ELFSIZE 32
#define ELF_TARG_CLASS ELFCLASS32
#endif
#if defined(__MIPSEB__)
#define ELF_TARG_DATA ELFDATA2MSB
#else
#define ELF_TARG_DATA ELFDATA2LSB
#endif
#define ELF_TARG_MACH EM_MIPS
#define _NLIST_DO_ELF
#if defined(_LP64)
#define _KERN_DO_ELF64
#if defined(COMPAT_O32)
#define _KERN_DO_ELF
#endif
#else
#define _KERN_DO_ELF
#endif
/* Information taken from MIPS ABI supplemental */
/* Architecture dependent Segment types - p_type */
#define PT_MIPS_REGINFO 0x70000000 /* Register usage information */
/* Architecture dependent d_tag field for Elf32_Dyn. */
#define DT_MIPS_RLD_VERSION 0x70000001 /* Runtime Linker Interface ID */
#define DT_MIPS_TIME_STAMP 0x70000002 /* Timestamp */
#define DT_MIPS_ICHECKSUM 0x70000003 /* Cksum of ext. str. and com. sizes */
#define DT_MIPS_IVERSION 0x70000004 /* Version string (string tbl index) */
#define DT_MIPS_FLAGS 0x70000005 /* Flags */
#define DT_MIPS_BASE_ADDRESS 0x70000006 /* Segment base address */
#define DT_MIPS_CONFLICT 0x70000008 /* Adr of .conflict section */
#define DT_MIPS_LIBLIST 0x70000009 /* Address of .liblist section */
#define DT_MIPS_LOCAL_GOTNO 0x7000000a /* Number of local .GOT entries */
#define DT_MIPS_CONFLICTNO 0x7000000b /* Number of .conflict entries */
#define DT_MIPS_LIBLISTNO 0x70000010 /* Number of .liblist entries */
#define DT_MIPS_SYMTABNO 0x70000011 /* Number of .dynsym entries */
#define DT_MIPS_UNREFEXTNO 0x70000012 /* First external DYNSYM */
#define DT_MIPS_GOTSYM 0x70000013 /* First GOT entry in .dynsym */
#define DT_MIPS_HIPAGENO 0x70000014 /* Number of GOT page table entries */
#define DT_MIPS_RLD_MAP 0x70000016 /* Address of debug map pointer */
#define DT_PROCNUM (DT_MIPS_RLD_MAP - DT_LOPROC + 1)
/*
* Legal values for e_flags field of Elf32_Ehdr.
*/
#define EF_MIPS_NOREORDER 0x00000001 /* .noreorder was used */
#define EF_MIPS_PIC 0x00000002 /* Contains PIC code */
#define EF_MIPS_CPIC 0x00000004 /* Uses PIC calling sequence */
#define EF_MIPS_ABI2 0x00000020 /* -n32 on Irix 6 */
#define EF_MIPS_32BITMODE 0x00000100 /* 64 bit in 32 bit mode... */
#define EF_MIPS_ARCH 0xf0000000 /* MIPS architecture level */
#define E_MIPS_ARCH_1 0x00000000
#define E_MIPS_ARCH_2 0x10000000
#define E_MIPS_ARCH_3 0x20000000
#define E_MIPS_ARCH_4 0x30000000
#define EF_MIPS_ABI 0x0000f000 /* ABI level */
#define E_MIPS_ABI_NONE 0x00000000 /* ABI level not set */
#define E_MIPS_ABI_O32 0x00001000
#define E_MIPS_ABI_O64 0x00002000
#define E_MIPS_ABI_EABI32 0x00004000
#define E_MIPS_ABI_EABI64 0x00004000
/*
* Mips special sections.
*/
#define SHN_MIPS_ACOMMON 0xff00 /* Allocated common symbols */
#define SHN_MIPS_SCOMMON 0xff03 /* Small common symbols */
#define SHN_MIPS_SUNDEFINED 0xff04 /* Small undefined symbols */
/*
* Legal values for sh_type field of Elf32_Shdr.
*/
#define SHT_MIPS_LIBLIST 0x70000000 /* Shared objects used in link */
#define SHT_MIPS_CONFLICT 0x70000002 /* Conflicting symbols */
#define SHT_MIPS_GPTAB 0x70000003 /* Global data area sizes */
#define SHT_MIPS_UCODE 0x70000004 /* Reserved for SGI/MIPS compilers */
#define SHT_MIPS_DEBUG 0x70000005 /* MIPS ECOFF debugging information */
#define SHT_MIPS_REGINFO 0x70000006 /* Register usage information */
/*
* Legal values for sh_flags field of Elf32_Shdr.
*/
#define SHF_MIPS_GPREL 0x10000000 /* Must be part of global data area */
#if 0
/*
* Entries found in sections of type SHT_MIPS_GPTAB.
*/
typedef union {
struct {
Elf32_Word gt_current_g_value; /* -G val used in compilation */
Elf32_Word gt_unused; /* Not used */
} gt_header; /* First entry in section */
struct {
Elf32_Word gt_g_value; /* If this val were used for -G */
Elf32_Word gt_bytes; /* This many bytes would be used */
} gt_entry; /* Subsequent entries in section */
} Elf32_gptab;
/*
* Entry found in sections of type SHT_MIPS_REGINFO.
*/
typedef struct {
Elf32_Word ri_gprmask; /* General registers used */
Elf32_Word ri_cprmask[4]; /* Coprocessor registers used */
Elf32_Sword ri_gp_value; /* $gp register value */
} Elf32_RegInfo;
#endif
/*
* Mips relocations.
*/
#define R_MIPS_NONE 0 /* No reloc */
#define R_MIPS_16 1 /* Direct 16 bit */
#define R_MIPS_32 2 /* Direct 32 bit */
#define R_MIPS_REL32 3 /* PC relative 32 bit */
#define R_MIPS_26 4 /* Direct 26 bit shifted */
#define R_MIPS_HI16 5 /* High 16 bit */
#define R_MIPS_LO16 6 /* Low 16 bit */
#define R_MIPS_GPREL16 7 /* GP relative 16 bit */
#define R_MIPS_LITERAL 8 /* 16 bit literal entry */
#define R_MIPS_GOT16 9 /* 16 bit GOT entry */
#define R_MIPS_PC16 10 /* PC relative 16 bit */
#define R_MIPS_CALL16 11 /* 16 bit GOT entry for function */
#define R_MIPS_GPREL32 12 /* GP relative 32 bit */
#define R_MIPS_64 18
#define R_MIPS_REL32_64 ((R_MIPS_64 << 8) | R_MIPS_REL32)
#endif /* !_MIPS64_EXEC_H_ */

169
libc/arch-mips64/include/machine/ieee.h Normal file
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/* $OpenBSD: ieee.h,v 1.4 2010/01/23 19:11:21 miod Exp $ */
/*
* Copyright (c) 1992, 1993
* The Regents of the University of California. All rights reserved.
*
* This software was developed by the Computer Systems Engineering group
* at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
* contributed to Berkeley.
*
* All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the University of
* California, Lawrence Berkeley Laboratory.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* @(#)ieee.h 8.1 (Berkeley) 6/11/93
*/
/*
* ieee.h defines the machine-dependent layout of the machine's IEEE
* floating point. It does *not* define (yet?) any of the rounding
* mode bits, exceptions, and so forth.
*/
/*
* Define the number of bits in each fraction and exponent.
*
* k k+1
* Note that 1.0 x 2 == 0.1 x 2 and that denorms are represented
*
* (-exp_bias+1)
* as fractions that look like 0.fffff x 2 . This means that
*
* -126
* the number 0.10000 x 2 , for instance, is the same as the normalized
*
* -127 -128
* float 1.0 x 2 . Thus, to represent 2 , we need one leading zero
*
* -129
* in the fraction; to represent 2 , we need two, and so on. This
*
* (-exp_bias-fracbits+1)
* implies that the smallest denormalized number is 2
*
* for whichever format we are talking about: for single precision, for
*
* -126 -149
* instance, we get .00000000000000000000001 x 2 , or 1.0 x 2 , and
*
* -149 == -127 - 23 + 1.
*/
#define SNG_EXPBITS 8
#define SNG_FRACBITS 23
#define DBL_EXPBITS 11
#define DBL_FRACHBITS 20
#define DBL_FRACLBITS 32
#define DBL_FRACBITS 52
#define EXT_EXPBITS 15
#define EXT_FRACHBITS 16
#define EXT_FRACHMBITS 32
#define EXT_FRACLMBITS 32
#define EXT_FRACLBITS 32
#define EXT_FRACBITS 112
#define EXT_IMPLICIT_NBIT
#define EXT_TO_ARRAY32(p, a) do { \
(a)[0] = (uint32_t)(p)->ext_fracl; \
(a)[1] = (uint32_t)(p)->ext_fraclm; \
(a)[2] = (uint32_t)(p)->ext_frachm; \
(a)[3] = (uint32_t)(p)->ext_frach; \
} while(0)
struct ieee_single {
#ifdef __MIPSEB__
u_int sng_sign:1;
u_int sng_exp:8;
u_int sng_frac:23;
#else
u_int sng_frac:23;
u_int sng_exp:8;
u_int sng_sign:1;
#endif
};
struct ieee_double {
#ifdef __MIPSEB__
u_int dbl_sign:1;
u_int dbl_exp:11;
u_int dbl_frach:20;
u_int dbl_fracl;
#else
u_int dbl_fracl;
u_int dbl_frach:20;
u_int dbl_exp:11;
u_int dbl_sign:1;
#endif
};
struct ieee_ext {
#ifdef __MIPSEB__
u_int ext_sign:1;
u_int ext_exp:15;
u_int ext_frach:16;
u_int ext_frachm;
u_int ext_fraclm;
u_int ext_fracl;
#else
u_int ext_fracl;
u_int ext_fraclm;
u_int ext_frachm;
u_int ext_frach:16;
u_int ext_exp:15;
u_int ext_sign:1;
#endif
};
/*
* Floats whose exponent is in [1..INFNAN) (of whatever type) are
* `normal'. Floats whose exponent is INFNAN are either Inf or NaN.
* Floats whose exponent is zero are either zero (iff all fraction
* bits are zero) or subnormal values.
*
* A NaN is a `signalling NaN' if its QUIETNAN bit is clear in its
* high fraction; if the bit is set, it is a `quiet NaN'.
*/
#define SNG_EXP_INFNAN 255
#define DBL_EXP_INFNAN 2047
#define EXT_EXP_INFNAN 32767
#if 0
#define SNG_QUIETNAN (1 << 22)
#define DBL_QUIETNAN (1 << 19)
#define EXT_QUIETNAN (1 << 15)
#endif
/*
* Exponent biases.
*/
#define SNG_EXP_BIAS 127
#define DBL_EXP_BIAS 1023
#define EXT_EXP_BIAS 16383

62
libc/arch-mips64/include/machine/limits.h Normal file
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/* $OpenBSD: limits.h,v 1.5 2007/05/07 20:51:07 kettenis Exp $ */
/*
* Copyright (c) 1988, 1993
* The Regents of the University of California. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* @(#)limits.h 8.3 (Berkeley) 1/4/94
*/
#ifndef _MIPS_LIMITS_H_
#define _MIPS_LIMITS_H_
#include <sys/cdefs.h>
#define MB_LEN_MAX 6 /* Allow 31 bit UTF2 */
#ifndef SIZE_MAX
#define SIZE_MAX ULONG_MAX /* max value for a size_t */
#endif
#define SSIZE_MAX LONG_MAX /* max value for a ssize_t */
#if __BSD_VISIBLE
#define SIZE_T_MAX ULONG_MAX /* max value for a size_t (historic) */
/* Quads and longs are the same on mips64 */
#define UQUAD_MAX (ULONG_MAX) /* max value for a uquad_t */
#define QUAD_MAX (LONG_MAX) /* max value for a quad_t */
#define QUAD_MIN (LONG_MIN) /* min value for a quad_t */
#endif /* __BSD_VISIBLE */
#define LONGLONG_BIT 64
#define LONGLONG_MIN (-9223372036854775807LL-1)
#define LONGLONG_MAX 9223372036854775807LL
#define ULONGLONG_MAX 18446744073709551615ULL
#endif /* !_MIPS_LIMITS_H_ */

99
libc/arch-mips64/include/machine/regdef.h Normal file
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/* $OpenBSD: regdef.h,v 1.3 2005/08/07 07:29:44 miod Exp $ */
/*
* Copyright (c) 1992, 1993
* The Regents of the University of California. All rights reserved.
*
* This code is derived from software contributed to Berkeley by
* Ralph Campbell. This file is derived from the MIPS RISC
* Architecture book by Gerry Kane.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* @(#)regdef.h 8.1 (Berkeley) 6/10/93
*/
#ifndef _MIPS_REGDEF_H_
#define _MIPS_REGDEF_H_
#if (_MIPS_SIM == _ABI64) && !defined(__mips_n64)
#define __mips_n64 1
#endif
#if (_MIPS_SIM == _ABIN32) && !defined(__mips_n32)
#define __mips_n32 1
#endif
#define zero $0 /* always zero */
#define AT $at /* assembler temp */
#define v0 $2 /* return value */
#define v1 $3
#define a0 $4 /* argument registers */
#define a1 $5
#define a2 $6
#define a3 $7
#if defined(__mips_n32) || defined(__mips_n64)
#define a4 $8 /* expanded register arguments */
#define a5 $9
#define a6 $10
#define a7 $11
#define ta0 $8 /* alias */
#define ta1 $9
#define ta2 $10
#define ta3 $11
#define t0 $12 /* temp registers (not saved across subroutine calls) */
#define t1 $13
#define t2 $14
#define t3 $15
#else
#define t0 $8 /* temp registers (not saved across subroutine calls) */
#define t1 $9
#define t2 $10
#define t3 $11
#define t4 $12
#define t5 $13
#define t6 $14
#define t7 $15
#define ta0 $12 /* alias */
#define ta1 $13
#define ta2 $14
#define ta3 $15
#endif
#define s0 $16 /* saved across subroutine calls (callee saved) */
#define s1 $17
#define s2 $18
#define s3 $19
#define s4 $20
#define s5 $21
#define s6 $22
#define s7 $23
#define t8 $24 /* two more temp registers */
#define t9 $25
#define k0 $26 /* kernel temporary */
#define k1 $27
#define gp $28 /* global pointer */
#define sp $29 /* stack pointer */
#define s8 $30 /* one more callee saved */
#define ra $31 /* return address */
#endif /* !_MIPS_REGDEF_H_ */

119
libc/arch-mips64/include/machine/regnum.h Normal file
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/* $OpenBSD: regnum.h,v 1.3 2004/08/10 20:28:13 deraadt Exp $ */
/*
* Copyright (c) 2001-2002 Opsycon AB (www.opsycon.se / www.opsycon.com)
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
*/
#ifndef _MIPS64_REGNUM_H_
#define _MIPS64_REGNUM_H_
/*
* Location of the saved registers relative to ZERO.
* Usage is p->p_regs[XX].
*/
#define ZERO 0
#define AST 1
#define V0 2
#define V1 3
#define A0 4
#define A1 5
#define A2 6
#define A3 7
#define T0 8
#define T1 9
#define T2 10
#define T3 11
#define T4 12
#define T5 13
#define T6 14
#define T7 15
#define S0 16
#define S1 17
#define S2 18
#define S3 19
#define S4 20
#define S5 21
#define S6 22
#define S7 23
#define T8 24
#define T9 25
#define K0 26
#define K1 27
#define GP 28
#define SP 29
#define S8 30
#define RA 31
#define SR 32
#define PS SR /* alias for SR */
#define MULLO 33
#define MULHI 34
#define BADVADDR 35
#define CAUSE 36
#define PC 37
#define IC 38
#define CPL 39
#define NUMSAVEREGS 40 /* Number of registers saved in trap */
#define FPBASE NUMSAVEREGS
#define F0 (FPBASE+0)
#define F1 (FPBASE+1)
#define F2 (FPBASE+2)
#define F3 (FPBASE+3)
#define F4 (FPBASE+4)
#define F5 (FPBASE+5)
#define F6 (FPBASE+6)
#define F7 (FPBASE+7)
#define F8 (FPBASE+8)
#define F9 (FPBASE+9)
#define F10 (FPBASE+10)
#define F11 (FPBASE+11)
#define F12 (FPBASE+12)
#define F13 (FPBASE+13)
#define F14 (FPBASE+14)
#define F15 (FPBASE+15)
#define F16 (FPBASE+16)
#define F17 (FPBASE+17)
#define F18 (FPBASE+18)
#define F19 (FPBASE+19)
#define F20 (FPBASE+20)
#define F21 (FPBASE+21)
#define F22 (FPBASE+22)
#define F23 (FPBASE+23)
#define F24 (FPBASE+24)
#define F25 (FPBASE+25)
#define F26 (FPBASE+26)
#define F27 (FPBASE+27)
#define F28 (FPBASE+28)
#define F29 (FPBASE+29)
#define F30 (FPBASE+30)
#define F31 (FPBASE+31)
#define FSR (FPBASE+32)
#define NUMFPREGS 33
#define NREGS (NUMSAVEREGS + NUMFPREGS)
#endif /* !_MIPS64_REGNUM_H_ */

10
libc/arch-mips64/include/machine/setjmp.h Normal file
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/* $OpenBSD: setjmp.h,v 1.2 2004/08/10 21:10:56 pefo Exp $ */
/* Public domain */
#ifndef _MIPS_SETJMP_H_
#define _MIPS_SETJMP_H_
#define _JBLEN 157 /* size, in longs, of a jmp_buf */
#endif /* !_MIPS_SETJMP_H_ */

53
libc/arch-mips64/include/machine/signal.h Normal file
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/* $OpenBSD: signal.h,v 1.8 2006/01/09 18:18:37 millert Exp $ */
/*
* Copyright (c) 1992, 1993
* The Regents of the University of California. All rights reserved.
*
* This code is derived from software contributed to Berkeley by
* Ralph Campbell.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* @(#)signal.h 8.1 (Berkeley) 6/10/93
*/
#ifndef _MIPS_SIGNAL_H_
#define _MIPS_SIGNAL_H_
#include <machine/asm.h>
#define SC_REGMASK (0*REGSZ)
#define SC_STATUS (1*REGSZ)
#define SC_PC (2*REGSZ)
#define SC_REGS (SC_PC+8)
#define SC_FPREGS (SC_REGS+32*8)
#define SC_ACX (SC_FPREGS+32*REGSZ_FP)
#define SC_USED_MATH (SC_ACX+3*REGSZ)
/* OpenBSD compatibility */
#define SC_MASK SC_REGMASK
#define SC_FPUSED SC_USED_MATH
#endif /* !_MIPS_SIGNAL_H_ */