Merge "Use proper variable typing"
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commit
4efbf95d8c
@ -153,7 +153,8 @@ feholdexcept(fenv_t *envp)
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int
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int
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feupdateenv(const fenv_t *envp)
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feupdateenv(const fenv_t *envp)
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{
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{
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int mxcsr, status;
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int mxcsr;
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short status;
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__fnstsw(&status);
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__fnstsw(&status);
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if (__HAS_SSE())
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if (__HAS_SSE())
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@ -102,7 +102,7 @@ extern const fenv_t __fe_dfl_env;
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#define __fnclex() __asm __volatile("fnclex")
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#define __fnclex() __asm __volatile("fnclex")
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#define __fnstenv(__env) __asm __volatile("fnstenv %0" : "=m" (*(__env)))
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#define __fnstenv(__env) __asm __volatile("fnstenv %0" : "=m" (*(__env)))
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#define __fnstcw(__cw) __asm __volatile("fnstcw %0" : "=m" (*(__cw)))
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#define __fnstcw(__cw) __asm __volatile("fnstcw %0" : "=m" (*(__cw)))
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#define __fnstsw(__sw) __asm __volatile("fnstsw %0" : "=am" (*(__sw)))
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#define __fnstsw(__sw) __asm __volatile("fnstsw %0" : "=a" (*(__sw)))
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#define __fwait() __asm __volatile("fwait")
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#define __fwait() __asm __volatile("fwait")
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#define __ldmxcsr(__csr) __asm __volatile("ldmxcsr %0" : : "m" (__csr))
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#define __ldmxcsr(__csr) __asm __volatile("ldmxcsr %0" : : "m" (__csr))
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#define __stmxcsr(__csr) __asm __volatile("stmxcsr %0" : "=m" (*(__csr)))
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#define __stmxcsr(__csr) __asm __volatile("stmxcsr %0" : "=m" (*(__csr)))
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@ -148,7 +148,8 @@ int feraiseexcept(int __excepts);
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static __inline int
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static __inline int
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fetestexcept(int __excepts)
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fetestexcept(int __excepts)
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{
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{
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int __mxcsr, __status;
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int __mxcsr;
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short __status;
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__fnstsw(&__status);
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__fnstsw(&__status);
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if (__HAS_SSE())
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if (__HAS_SSE())
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