Remove the unnecessary generic-neon code.
Bug: 18156619
(cherry picked from commit 2169e17482)
Change-Id: I4a7f5bb9ad4c27b274f3a3c86c1617ca0578b98f
This commit is contained in:
Christopher Ferris
parent
1ea31a2901
commit
43dc3a9aae
@ -52,7 +52,7 @@ ifeq ($(strip $(TARGET_CPU_VARIANT)),)
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endif
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cpu_variant_mk := $(LOCAL_PATH)/arch-arm64/$(TARGET_CPU_VARIANT)/$(TARGET_CPU_VARIANT).mk
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ifeq ($(wildcard $(cpu_variant_mk)),)
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$(error "TARGET_CPU_VARIANT not set or set to an unknown value. Possible values are generic, generic-neon, denver64. Use generic for devices that do not have a CPU similar to any of the supported cpu variants.")
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$(error "TARGET_CPU_VARIANT not set or set to an unknown value. Possible values are generic, denver64. Use generic for devices that do not have a CPU similar to any of the supported cpu variants.")
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endif
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include $(cpu_variant_mk)
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libc_common_additional_dependencies += $(cpu_variank_mk)
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@ -1,179 +0,0 @@
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/* Copyright (c) 2012, Linaro Limited
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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* Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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* Neither the name of the Linaro nor the
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names of its contributors may be used to endorse or promote products
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derived from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/* Assumptions:
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*
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* ARMv8-a, AArch64
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* Unaligned accesses
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*
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*/
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#include <private/bionic_asm.h>
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#define dstin x0
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#define src x1
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#define count x2
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#define tmp1 x3
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#define tmp1w w3
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#define tmp2 x4
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#define tmp2w w4
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#define tmp3 x5
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#define tmp3w w5
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#define dst x6
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#define A_l x7
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#define A_h x8
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#define B_l x9
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#define B_h x10
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#define C_l x11
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#define C_h x12
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#define D_l x13
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#define D_h x14
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#define QA_l q0
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#define QA_h q1
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#define QB_l q2
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#define QB_h q3
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ENTRY(memcpy)
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mov dst, dstin
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cmp count, #64
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b.ge .Lcpy_not_short
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cmp count, #15
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b.le .Ltail15tiny
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/* Deal with small copies quickly by dropping straight into the
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* exit block. */
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.Ltail63:
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/* Copy up to 48 bytes of data. At this point we only need the
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* bottom 6 bits of count to be accurate. */
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ands tmp1, count, #0x30
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b.eq .Ltail15
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add dst, dst, tmp1
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add src, src, tmp1
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cmp tmp1w, #0x20
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b.eq 1f
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b.lt 2f
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ldp A_l, A_h, [src, #-48]
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stp A_l, A_h, [dst, #-48]
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1:
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ldp A_l, A_h, [src, #-32]
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stp A_l, A_h, [dst, #-32]
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2:
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ldp A_l, A_h, [src, #-16]
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stp A_l, A_h, [dst, #-16]
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.Ltail15:
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ands count, count, #15
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beq 1f
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add src, src, count
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ldp A_l, A_h, [src, #-16]
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add dst, dst, count
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stp A_l, A_h, [dst, #-16]
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1:
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ret
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.Ltail15tiny:
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/* Copy up to 15 bytes of data. Does not assume additional data
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being copied. */
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tbz count, #3, 1f
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ldr tmp1, [src], #8
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str tmp1, [dst], #8
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1:
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tbz count, #2, 1f
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ldr tmp1w, [src], #4
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str tmp1w, [dst], #4
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1:
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tbz count, #1, 1f
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ldrh tmp1w, [src], #2
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strh tmp1w, [dst], #2
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1:
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tbz count, #0, 1f
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ldrb tmp1w, [src]
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strb tmp1w, [dst]
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1:
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ret
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.Lcpy_not_short:
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/* We don't much care about the alignment of DST, but we want SRC
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* to be 128-bit (16 byte) aligned so that we don't cross cache line
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* boundaries on both loads and stores. */
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neg tmp2, src
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ands tmp2, tmp2, #15 /* Bytes to reach alignment. */
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b.eq 2f
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sub count, count, tmp2
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/* Copy more data than needed; it's faster than jumping
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* around copying sub-Quadword quantities. We know that
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* it can't overrun. */
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ldp A_l, A_h, [src]
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add src, src, tmp2
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stp A_l, A_h, [dst]
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add dst, dst, tmp2
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/* There may be less than 63 bytes to go now. */
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cmp count, #63
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b.le .Ltail63
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2:
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subs count, count, #128
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b.ge .Lcpy_body_large
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/* Less than 128 bytes to copy, so handle 64 here and then jump
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* to the tail. */
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ldp QA_l, QA_h, [src]
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ldp QB_l, QB_h, [src, #32]
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stp QA_l, QA_h, [dst]
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stp QB_l, QB_h, [dst, #32]
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tst count, #0x3f
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add src, src, #64
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add dst, dst, #64
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b.ne .Ltail63
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ret
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/* Critical loop. Start at a new cache line boundary. Assuming
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* 64 bytes per line this ensures the entire loop is in one line. */
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.p2align 6
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.Lcpy_body_large:
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/* There are at least 128 bytes to copy. */
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ldp QA_l, QA_h, [src, #0]
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sub dst, dst, #32 /* Pre-bias. */
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ldp QB_l, QB_h, [src, #32]! /* src += 64 - Pre-bias. */
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1:
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stp QA_l, QA_h, [dst, #32]
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ldp QA_l, QA_h, [src, #32]
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stp QB_l, QB_h, [dst, #64]!
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ldp QB_l, QB_h, [src, #64]!
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subs count, count, #64
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b.ge 1b
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stp QA_l, QA_h, [dst, #32]
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stp QB_l, QB_h, [dst, #64]
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add src, src, #32
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add dst, dst, #64 + 32
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tst count, #0x3f
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b.ne .Ltail63
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ret
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END(memcpy)
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@ -1,13 +0,0 @@
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libc_bionic_src_files_arm64 += \
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arch-arm64/generic/bionic/memchr.S \
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arch-arm64/generic/bionic/memcmp.S \
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arch-arm64/generic/bionic/memmove.S \
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arch-arm64/generic/bionic/memset.S \
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arch-arm64/generic/bionic/stpcpy.S \
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arch-arm64/generic/bionic/strchr.S \
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arch-arm64/generic/bionic/strcmp.S \
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arch-arm64/generic/bionic/strcpy.S \
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arch-arm64/generic/bionic/strlen.S \
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arch-arm64/generic/bionic/strncmp.S \
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arch-arm64/generic/bionic/strnlen.S \
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arch-arm64/generic-neon/bionic/memcpy.S \
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