am d2124b7c: am 7e997388: am b5e21103: Merge "AArch64: Use LDXR/STXR instead of LDAXR/STLXR for bionic_atomic_cmpxchg()"
* commit 'd2124b7c5ca15cb593c824d2488f6a95dce4a519': AArch64: Use LDXR/STXR instead of LDAXR/STLXR for bionic_atomic_cmpxchg()
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commit
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@ -29,15 +29,15 @@ __ATOMIC_INLINE__ int __bionic_cmpxchg(int32_t old_value, int32_t new_value, vol
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int32_t tmp, oldval;
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int32_t tmp, oldval;
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__asm__ __volatile__ (
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__asm__ __volatile__ (
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"// atomic_cmpxchg\n"
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"// atomic_cmpxchg\n"
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"1: ldaxr %w1, [%3]\n"
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"1: ldxr %w1, [%3]\n"
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" cmp %w1, %w4\n"
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" cmp %w1, %w4\n"
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" b.ne 2f\n"
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" b.ne 2f\n"
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" stlxr %w0, %w5, [%3]\n"
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" stxr %w0, %w5, [%3]\n"
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" cbnz %w0, 1b\n"
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" cbnz %w0, 1b\n"
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"2:"
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"2:"
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: "=&r" (tmp), "=&r" (oldval), "+o"(*ptr)
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: "=&r" (tmp), "=&r" (oldval), "+o"(*ptr)
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: "r" (ptr), "Ir" (old_value), "r" (new_value)
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: "r" (ptr), "Ir" (old_value), "r" (new_value)
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: "cc");
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: "cc", "memory");
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return oldval != old_value;
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return oldval != old_value;
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}
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}
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@ -51,7 +51,7 @@ __ATOMIC_INLINE__ int32_t __bionic_swap(int32_t new_value, volatile int32_t* ptr
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" cbnz %w1, 1b\n"
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" cbnz %w1, 1b\n"
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: "=&r" (prev), "=&r" (status), "+o" (*ptr)
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: "=&r" (prev), "=&r" (status), "+o" (*ptr)
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: "r" (ptr), "r" (new_value)
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: "r" (ptr), "r" (new_value)
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: "cc");
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: "cc", "memory");
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return prev;
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return prev;
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}
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}
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@ -65,7 +65,7 @@ __ATOMIC_INLINE__ int32_t __bionic_atomic_dec(volatile int32_t* ptr) {
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" cbnz %w2, 1b"
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" cbnz %w2, 1b"
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: "=&r" (prev), "=&r" (tmp), "=&r" (status), "+m"(*ptr)
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: "=&r" (prev), "=&r" (tmp), "=&r" (status), "+m"(*ptr)
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: "r" (ptr)
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: "r" (ptr)
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: "cc");
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: "cc", "memory");
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return prev;
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return prev;
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}
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}
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