generic-library/bionic
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

Fixes for the ARM-specific bswap_16, bswap_32, and bswap_64.

Browse Source 
1. Make the feature test work by excluding known-deficient processors, so
we don't have to maintain a complete list of all the processors that support
REV and REV16.

2. Don't abuse 'register' to get an effect similar to GCC's +l constraint,
but which was unnecessarily restrictive.

3. Fix __swap64md so _x isn't clobbered, breaking 64-bit swaps.

4. Make <byteswap.h> (which declars bswap_16 and friends) use <endian.h>
rather than <sys/endian.h>, so we get the machine-dependent implementations.

Change-Id: I6a38fad7a9fbe394aff141489617eb3883e1e944
This commit is contained in:
Elliott Hughes 2010-09-24 17:55:58 -07:00
parent 312be567a0
commit 3cf53d1a78
2 changed files with 27 additions and 30 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

36
libc/arch-arm/include/endian.h
View File

@ -33,14 +33,14 @@
#ifdef __GNUC__ #ifdef __GNUC__
/* NOTE: header <machine/cpu-features.h> could not be included directly /*
* since it defines extra macros, such as PLD. * REV and REV16 weren't available on ARM5 or ARM4.
* We don't include <machine/cpu-features.h> because it pollutes the
* namespace with macros like PLD.
*/ */
#if defined(__ARM_ARCH_7A__) || defined(__ARM_ARCH_7R__) || \ #if !defined __ARM_ARCH_5__ && !defined __ARM_ARCH_5T__ && \
defined(__ARM_ARCH_7__) || \ !defined __ARM_ARCH_5TE__ && !defined __ARM_ARCH_5TEJ__ && \
defined(__ARM_ARCH_6__) || defined(__ARM_ARCH_6J__) || \ !defined __ARM_ARCH_4T__ && !defined __ARM_ARCH_4__
defined(__ARM_ARCH_6K__) || defined(__ARM_ARCH_6Z__) || \
defined(__ARM_ARCH_6ZK__) || defined(__ARM_ARCH_6T2__)
/* According to RealView Assembler User's Guide, REV and REV16 are available /* According to RealView Assembler User's Guide, REV and REV16 are available
* in Thumb code and 16-bit instructions when used in Thumb-2 code. * in Thumb code and 16-bit instructions when used in Thumb-2 code.
@ -50,29 +50,25 @@
* *
* REV16 Rd, Rm * REV16 Rd, Rm
* Rd and Rm must both be Lo registers. * Rd and Rm must both be Lo registers.
*
* The +l constraint takes care of this without constraining us in ARM mode.
*/ */
#ifdef __thumb__
#define REV_LO_REG asm("r4")
#else
#define REV_LO_REG
#endif
#define __swap16md(x) ({ \ #define __swap16md(x) ({ \
register u_int16_t _x REV_LO_REG = (x); \ register u_int16_t _x = (x); \
__asm volatile ("rev16 %0, %0" : "+r" (_x)); \ __asm volatile ("rev16 %0, %0" : "+l" (_x)); \
_x; \ _x; \
}) })
#define __swap32md(x) ({ \ #define __swap32md(x) ({ \
register u_int32_t _x REV_LO_REG = (x); \ register u_int32_t _x = (x); \
__asm volatile ("rev %0, %0" : "+r" (_x)); \ __asm volatile ("rev %0, %0" : "+l" (_x)); \
_x; \ _x; \
}) })
#define __swap64md(x) ({ \ #define __swap64md(x) ({ \
u_int64_t _x = (x); \ u_int64_t _swap64md_x = (x); \
(u_int64_t) __swap32md(_x >> 32) | \ (u_int64_t) __swap32md(_swap64md_x >> 32) | \
(u_int64_t) __swap32md(_x & 0xffffffff) << 32; \ (u_int64_t) __swap32md(_swap64md_x & 0xffffffff) << 32; \
}) })
/* Tell sys/endian.h we have MD variants of the swap macros. */ /* Tell sys/endian.h we have MD variants of the swap macros. */

3
libc/include/byteswap.h
View File

@ -28,7 +28,8 @@
#ifndef _BYTESWAP_H_ #ifndef _BYTESWAP_H_
#define _BYTESWAP_H_ #define _BYTESWAP_H_
#include <sys/endian.h> /* endian.h rather than sys/endian.h so we get the machine-specific file. */
#include <endian.h>
#define bswap_16(x) swap16(x) #define bswap_16(x) swap16(x)
#define bswap_32(x) swap32(x) #define bswap_32(x) swap32(x)