bionic: add clean kernel header dsscomp.h
Change-Id: I09a98d0abe8ff4f92058f90ffb80ddc19ccee076 Signed-off-by: Iliyan Malchev <malchev@google.com>
This commit is contained in:
Iliyan Malchev
parent
7b79d1ed88
commit
3a5d668e01
312
libc/kernel/common/video/dsscomp.h
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312
libc/kernel/common/video/dsscomp.h
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/****************************************************************************
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****************************************************************************
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***
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*** This header was automatically generated from a Linux kernel header
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*** of the same name, to make information necessary for userspace to
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*** call into the kernel available to libc. It contains only constants,
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*** structures, and macros generated from the original header, and thus,
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*** contains no copyrightable information.
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***
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*** To edit the content of this header, modify the corresponding
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*** source file (e.g. under external/kernel-headers/original/) then
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*** run bionic/libc/kernel/tools/update_all.py
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***
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*** Any manual change here will be lost the next time this script will
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*** be run. You've been warned!
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***
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****************************************************************************
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****************************************************************************/
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#ifndef _LINUX_DSSCOMP_H
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#define _LINUX_DSSCOMP_H
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enum omap_plane {
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OMAP_DSS_GFX = 0,
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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OMAP_DSS_VIDEO1 = 1,
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OMAP_DSS_VIDEO2 = 2,
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OMAP_DSS_VIDEO3 = 3,
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OMAP_DSS_WB = 4,
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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};
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enum omap_channel {
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OMAP_DSS_CHANNEL_LCD = 0,
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OMAP_DSS_CHANNEL_DIGIT = 1,
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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OMAP_DSS_CHANNEL_LCD2 = 2,
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};
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enum omap_color_mode {
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OMAP_DSS_COLOR_CLUT1 = 1 << 0,
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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OMAP_DSS_COLOR_CLUT2 = 1 << 1,
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OMAP_DSS_COLOR_CLUT4 = 1 << 2,
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OMAP_DSS_COLOR_CLUT8 = 1 << 3,
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OMAP_DSS_COLOR_RGB12U = 1 << 4,
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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OMAP_DSS_COLOR_ARGB16 = 1 << 5,
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OMAP_DSS_COLOR_RGB16 = 1 << 6,
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OMAP_DSS_COLOR_RGB24U = 1 << 7,
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OMAP_DSS_COLOR_RGB24P = 1 << 8,
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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OMAP_DSS_COLOR_YUV2 = 1 << 9,
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OMAP_DSS_COLOR_UYVY = 1 << 10,
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OMAP_DSS_COLOR_ARGB32 = 1 << 11,
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OMAP_DSS_COLOR_RGBA32 = 1 << 12,
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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OMAP_DSS_COLOR_RGBX24 = 1 << 13,
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OMAP_DSS_COLOR_RGBX32 = 1 << 13,
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OMAP_DSS_COLOR_NV12 = 1 << 14,
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OMAP_DSS_COLOR_RGBA16 = 1 << 15,
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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OMAP_DSS_COLOR_RGBX12 = 1 << 16,
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OMAP_DSS_COLOR_RGBX16 = 1 << 16,
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OMAP_DSS_COLOR_ARGB16_1555 = 1 << 17,
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OMAP_DSS_COLOR_XRGB15 = 1 << 18,
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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OMAP_DSS_COLOR_XRGB16_1555 = 1 << 18,
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};
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enum omap_dss_trans_key_type {
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OMAP_DSS_COLOR_KEY_GFX_DST = 0,
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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OMAP_DSS_COLOR_KEY_VID_SRC = 1,
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};
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enum omap_dss_display_state {
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OMAP_DSS_DISPLAY_DISABLED = 0,
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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OMAP_DSS_DISPLAY_ACTIVE,
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OMAP_DSS_DISPLAY_SUSPENDED,
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OMAP_DSS_DISPLAY_TRANSITION,
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};
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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struct omap_video_timings {
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__u16 x_res;
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__u16 y_res;
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__u32 pixel_clock;
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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__u16 hsw;
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__u16 hfp;
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__u16 hbp;
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__u16 vsw;
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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__u16 vfp;
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__u16 vbp;
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};
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struct omap_dss_cconv_coefs {
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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__s16 ry, rcr, rcb;
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__s16 gy, gcr, gcb;
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__s16 by, bcr, bcb;
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__u16 full_range;
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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} __attribute__ ((aligned(4)));
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struct omap_dss_cpr_coefs {
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__s16 rr, rg, rb;
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__s16 gr, gg, gb;
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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__s16 br, bg, bb;
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};
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enum s3d_disp_type {
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S3D_DISP_NONE = 0,
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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S3D_DISP_FRAME_SEQ,
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S3D_DISP_ROW_IL,
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S3D_DISP_COL_IL,
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S3D_DISP_PIX_IL,
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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S3D_DISP_CHECKB,
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S3D_DISP_OVERUNDER,
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S3D_DISP_SIDEBYSIDE,
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};
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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enum s3d_disp_sub_sampling {
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S3D_DISP_SUB_SAMPLE_NONE = 0,
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S3D_DISP_SUB_SAMPLE_V,
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S3D_DISP_SUB_SAMPLE_H,
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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};
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enum s3d_disp_order {
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S3D_DISP_ORDER_L = 0,
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S3D_DISP_ORDER_R = 1,
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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};
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enum s3d_disp_view {
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S3D_DISP_VIEW_L = 0,
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S3D_DISP_VIEW_R,
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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};
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struct s3d_disp_info {
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enum s3d_disp_type type;
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enum s3d_disp_sub_sampling sub_samp;
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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enum s3d_disp_order order;
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unsigned int gap;
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};
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enum omap_dss_ilace_mode {
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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OMAP_DSS_ILACE = (1 << 0),
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OMAP_DSS_ILACE_SEQ = (1 << 1),
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OMAP_DSS_ILACE_SWAP = (1 << 2),
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OMAP_DSS_ILACE_NONE = 0,
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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OMAP_DSS_ILACE_IL_TB = OMAP_DSS_ILACE,
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OMAP_DSS_ILACE_IL_BT = OMAP_DSS_ILACE | OMAP_DSS_ILACE_SWAP,
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OMAP_DSS_ILACE_SEQ_TB = OMAP_DSS_ILACE_IL_TB | OMAP_DSS_ILACE_SEQ,
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OMAP_DSS_ILACE_SEQ_BT = OMAP_DSS_ILACE_IL_BT | OMAP_DSS_ILACE_SEQ,
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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};
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struct dss2_vc1_range_map_info {
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__u8 enable;
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__u8 range_y;
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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__u8 range_uv;
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} __attribute__ ((aligned(4)));
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struct dss2_rect_t {
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__s32 x;
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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__s32 y;
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__u32 w;
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__u32 h;
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} __attribute__ ((aligned(4)));
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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struct dss2_decim {
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__u8 min_x;
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__u8 max_x;
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__u8 min_y;
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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__u8 max_y;
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} __attribute__ ((aligned(4)));
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struct dss2_ovl_cfg {
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__u16 width;
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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__u16 height;
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__u32 stride;
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enum omap_color_mode color_mode;
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__u8 pre_mult_alpha;
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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__u8 global_alpha;
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__u8 rotation;
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__u8 mirror;
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enum omap_dss_ilace_mode ilace;
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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struct dss2_rect_t win;
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struct dss2_rect_t crop;
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struct dss2_decim decim;
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struct omap_dss_cconv_coefs cconv;
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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struct dss2_vc1_range_map_info vc1;
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__u8 ix;
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__u8 zorder;
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__u8 enabled;
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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__u8 zonly;
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} __attribute__ ((aligned(4)));
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enum omapdss_buffer_type {
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OMAP_DSS_BUFTYPE_SDMA,
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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OMAP_DSS_BUFTYPE_TILER_8BIT,
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OMAP_DSS_BUFTYPE_TILER_16BIT,
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OMAP_DSS_BUFTYPE_TILER_32BIT,
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OMAP_DSS_BUFTYPE_TILER_PAGE,
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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};
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struct dss2_ovl_info {
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struct dss2_ovl_cfg cfg;
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union {
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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struct {
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void *address;
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__u16 ba_type;
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__u16 uv_type;
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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};
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struct {
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__u32 ba;
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__u32 uv;
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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};
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};
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};
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struct dss2_mgr_info {
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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__u32 ix;
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__u32 default_color;
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enum omap_dss_trans_key_type trans_key_type;
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__u32 trans_key;
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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struct omap_dss_cpr_coefs cpr_coefs;
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__u8 trans_enabled;
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__u8 interlaced;
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__u8 alpha_blending;
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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__u8 cpr_enabled;
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__u8 swap_rb;
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} __attribute__ ((aligned(4)));
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enum dsscomp_setup_mode {
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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DSSCOMP_SETUP_MODE_APPLY = (1 << 0),
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DSSCOMP_SETUP_MODE_DISPLAY = (1 << 1),
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DSSCOMP_SETUP_MODE_CAPTURE = (1 << 2),
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DSSCOMP_SETUP_APPLY = DSSCOMP_SETUP_MODE_APPLY,
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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DSSCOMP_SETUP_DISPLAY =
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DSSCOMP_SETUP_MODE_APPLY | DSSCOMP_SETUP_MODE_DISPLAY,
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DSSCOMP_SETUP_CAPTURE =
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DSSCOMP_SETUP_MODE_APPLY | DSSCOMP_SETUP_MODE_CAPTURE,
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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DSSCOMP_SETUP_DISPLAY_CAPTURE =
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DSSCOMP_SETUP_DISPLAY | DSSCOMP_SETUP_CAPTURE,
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};
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struct dsscomp_setup_mgr_data {
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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__u32 sync_id;
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struct dss2_rect_t win;
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enum dsscomp_setup_mode mode;
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__u16 num_ovls;
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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__u16 get_sync_obj;
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struct dss2_mgr_info mgr;
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struct dss2_ovl_info ovls[0];
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};
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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struct dsscomp_check_ovl_data {
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enum dsscomp_setup_mode mode;
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struct dss2_mgr_info mgr;
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struct dss2_ovl_info ovl;
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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};
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struct dsscomp_wb_copy_data {
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struct dss2_ovl_info ovl, wb;
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};
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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struct dsscomp_display_info {
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__u32 ix;
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__u32 overlays_available;
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__u32 overlays_owned;
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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enum omap_channel channel;
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enum omap_dss_display_state state;
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__u8 enabled;
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struct omap_video_timings timings;
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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struct s3d_disp_info s3d_info;
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struct dss2_mgr_info mgr;
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};
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enum dsscomp_wait_phase {
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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DSSCOMP_WAIT_PROGRAMMED = 1,
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DSSCOMP_WAIT_DISPLAYED,
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DSSCOMP_WAIT_RELEASED,
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};
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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struct dsscomp_wait_data {
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__u32 timeout_us;
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enum dsscomp_wait_phase phase;
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};
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define DSSCOMP_SETUP_MGR _IOW('O', 128, struct dsscomp_setup_mgr_data)
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#define DSSCOMP_CHECK_OVL _IOWR('O', 129, struct dsscomp_check_ovl_data)
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#define DSSCOMP_WB_COPY _IOW('O', 130, struct dsscomp_wb_copy_data)
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#define DSSCOMP_QUERY_DISPLAY _IOWR('O', 131, struct dsscomp_display_info)
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define DSSCOMP_WAIT _IOW('O', 132, struct dsscomp_wait_data)
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#define DSSCOMP_SETUP_MGR_G _IOW('O', 127, struct dsscomp_setup_mgr_data)
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#endif
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