Update kernel headers to v3.14.
Other changes: - Modify update_all.py to skip ion header files when importing into aosp. - Fix generate_uapi_headers.sh to handle imports from a linux-stable kernel. Change-Id: I1ad81b9ccb063c21740f9875f2cc1238052cd4b3
This commit is contained in:
@@ -97,293 +97,298 @@ enum rt_op {
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enum cop_op {
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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mfc_op = 0x00, dmfc_op = 0x01,
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cfc_op = 0x02, mtc_op = 0x04,
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dmtc_op = 0x05, ctc_op = 0x06,
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bc_op = 0x08, cop_op = 0x10,
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cfc_op = 0x02, mfhc_op = 0x03,
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mtc_op = 0x04, dmtc_op = 0x05,
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ctc_op = 0x06, mthc_op = 0x07,
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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bc_op = 0x08, cop_op = 0x10,
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copm_op = 0x18
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};
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enum bcop_op {
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bcf_op, bct_op, bcfl_op, bctl_op
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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bcf_op, bct_op, bcfl_op, bctl_op
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};
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enum cop0_coi_func {
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tlbr_op = 0x01, tlbwi_op = 0x02,
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tlbwr_op = 0x06, tlbp_op = 0x08,
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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tlbwr_op = 0x06, tlbp_op = 0x08,
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rfe_op = 0x10, eret_op = 0x18
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};
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enum cop0_com_func {
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tlbr1_op = 0x01, tlbw_op = 0x02,
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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tlbr1_op = 0x01, tlbw_op = 0x02,
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tlbp1_op = 0x08, dctr_op = 0x09,
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dctw_op = 0x0a
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};
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enum cop1_fmt {
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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enum cop1_fmt {
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s_fmt, d_fmt, e_fmt, q_fmt,
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w_fmt, l_fmt
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};
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enum cop1_sdw_func {
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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enum cop1_sdw_func {
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fadd_op = 0x00, fsub_op = 0x01,
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fmul_op = 0x02, fdiv_op = 0x03,
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fsqrt_op = 0x04, fabs_op = 0x05,
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fmov_op = 0x06, fneg_op = 0x07,
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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fmov_op = 0x06, fneg_op = 0x07,
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froundl_op = 0x08, ftruncl_op = 0x09,
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fceill_op = 0x0a, ffloorl_op = 0x0b,
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fround_op = 0x0c, ftrunc_op = 0x0d,
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fceil_op = 0x0e, ffloor_op = 0x0f,
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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fceil_op = 0x0e, ffloor_op = 0x0f,
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fmovc_op = 0x11, fmovz_op = 0x12,
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fmovn_op = 0x13, frecip_op = 0x15,
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frsqrt_op = 0x16, fcvts_op = 0x20,
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fcvtd_op = 0x21, fcvte_op = 0x22,
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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fcvtd_op = 0x21, fcvte_op = 0x22,
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fcvtw_op = 0x24, fcvtl_op = 0x25,
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fcmp_op = 0x30
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};
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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enum cop1x_func {
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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lwxc1_op = 0x00, ldxc1_op = 0x01,
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pfetch_op = 0x07, swxc1_op = 0x08,
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sdxc1_op = 0x09, madd_s_op = 0x20,
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madd_d_op = 0x21, madd_e_op = 0x22,
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swxc1_op = 0x08, sdxc1_op = 0x09,
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pfetch_op = 0x0f, madd_s_op = 0x20,
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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madd_d_op = 0x21, madd_e_op = 0x22,
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msub_s_op = 0x28, msub_d_op = 0x29,
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msub_e_op = 0x2a, nmadd_s_op = 0x30,
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nmadd_d_op = 0x31, nmadd_e_op = 0x32,
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nmsub_s_op = 0x38, nmsub_d_op = 0x39,
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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nmsub_s_op = 0x38, nmsub_d_op = 0x39,
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nmsub_e_op = 0x3a
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};
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enum mad_func {
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madd_fp_op = 0x08, msub_fp_op = 0x0a,
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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madd_fp_op = 0x08, msub_fp_op = 0x0a,
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nmadd_fp_op = 0x0c, nmsub_fp_op = 0x0e
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};
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enum lx_func {
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lwx_op = 0x00,
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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lwx_op = 0x00,
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lhx_op = 0x04,
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lbux_op = 0x06,
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ldx_op = 0x08,
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lwux_op = 0x10,
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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lwux_op = 0x10,
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lhux_op = 0x14,
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lbx_op = 0x16,
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};
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enum mm_major_op {
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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enum mm_major_op {
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mm_pool32a_op, mm_pool16a_op, mm_lbu16_op, mm_move16_op,
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mm_addi32_op, mm_lbu32_op, mm_sb32_op, mm_lb32_op,
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mm_pool32b_op, mm_pool16b_op, mm_lhu16_op, mm_andi16_op,
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mm_addiu32_op, mm_lhu32_op, mm_sh32_op, mm_lh32_op,
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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mm_addiu32_op, mm_lhu32_op, mm_sh32_op, mm_lh32_op,
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mm_pool32i_op, mm_pool16c_op, mm_lwsp16_op, mm_pool16d_op,
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mm_ori32_op, mm_pool32f_op, mm_reserved1_op, mm_reserved2_op,
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mm_pool32c_op, mm_lwgp16_op, mm_lw16_op, mm_pool16e_op,
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mm_xori32_op, mm_jals32_op, mm_addiupc_op, mm_reserved3_op,
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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mm_xori32_op, mm_jals32_op, mm_addiupc_op, mm_reserved3_op,
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mm_reserved4_op, mm_pool16f_op, mm_sb16_op, mm_beqz16_op,
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mm_slti32_op, mm_beq32_op, mm_swc132_op, mm_lwc132_op,
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mm_reserved5_op, mm_reserved6_op, mm_sh16_op, mm_bnez16_op,
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mm_sltiu32_op, mm_bne32_op, mm_sdc132_op, mm_ldc132_op,
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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mm_sltiu32_op, mm_bne32_op, mm_sdc132_op, mm_ldc132_op,
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mm_reserved7_op, mm_reserved8_op, mm_swsp16_op, mm_b16_op,
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mm_andi32_op, mm_j32_op, mm_sd32_op, mm_ld32_op,
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mm_reserved11_op, mm_reserved12_op, mm_sw16_op, mm_li16_op,
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mm_jalx32_op, mm_jal32_op, mm_sw32_op, mm_lw32_op,
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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mm_jalx32_op, mm_jal32_op, mm_sw32_op, mm_lw32_op,
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};
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enum mm_32i_minor_op {
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mm_bltz_op, mm_bltzal_op, mm_bgez_op, mm_bgezal_op,
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mm_blez_op, mm_bnezc_op, mm_bgtz_op, mm_beqzc_op,
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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mm_blez_op, mm_bnezc_op, mm_bgtz_op, mm_beqzc_op,
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mm_tlti_op, mm_tgei_op, mm_tltiu_op, mm_tgeiu_op,
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mm_tnei_op, mm_lui_op, mm_teqi_op, mm_reserved13_op,
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mm_synci_op, mm_bltzals_op, mm_reserved14_op, mm_bgezals_op,
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mm_bc2f_op, mm_bc2t_op, mm_reserved15_op, mm_reserved16_op,
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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mm_bc2f_op, mm_bc2t_op, mm_reserved15_op, mm_reserved16_op,
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mm_reserved17_op, mm_reserved18_op, mm_bposge64_op, mm_bposge32_op,
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mm_bc1f_op, mm_bc1t_op, mm_reserved19_op, mm_reserved20_op,
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mm_bc1any2f_op, mm_bc1any2t_op, mm_bc1any4f_op, mm_bc1any4t_op,
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};
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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};
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enum mm_32a_minor_op {
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mm_sll32_op = 0x000,
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mm_ins_op = 0x00c,
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mm_ext_op = 0x02c,
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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mm_ext_op = 0x02c,
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mm_pool32axf_op = 0x03c,
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mm_srl32_op = 0x040,
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mm_sra_op = 0x080,
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mm_rotr_op = 0x0c0,
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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mm_rotr_op = 0x0c0,
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mm_lwxs_op = 0x118,
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mm_addu32_op = 0x150,
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mm_subu32_op = 0x1d0,
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mm_and_op = 0x250,
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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mm_and_op = 0x250,
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mm_or32_op = 0x290,
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mm_xor32_op = 0x310,
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};
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enum mm_32b_func {
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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enum mm_32b_func {
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mm_lwc2_func = 0x0,
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mm_lwp_func = 0x1,
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mm_ldc2_func = 0x2,
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mm_ldp_func = 0x4,
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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mm_ldp_func = 0x4,
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mm_lwm32_func = 0x5,
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mm_cache_func = 0x6,
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mm_ldm_func = 0x7,
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mm_swc2_func = 0x8,
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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mm_swc2_func = 0x8,
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mm_swp_func = 0x9,
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mm_sdc2_func = 0xa,
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mm_sdp_func = 0xc,
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mm_swm32_func = 0xd,
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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mm_swm32_func = 0xd,
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mm_sdm_func = 0xf,
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};
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enum mm_32c_func {
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mm_pref_func = 0x2,
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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mm_pref_func = 0x2,
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mm_ll_func = 0x3,
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mm_swr_func = 0x9,
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mm_sc_func = 0xb,
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mm_lwu_func = 0xe,
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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mm_lwu_func = 0xe,
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};
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enum mm_32axf_minor_op {
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mm_mfc0_op = 0x003,
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mm_mtc0_op = 0x00b,
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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mm_mtc0_op = 0x00b,
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mm_tlbp_op = 0x00d,
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mm_jalr_op = 0x03c,
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mm_tlbr_op = 0x04d,
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mm_jalrhb_op = 0x07c,
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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mm_jalrhb_op = 0x07c,
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mm_tlbwi_op = 0x08d,
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mm_tlbwr_op = 0x0cd,
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mm_jalrs_op = 0x13c,
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mm_jalrshb_op = 0x17c,
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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mm_jalrshb_op = 0x17c,
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mm_syscall_op = 0x22d,
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mm_eret_op = 0x3cd,
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};
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enum mm_32f_minor_op {
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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enum mm_32f_minor_op {
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mm_32f_00_op = 0x00,
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mm_32f_01_op = 0x01,
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mm_32f_02_op = 0x02,
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mm_32f_10_op = 0x08,
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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mm_32f_10_op = 0x08,
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mm_32f_11_op = 0x09,
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mm_32f_12_op = 0x0a,
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mm_32f_20_op = 0x10,
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mm_32f_30_op = 0x18,
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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mm_32f_30_op = 0x18,
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mm_32f_40_op = 0x20,
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mm_32f_41_op = 0x21,
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mm_32f_42_op = 0x22,
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mm_32f_50_op = 0x28,
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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mm_32f_50_op = 0x28,
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mm_32f_51_op = 0x29,
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mm_32f_52_op = 0x2a,
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mm_32f_60_op = 0x30,
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mm_32f_70_op = 0x38,
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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mm_32f_70_op = 0x38,
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mm_32f_73_op = 0x3b,
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mm_32f_74_op = 0x3c,
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};
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enum mm_32f_10_minor_op {
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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enum mm_32f_10_minor_op {
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mm_lwxc1_op = 0x1,
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mm_swxc1_op,
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mm_ldxc1_op,
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mm_sdxc1_op,
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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mm_sdxc1_op,
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mm_luxc1_op,
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mm_suxc1_op,
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};
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enum mm_32f_func {
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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enum mm_32f_func {
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mm_lwxc1_func = 0x048,
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mm_swxc1_func = 0x088,
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mm_ldxc1_func = 0x0c8,
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mm_sdxc1_func = 0x108,
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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mm_sdxc1_func = 0x108,
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};
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enum mm_32f_40_minor_op {
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mm_fmovf_op,
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mm_fmovt_op,
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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mm_fmovt_op,
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};
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enum mm_32f_60_minor_op {
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mm_fadd_op,
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mm_fsub_op,
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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mm_fsub_op,
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mm_fmul_op,
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mm_fdiv_op,
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};
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enum mm_32f_70_minor_op {
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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enum mm_32f_70_minor_op {
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mm_fmovn_op,
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mm_fmovz_op,
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};
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enum mm_32f_73_minor_op {
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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enum mm_32f_73_minor_op {
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mm_fmov0_op = 0x01,
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mm_fcvtl_op = 0x04,
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mm_movf0_op = 0x05,
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mm_frsqrt_op = 0x08,
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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mm_frsqrt_op = 0x08,
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mm_ffloorl_op = 0x0c,
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mm_fabs0_op = 0x0d,
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mm_fcvtw_op = 0x24,
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mm_movt0_op = 0x25,
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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mm_movt0_op = 0x25,
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mm_fsqrt_op = 0x28,
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mm_ffloorw_op = 0x2c,
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mm_fneg0_op = 0x2d,
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mm_cfc1_op = 0x40,
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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mm_cfc1_op = 0x40,
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mm_frecip_op = 0x48,
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mm_fceill_op = 0x4c,
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mm_fcvtd0_op = 0x4d,
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mm_ctc1_op = 0x60,
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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mm_ctc1_op = 0x60,
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mm_fceilw_op = 0x6c,
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mm_fcvts0_op = 0x6d,
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mm_mfc1_op = 0x80,
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mm_fmov1_op = 0x81,
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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mm_fmov1_op = 0x81,
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mm_movf1_op = 0x85,
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mm_ftruncl_op = 0x8c,
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mm_fabs1_op = 0x8d,
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mm_mtc1_op = 0xa0,
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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mm_mtc1_op = 0xa0,
|
||||
mm_movt1_op = 0xa5,
|
||||
mm_ftruncw_op = 0xac,
|
||||
mm_fneg1_op = 0xad,
|
||||
mm_froundl_op = 0xcc,
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
mm_mfhc1_op = 0xc0,
|
||||
mm_froundl_op = 0xcc,
|
||||
mm_fcvtd1_op = 0xcd,
|
||||
mm_mthc1_op = 0xe0,
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
mm_froundw_op = 0xec,
|
||||
mm_fcvts1_op = 0xed,
|
||||
};
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
enum mm_16c_minor_op {
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
mm_lwm16_op = 0x04,
|
||||
mm_swm16_op = 0x05,
|
||||
mm_jr16_op = 0x18,
|
||||
mm_jr16_op = 0x0c,
|
||||
mm_jrc_op = 0x0d,
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
mm_jrc_op = 0x1a,
|
||||
mm_jalr16_op = 0x1c,
|
||||
mm_jalrs16_op = 0x1e,
|
||||
mm_jalr16_op = 0x0e,
|
||||
mm_jalrs16_op = 0x0f,
|
||||
mm_jraddiusp_op = 0x18,
|
||||
};
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
enum mm_16d_minor_op {
|
||||
|
Reference in New Issue
Block a user