Merge "Clean up the pthread-only atomic stuff a little."
This commit is contained in:
Elliott Hughes
Gerrit Code Review
commit
341b55a1e6
@ -16,172 +16,64 @@
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#ifndef BIONIC_ATOMIC_ARM_H
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#define BIONIC_ATOMIC_ARM_H
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#include <machine/cpu-features.h>
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/* Some of the harware instructions used below are not available in Thumb-1
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* mode (they are if you build in ARM or Thumb-2 mode though). To solve this
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* problem, we're going to use the same technique than libatomics_ops,
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* which is to temporarily switch to ARM, do the operation, then switch
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* back to Thumb-1.
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*
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* This results in two 'bx' jumps, just like a normal function call, but
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* everything is kept inlined, avoids loading or computing the function's
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* address, and prevents a little I-cache trashing too.
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*
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* However, it is highly recommended to avoid compiling any C library source
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* file that use these functions in Thumb-1 mode.
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*
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* Define three helper macros to implement this:
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*/
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#if defined(__thumb__) && !defined(__thumb2__)
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# define __ATOMIC_SWITCH_TO_ARM \
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"adr r3, 5f\n" \
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"bx r3\n" \
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".align\n" \
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".arm\n" \
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"5:\n"
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/* note: the leading \n below is intentional */
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# define __ATOMIC_SWITCH_TO_THUMB \
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"\n" \
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"adr r3, 6f\n" \
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"bx r3\n" \
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".thumb" \
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"6:\n"
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# define __ATOMIC_CLOBBERS "r3" /* list of clobbered registers */
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/* Warn the user that ARM mode should really be preferred! */
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# warning Rebuilding this source file in ARM mode is highly recommended for performance!!
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#else
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# define __ATOMIC_SWITCH_TO_ARM /* nothing */
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# define __ATOMIC_SWITCH_TO_THUMB /* nothing */
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# define __ATOMIC_CLOBBERS /* nothing */
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#endif
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/* Define a full memory barrier, this is only needed if we build the
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* platform for a multi-core device. For the record, using a 'dmb'
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* instruction on a Nexus One device can take up to 180 ns even if
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* it is completely un-necessary on this device.
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*
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* NOTE: This is where the platform and NDK headers atomic headers are
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* going to diverge. With the NDK, we don't know if the generated
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* code is going to run on a single or multi-core device, so we
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* need to be cautious.
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*
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* I.e. on single-core devices, the helper immediately returns,
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* on multi-core devices, it uses "dmb" or any other means to
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* perform a full-memory barrier.
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*
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* There are three cases to consider for the platform:
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*
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* - multi-core ARMv7-A => use the 'dmb' hardware instruction
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* - multi-core ARMv6 => use the coprocessor
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* - single core ARMv6+ => do not use any hardware barrier
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*/
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__ATOMIC_INLINE__ void __bionic_memory_barrier(void) {
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#if defined(ANDROID_SMP) && ANDROID_SMP == 1
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/* For ARMv7-A, we can use the 'dmb' instruction directly */
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__ATOMIC_INLINE__ void __bionic_memory_barrier(void) {
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/* Note: we always build in ARM or Thumb-2 on ARMv7-A, so don't
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* bother with __ATOMIC_SWITCH_TO_ARM */
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__asm__ __volatile__ ( "dmb" : : : "memory" );
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__asm__ __volatile__ ( "dmb" : : : "memory" );
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#else
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/* A simple compiler barrier. */
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__asm__ __volatile__ ( "" : : : "memory" );
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#endif
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}
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#else /* !ANDROID_SMP */
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__ATOMIC_INLINE__ void __bionic_memory_barrier(void) {
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/* A simple compiler barrier */
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__asm__ __volatile__ ( "" : : : "memory" );
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}
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#endif /* !ANDROID_SMP */
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/* Compare-and-swap, without any explicit barriers. Note that this functions
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* returns 0 on success, and 1 on failure. The opposite convention is typically
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* used on other platforms.
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*/
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__ATOMIC_INLINE__ int
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__bionic_cmpxchg(int32_t old_value, int32_t new_value, volatile int32_t* ptr)
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{
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int32_t prev, status;
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do {
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__asm__ __volatile__ (
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__ATOMIC_SWITCH_TO_ARM
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"ldrex %0, [%3]\n"
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"mov %1, #0\n"
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"teq %0, %4\n"
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__ATOMIC_INLINE__ int __bionic_cmpxchg(int32_t old_value, int32_t new_value, volatile int32_t* ptr) {
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int32_t prev, status;
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do {
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__asm__ __volatile__ (
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"ldrex %0, [%3]\n"
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"mov %1, #0\n"
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"teq %0, %4\n"
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#ifdef __thumb2__
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"it eq\n"
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"it eq\n"
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#endif
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"strexeq %1, %5, [%3]"
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__ATOMIC_SWITCH_TO_THUMB
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: "=&r" (prev), "=&r" (status), "+m"(*ptr)
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: "r" (ptr), "Ir" (old_value), "r" (new_value)
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: __ATOMIC_CLOBBERS "cc");
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} while (__builtin_expect(status != 0, 0));
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return prev != old_value;
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"strexeq %1, %5, [%3]"
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: "=&r" (prev), "=&r" (status), "+m"(*ptr)
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: "r" (ptr), "Ir" (old_value), "r" (new_value)
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: "cc");
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} while (__builtin_expect(status != 0, 0));
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return prev != old_value;
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}
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/* Swap operation, without any explicit barriers. */
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__ATOMIC_INLINE__ int32_t
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__bionic_swap(int32_t new_value, volatile int32_t* ptr)
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{
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int32_t prev, status;
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do {
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__asm__ __volatile__ (
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__ATOMIC_SWITCH_TO_ARM
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"ldrex %0, [%3]\n"
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"strex %1, %4, [%3]"
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__ATOMIC_SWITCH_TO_THUMB
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: "=&r" (prev), "=&r" (status), "+m" (*ptr)
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: "r" (ptr), "r" (new_value)
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: __ATOMIC_CLOBBERS "cc");
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} while (__builtin_expect(status != 0, 0));
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return prev;
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/* Swap, without any explicit barriers. */
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__ATOMIC_INLINE__ int32_t __bionic_swap(int32_t new_value, volatile int32_t* ptr) {
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int32_t prev, status;
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do {
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__asm__ __volatile__ (
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"ldrex %0, [%3]\n"
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"strex %1, %4, [%3]"
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: "=&r" (prev), "=&r" (status), "+m" (*ptr)
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: "r" (ptr), "r" (new_value)
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: "cc");
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} while (__builtin_expect(status != 0, 0));
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return prev;
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}
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/* Atomic increment - without any barriers
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* This returns the old value
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*/
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__ATOMIC_INLINE__ int32_t
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__bionic_atomic_inc(volatile int32_t* ptr)
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{
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int32_t prev, tmp, status;
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do {
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__asm__ __volatile__ (
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__ATOMIC_SWITCH_TO_ARM
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"ldrex %0, [%4]\n"
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"add %1, %0, #1\n"
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"strex %2, %1, [%4]"
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__ATOMIC_SWITCH_TO_THUMB
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: "=&r" (prev), "=&r" (tmp), "=&r" (status), "+m"(*ptr)
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: "r" (ptr)
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: __ATOMIC_CLOBBERS "cc");
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} while (__builtin_expect(status != 0, 0));
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return prev;
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}
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/* Atomic decrement - without any barriers
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* This returns the old value.
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*/
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__ATOMIC_INLINE__ int32_t
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__bionic_atomic_dec(volatile int32_t* ptr)
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{
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int32_t prev, tmp, status;
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do {
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__asm__ __volatile__ (
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__ATOMIC_SWITCH_TO_ARM
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"ldrex %0, [%4]\n"
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"sub %1, %0, #1\n"
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"strex %2, %1, [%4]"
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__ATOMIC_SWITCH_TO_THUMB
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: "=&r" (prev), "=&r" (tmp), "=&r" (status), "+m"(*ptr)
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: "r" (ptr)
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: __ATOMIC_CLOBBERS "cc");
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} while (__builtin_expect(status != 0, 0));
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return prev;
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/* Atomic decrement, without explicit barriers. */
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__ATOMIC_INLINE__ int32_t __bionic_atomic_dec(volatile int32_t* ptr) {
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int32_t prev, tmp, status;
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do {
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__asm__ __volatile__ (
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"ldrex %0, [%4]\n"
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"sub %1, %0, #1\n"
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"strex %2, %1, [%4]"
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: "=&r" (prev), "=&r" (tmp), "=&r" (status), "+m"(*ptr)
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: "r" (ptr)
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: "cc");
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} while (__builtin_expect(status != 0, 0));
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return prev;
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}
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#endif /* SYS_ATOMICS_ARM_H */
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@ -16,46 +16,35 @@
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#ifndef BIONIC_ATOMIC_GCC_BUILTIN_H
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#define BIONIC_ATOMIC_GCC_BUILTIN_H
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/* This header file is used by default if we don't have optimized atomic
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/*
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* This header file is used by default if we don't have optimized atomic
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* routines for a given platform. See bionic_atomic_arm.h and
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* bionic_atomic_x86.h for examples.
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*
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* Note that the GCC builtins include barriers that aren't present in
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* the architecture-specific assembler versions.
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*/
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__ATOMIC_INLINE__ void
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__bionic_memory_barrier(void)
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{
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__sync_synchronize();
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__ATOMIC_INLINE__ void __bionic_memory_barrier(void) {
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__sync_synchronize();
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}
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__ATOMIC_INLINE__ int
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__bionic_cmpxchg(int32_t old_value, int32_t new_value, volatile int32_t* ptr)
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{
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/* We must return 0 on success */
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return __sync_val_compare_and_swap(ptr, old_value, new_value) != old_value;
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__ATOMIC_INLINE__ int __bionic_cmpxchg(int32_t old_value, int32_t new_value, volatile int32_t* ptr) {
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/* We must return 0 on success. */
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return __sync_val_compare_and_swap(ptr, old_value, new_value) != old_value;
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}
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__ATOMIC_INLINE__ int32_t
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__bionic_swap(int32_t new_value, volatile int32_t* ptr)
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{
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int32_t old_value;
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do {
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old_value = *ptr;
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} while (__sync_val_compare_and_swap(ptr, old_value, new_value) != old_value);
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return old_value;
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__ATOMIC_INLINE__ int32_t __bionic_swap(int32_t new_value, volatile int32_t* ptr) {
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int32_t old_value;
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do {
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old_value = *ptr;
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} while (__sync_val_compare_and_swap(ptr, old_value, new_value) != old_value);
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return old_value;
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}
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__ATOMIC_INLINE__ int32_t
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__bionic_atomic_inc(volatile int32_t* ptr)
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{
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/* We must return the old value */
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return __sync_fetch_and_add(ptr, 1);
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}
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__ATOMIC_INLINE__ int32_t
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__bionic_atomic_dec(volatile int32_t* ptr)
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{
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/* We must return the old value */
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return __sync_fetch_and_add(ptr, -1);
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__ATOMIC_INLINE__ int32_t __bionic_atomic_dec(volatile int32_t* ptr) {
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/* We must return the old value. */
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return __sync_fetch_and_add(ptr, -1);
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}
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#endif /* BIONIC_ATOMIC_GCC_BUILTIN_H */
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@ -23,11 +23,6 @@
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* memory barrier needs to be issued inline rather than as a function
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* call.
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*
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* Most code should not use these.
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*
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* Anything that does include this file must set ANDROID_SMP to either
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* 0 or 1, indicating compilation for UP or SMP, respectively.
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*
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* Macros defined in this header:
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*
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* void ANDROID_MEMBAR_FULL(void)
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@ -19,84 +19,58 @@
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/* Define a full memory barrier, this is only needed if we build the
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* platform for a multi-core device.
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*/
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__ATOMIC_INLINE__ void __bionic_memory_barrier() {
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#if defined(ANDROID_SMP) && ANDROID_SMP == 1
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__ATOMIC_INLINE__ void
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__bionic_memory_barrier()
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{
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__asm__ __volatile__ ( "sync" : : : "memory" );
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}
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__asm__ __volatile__ ( "sync" : : : "memory" );
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#else
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__ATOMIC_INLINE__ void
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__bionic_memory_barrier()
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{
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/* A simple compiler barrier */
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__asm__ __volatile__ ( "" : : : "memory" );
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}
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/* A simple compiler barrier. */
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__asm__ __volatile__ ( "" : : : "memory" );
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#endif
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}
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|
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/* Compare-and-swap, without any explicit barriers. Note that this function
|
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* returns 0 on success, and 1 on failure. The opposite convention is typically
|
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* used on other platforms.
|
||||
*/
|
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__ATOMIC_INLINE__ int
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__bionic_cmpxchg(int32_t old_value, int32_t new_value, volatile int32_t* ptr)
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{
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int32_t prev, status;
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__asm__ __volatile__ ("1: move %[status], %[new_value] \n"
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" ll %[prev], 0(%[ptr]) \n"
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" bne %[old_value], %[prev], 2f \n"
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" sc %[status], 0(%[ptr]) \n"
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" beqz %[status], 1b \n"
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"2: \n"
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: [prev]"=&r"(prev), [status]"=&r"(status), "+m"(*ptr)
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: [new_value]"r"(new_value), [old_value]"r"(old_value), [ptr]"r"(ptr)
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: "memory");
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return prev != old_value;
|
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__ATOMIC_INLINE__ int __bionic_cmpxchg(int32_t old_value, int32_t new_value, volatile int32_t* ptr) {
|
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int32_t prev, status;
|
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__asm__ __volatile__ ("1: move %[status], %[new_value] \n"
|
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" ll %[prev], 0(%[ptr]) \n"
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" bne %[old_value], %[prev], 2f \n"
|
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" sc %[status], 0(%[ptr]) \n"
|
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" beqz %[status], 1b \n"
|
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"2: \n"
|
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: [prev]"=&r"(prev), [status]"=&r"(status), "+m"(*ptr)
|
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: [new_value]"r"(new_value), [old_value]"r"(old_value), [ptr]"r"(ptr)
|
||||
: "memory");
|
||||
return prev != old_value;
|
||||
}
|
||||
|
||||
|
||||
/* Swap, without any explicit barriers */
|
||||
__ATOMIC_INLINE__ int32_t
|
||||
__bionic_swap(int32_t new_value, volatile int32_t *ptr)
|
||||
{
|
||||
int32_t prev, status;
|
||||
__asm__ __volatile__ ("1: move %[status], %[new_value] \n"
|
||||
" ll %[prev], 0(%[ptr]) \n"
|
||||
" sc %[status], 0(%[ptr]) \n"
|
||||
" beqz %[status], 1b \n"
|
||||
: [prev]"=&r"(prev), [status]"=&r"(status), "+m"(*ptr)
|
||||
: [ptr]"r"(ptr), [new_value]"r"(new_value)
|
||||
: "memory");
|
||||
return prev;
|
||||
/* Swap, without any explicit barriers. */
|
||||
__ATOMIC_INLINE__ int32_t __bionic_swap(int32_t new_value, volatile int32_t* ptr) {
|
||||
int32_t prev, status;
|
||||
__asm__ __volatile__ ("1: move %[status], %[new_value] \n"
|
||||
" ll %[prev], 0(%[ptr]) \n"
|
||||
" sc %[status], 0(%[ptr]) \n"
|
||||
" beqz %[status], 1b \n"
|
||||
: [prev]"=&r"(prev), [status]"=&r"(status), "+m"(*ptr)
|
||||
: [ptr]"r"(ptr), [new_value]"r"(new_value)
|
||||
: "memory");
|
||||
return prev;
|
||||
}
|
||||
|
||||
/* Atomic increment, without explicit barriers */
|
||||
__ATOMIC_INLINE__ int32_t
|
||||
__bionic_atomic_inc(volatile int32_t *ptr)
|
||||
{
|
||||
int32_t prev, status;
|
||||
__asm__ __volatile__ ("1: ll %[prev], 0(%[ptr]) \n"
|
||||
" addiu %[status], %[prev], 1 \n"
|
||||
" sc %[status], 0(%[ptr]) \n"
|
||||
" beqz %[status], 1b \n"
|
||||
: [prev]"=&r" (prev), [status]"=&r"(status), "+m" (*ptr)
|
||||
: [ptr]"r"(ptr)
|
||||
: "memory");
|
||||
return prev;
|
||||
/* Atomic decrement, without explicit barriers. */
|
||||
__ATOMIC_INLINE__ int32_t __bionic_atomic_dec(volatile int32_t* ptr) {
|
||||
int32_t prev, status;
|
||||
__asm__ __volatile__ ("1: ll %[prev], 0(%[ptr]) \n"
|
||||
" addiu %[status], %[prev], -1 \n"
|
||||
" sc %[status], 0(%[ptr]) \n"
|
||||
" beqz %[status], 1b \n"
|
||||
: [prev]"=&r" (prev), [status]"=&r"(status), "+m" (*ptr)
|
||||
: [ptr]"r"(ptr)
|
||||
: "memory");
|
||||
return prev;
|
||||
}
|
||||
|
||||
/* Atomic decrement, without explicit barriers */
|
||||
__ATOMIC_INLINE__ int32_t
|
||||
__bionic_atomic_dec(volatile int32_t *ptr)
|
||||
{
|
||||
int32_t prev, status;
|
||||
__asm__ __volatile__ ("1: ll %[prev], 0(%[ptr]) \n"
|
||||
" addiu %[status], %[prev], -1 \n"
|
||||
" sc %[status], 0(%[ptr]) \n"
|
||||
" beqz %[status], 1b \n"
|
||||
: [prev]"=&r" (prev), [status]"=&r"(status), "+m" (*ptr)
|
||||
: [ptr]"r"(ptr)
|
||||
: "memory");
|
||||
return prev;
|
||||
}
|
||||
#endif /* BIONIC_ATOMIC_MIPS_H */
|
||||
|
||||
@ -19,28 +19,20 @@
|
||||
/* Define a full memory barrier, this is only needed if we build the
|
||||
* platform for a multi-core device.
|
||||
*/
|
||||
__ATOMIC_INLINE__ void __bionic_memory_barrier() {
|
||||
#if defined(ANDROID_SMP) && ANDROID_SMP == 1
|
||||
__ATOMIC_INLINE__ void
|
||||
__bionic_memory_barrier()
|
||||
{
|
||||
__asm__ __volatile__ ( "mfence" : : : "memory" );
|
||||
}
|
||||
__asm__ __volatile__ ( "mfence" : : : "memory" );
|
||||
#else
|
||||
__ATOMIC_INLINE__ void
|
||||
__bionic_memory_barrier()
|
||||
{
|
||||
/* A simple compiler barrier */
|
||||
__asm__ __volatile__ ( "" : : : "memory" );
|
||||
}
|
||||
/* A simple compiler barrier. */
|
||||
__asm__ __volatile__ ( "" : : : "memory" );
|
||||
#endif
|
||||
}
|
||||
|
||||
/* Compare-and-swap, without any explicit barriers. Note that this function
|
||||
* returns 0 on success, and 1 on failure. The opposite convention is typically
|
||||
* used on other platforms.
|
||||
*/
|
||||
__ATOMIC_INLINE__ int
|
||||
__bionic_cmpxchg(int32_t old_value, int32_t new_value, volatile int32_t* ptr)
|
||||
{
|
||||
__ATOMIC_INLINE__ int __bionic_cmpxchg(int32_t old_value, int32_t new_value, volatile int32_t* ptr) {
|
||||
int32_t prev;
|
||||
__asm__ __volatile__ ("lock; cmpxchgl %1, %2"
|
||||
: "=a" (prev)
|
||||
@ -49,40 +41,23 @@ __bionic_cmpxchg(int32_t old_value, int32_t new_value, volatile int32_t* ptr)
|
||||
return prev != old_value;
|
||||
}
|
||||
|
||||
|
||||
/* Swap, without any explicit barriers */
|
||||
__ATOMIC_INLINE__ int32_t
|
||||
__bionic_swap(int32_t new_value, volatile int32_t *ptr)
|
||||
{
|
||||
__asm__ __volatile__ ("xchgl %1, %0"
|
||||
: "=r" (new_value)
|
||||
: "m" (*ptr), "0" (new_value)
|
||||
: "memory");
|
||||
return new_value;
|
||||
/* Swap, without any explicit barriers. */
|
||||
__ATOMIC_INLINE__ int32_t __bionic_swap(int32_t new_value, volatile int32_t *ptr) {
|
||||
__asm__ __volatile__ ("xchgl %1, %0"
|
||||
: "=r" (new_value)
|
||||
: "m" (*ptr), "0" (new_value)
|
||||
: "memory");
|
||||
return new_value;
|
||||
}
|
||||
|
||||
/* Atomic increment, without explicit barriers */
|
||||
__ATOMIC_INLINE__ int32_t
|
||||
__bionic_atomic_inc(volatile int32_t *ptr)
|
||||
{
|
||||
int increment = 1;
|
||||
__asm__ __volatile__ ("lock; xaddl %0, %1"
|
||||
: "+r" (increment), "+m" (*ptr)
|
||||
: : "memory");
|
||||
/* increment now holds the old value of *ptr */
|
||||
return increment;
|
||||
}
|
||||
|
||||
/* Atomic decrement, without explicit barriers */
|
||||
__ATOMIC_INLINE__ int32_t
|
||||
__bionic_atomic_dec(volatile int32_t *ptr)
|
||||
{
|
||||
int increment = -1;
|
||||
__asm__ __volatile__ ("lock; xaddl %0, %1"
|
||||
: "+r" (increment), "+m" (*ptr)
|
||||
: : "memory");
|
||||
/* increment now holds the old value of *ptr */
|
||||
return increment;
|
||||
/* Atomic decrement, without explicit barriers. */
|
||||
__ATOMIC_INLINE__ int32_t __bionic_atomic_dec(volatile int32_t* ptr) {
|
||||
int increment = -1;
|
||||
__asm__ __volatile__ ("lock; xaddl %0, %1"
|
||||
: "+r" (increment), "+m" (*ptr)
|
||||
: : "memory");
|
||||
/* increment now holds the old value of *ptr */
|
||||
return increment;
|
||||
}
|
||||
|
||||
#endif /* BIONIC_ATOMIC_X86_H */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user