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am 26c5b2d4: Merge "[MIPS] Rewrite fenv.h for Android"

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* commit '26c5b2d460e3b2595eb7f0605edcd02753a13594':
  [MIPS] Rewrite fenv.h for Android
This commit is contained in:
Elliott Hughes 2013-01-07 13:48:55 -08:00 committed by Android Git Automerger
commit 2458d06fc1
1 changed files with 151 additions and 144 deletions
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295
libm/include/mips/fenv.h
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@ -26,193 +26,200 @@
* $FreeBSD: src/lib/msun/arm/fenv.h,v 1.5 2005/03/16 19:03:45 das Exp $ * $FreeBSD: src/lib/msun/arm/fenv.h,v 1.5 2005/03/16 19:03:45 das Exp $
*/ */
#ifndef _FENV_H_ /*
#define _FENV_H_ Rewritten for Android.
*/
/* MIPS FPU floating point control register bits.
*
* 31-25 -> floating point conditions code bits set by FP compare
* instructions
* 24 -> flush denormalized results to zero instead of
* causing unimplemented operation exception.
* 23 -> Condition bit
* 22 -> In conjunction with FS detects denormalized
* operands and replaces them internally with 0.
* 21 -> In conjunction with FS forces denormalized operands
* to the closest normalized value.
* 20-18 -> reserved (read as 0, write with 0)
* 17 -> cause bit for unimplemented operation
* 16 -> cause bit for invalid exception
* 15 -> cause bit for division by zero exception
* 14 -> cause bit for overflow exception
* 13 -> cause bit for underflow exception
* 12 -> cause bit for inexact exception
* 11 -> enable exception for invalid exception
* 10 -> enable exception for division by zero exception
* 9 -> enable exception for overflow exception
* 8 -> enable exception for underflow exception
* 7 -> enable exception for inexact exception
* 6 -> flag invalid exception
* 5 -> flag division by zero exception
* 4 -> flag overflow exception
* 3 -> flag underflow exception
* 2 -> flag inexact exception
* 1-0 -> rounding control
*
*
* Rounding Control:
* 00 - rounding to nearest (RN)
* 01 - rounding toward zero (RZ)
* 10 - rounding (up) toward plus infinity (RP)
* 11 - rounding (down)toward minus infinity (RM)
*/
#ifndef _FENV_H_
#define _FENV_H_
#include <sys/types.h> #include <sys/types.h>
__BEGIN_DECLS __BEGIN_DECLS
typedef __uint32_t fenv_t; typedef __uint32_t fenv_t;
typedef __uint32_t fexcept_t; typedef __uint32_t fexcept_t;
/* Exception flags */ /* Exception flags */
#define FE_INVALID 0x0001 #define FE_INVALID 0x40
#define FE_DIVBYZERO 0x0002 #define FE_DIVBYZERO 0x20
#define FE_OVERFLOW 0x0004 #define FE_OVERFLOW 0x10
#define FE_UNDERFLOW 0x0008 #define FE_UNDERFLOW 0x08
#define FE_INEXACT 0x0010 #define FE_INEXACT 0x04
#define FE_ALL_EXCEPT (FE_DIVBYZERO | FE_INEXACT | \ #define FE_ALL_EXCEPT (FE_DIVBYZERO | FE_INEXACT | \
FE_INVALID | FE_OVERFLOW | FE_UNDERFLOW) FE_INVALID | FE_OVERFLOW | FE_UNDERFLOW)
#define _FCSR_CAUSE_SHIFT 10
#define _ENABLE_SHIFT 5
#define _FCSR_ENABLE_MASK (FE_ALL_EXCEPT << _ENABLE_SHIFT)
/* Rounding modes */ /* Rounding modes */
#define FE_TONEAREST 0x0000 #define FE_TONEAREST 0x0000
#define FE_TOWARDZERO 0x0001 #define FE_TOWARDZERO 0x0001
#define FE_UPWARD 0x0002 #define FE_UPWARD 0x0002
#define FE_DOWNWARD 0x0003 #define FE_DOWNWARD 0x0003
#define _ROUND_MASK (FE_TONEAREST | FE_DOWNWARD | \ #define _FCSR_RMODE_SHIFT 0
FE_UPWARD | FE_TOWARDZERO) #define _FCSR_RMASK 0x3
/* Default floating-point environment */ /* Default floating-point environment */
extern const fenv_t __fe_dfl_env; extern const fenv_t __fe_dfl_env;
#define FE_DFL_ENV (&__fe_dfl_env) #define FE_DFL_ENV (&__fe_dfl_env)
/* We need to be able to map status flag positions to mask flag positions */ static __inline int fegetenv(fenv_t* __envp) {
#define _FPUSW_SHIFT 16 fenv_t _fcsr = 0;
#define _ENABLE_MASK (FE_ALL_EXCEPT << _FPUSW_SHIFT) #ifdef __mips_hard_float
__asm__ __volatile__("cfc1 %0,$31" : "=r" (_fcsr));
#ifdef ARM_HARD_FLOAT
#define __rfs(__fpsr) __asm __volatile("rfs %0" : "=r" (*(__fpsr)))
#define __wfs(__fpsr) __asm __volatile("wfs %0" : : "r" (__fpsr))
#else
#define __rfs(__fpsr)
#define __wfs(__fpsr)
#endif #endif
*__envp = _fcsr;
static __inline int return 0;
feclearexcept(int __excepts)
{
fexcept_t __fpsr;
__rfs(&__fpsr);
__fpsr &= ~__excepts;
__wfs(__fpsr);
return (0);
} }
static __inline int static __inline int fesetenv(const fenv_t* __envp) {
fegetexceptflag(fexcept_t *__flagp, int __excepts) fenv_t _fcsr = *__envp;
{ #ifdef __mips_hard_float
fexcept_t __fpsr; __asm__ __volatile__("ctc1 %0,$31" : : "r" (_fcsr));
#endif
__rfs(&__fpsr); return 0;
*__flagp = __fpsr & __excepts;
return (0);
} }
static __inline int static __inline int feclearexcept(int __excepts) {
fesetexceptflag(const fexcept_t *__flagp, int __excepts) fexcept_t __fcsr;
{ fegetenv(&__fcsr);
fexcept_t __fpsr; __excepts &= FE_ALL_EXCEPT;
__fcsr &= ~(__excepts | (__excepts << _FCSR_CAUSE_SHIFT));
__rfs(&__fpsr); fesetenv(&__fcsr);
__fpsr &= ~__excepts; return 0;
__fpsr |= *__flagp & __excepts;
__wfs(__fpsr);
return (0);
} }
static __inline int static __inline int fegetexceptflag(fexcept_t* __flagp, int __excepts) {
feraiseexcept(int __excepts) fexcept_t __fcsr;
{ fegetenv(&__fcsr);
fexcept_t __ex = __excepts; *__flagp = __fcsr & __excepts & FE_ALL_EXCEPT;
return 0;
fesetexceptflag(&__ex, __excepts); /* XXX */
return (0);
} }
static __inline int static __inline int fesetexceptflag(const fexcept_t* __flagp, int __excepts) {
fetestexcept(int __excepts) fexcept_t __fcsr;
{ fegetenv(&__fcsr);
fexcept_t __fpsr; /* Ensure that flags are all legal */
__excepts &= FE_ALL_EXCEPT;
__rfs(&__fpsr); __fcsr &= ~__excepts;
return (__fpsr & __excepts); __fcsr |= *__flagp & __excepts;
fesetenv(&__fcsr);
return 0;
} }
static __inline int static __inline int feraiseexcept(int __excepts) {
fegetround(void) fexcept_t __fcsr;
{ fegetenv(&__fcsr);
/* Ensure that flags are all legal */
/* __excepts &= FE_ALL_EXCEPT;
* Apparently, the rounding mode is specified as part of the /* Cause bit needs to be set as well for generating the exception*/
* instruction format on ARM, so the dynamic rounding mode is __fcsr |= __excepts | (__excepts << _FCSR_CAUSE_SHIFT);
* indeterminate. Some FPUs may differ. fesetenv(&__fcsr);
*/ return 0;
return (-1);
} }
static __inline int static __inline int fetestexcept(int __excepts) {
fesetround(int __round) fexcept_t __FCSR;
{ fegetenv(&__FCSR);
return (__FCSR & __excepts & FE_ALL_EXCEPT);
return (-1);
} }
static __inline int static __inline int fegetround(void) {
fegetenv(fenv_t *__envp) fenv_t _fcsr;
{ fegetenv(&_fcsr);
return (_fcsr & _FCSR_RMASK);
__rfs(__envp);
return (0);
} }
static __inline int static __inline int fesetround(int __round) {
feholdexcept(fenv_t *__envp) fenv_t _fcsr;
{ fegetenv(&_fcsr);
fenv_t __env; _fcsr &= ~_FCSR_RMASK;
_fcsr |= (__round & _FCSR_RMASK ) ;
__rfs(&__env); fesetenv(&_fcsr);
*__envp = __env; return 0;
__env &= ~(FE_ALL_EXCEPT | _ENABLE_MASK);
__wfs(__env);
return (0);
} }
static __inline int static __inline int feholdexcept(fenv_t* __envp) {
fesetenv(const fenv_t *__envp) fenv_t __env;
{ fegetenv(&__env);
*__envp = __env;
__wfs(*__envp); __env &= ~(FE_ALL_EXCEPT | _FCSR_ENABLE_MASK);
return (0); fesetenv(&__env);
return 0;
} }
static __inline int static __inline int feupdateenv(const fenv_t* __envp) {
feupdateenv(const fenv_t *__envp) fexcept_t __fcsr;
{ fegetenv(&__fcsr);
fexcept_t __fpsr; fesetenv(__envp);
feraiseexcept(__fcsr & FE_ALL_EXCEPT);
__rfs(&__fpsr); return 0;
__wfs(*__envp);
feraiseexcept(__fpsr & FE_ALL_EXCEPT);
return (0);
} }
#if __BSD_VISIBLE #if __BSD_VISIBLE
static __inline int static __inline int feenableexcept(int __mask) {
feenableexcept(int __mask) fenv_t __old_fcsr, __new_fcsr;
{ fegetenv(&__old_fcsr);
fenv_t __old_fpsr, __new_fpsr; __new_fcsr = __old_fcsr | (__mask & FE_ALL_EXCEPT) << _ENABLE_SHIFT;
fesetenv(&__new_fcsr);
__rfs(&__old_fpsr); return ((__old_fcsr >> _ENABLE_SHIFT) & FE_ALL_EXCEPT);
__new_fpsr = __old_fpsr | (__mask & FE_ALL_EXCEPT) << _FPUSW_SHIFT;
__wfs(__new_fpsr);
return ((__old_fpsr >> _FPUSW_SHIFT) & FE_ALL_EXCEPT);
} }
static __inline int static __inline int fedisableexcept(int __mask) {
fedisableexcept(int __mask) fenv_t __old_fcsr, __new_fcsr;
{ fegetenv(&__old_fcsr);
fenv_t __old_fpsr, __new_fpsr; __new_fcsr = __old_fcsr & ~((__mask & FE_ALL_EXCEPT) << _ENABLE_SHIFT);
fesetenv(&__new_fcsr);
__rfs(&__old_fpsr); return ((__old_fcsr >> _ENABLE_SHIFT) & FE_ALL_EXCEPT);
__new_fpsr = __old_fpsr & ~((__mask & FE_ALL_EXCEPT) << _FPUSW_SHIFT);
__wfs(__new_fpsr);
return ((__old_fpsr >> _FPUSW_SHIFT) & FE_ALL_EXCEPT);
} }
static __inline int static __inline int fegetexcept(void) {
fegetexcept(void) fenv_t __fcsr;
{ fegetenv(&__fcsr);
fenv_t __fpsr; return ((__fcsr & _FCSR_ENABLE_MASK) >> _ENABLE_SHIFT);
__rfs(&__fpsr);
return ((__fpsr & _ENABLE_MASK) >> _FPUSW_SHIFT);
} }
#endif /* __BSD_VISIBLE */ #endif /* __BSD_VISIBLE */
__END_DECLS __END_DECLS
#endif /* !_FENV_H_ */ #endif /* !_FENV_H_ */