generic-library/bionic
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

am 7d22a451: Merge "[MIPSR6] setjmp supports mips32r6 and FP64A/FPXX reg models"

Browse Source 
* commit '7d22a4519610f830178bbff32d961a2784354397':
  [MIPSR6] setjmp supports mips32r6 and FP64A/FPXX reg models
This commit is contained in:
Elliott Hughes
2014-07-24 04:03:03 +00:00
committed by Android Git Automerger
parent 3363e16ac9 7d22a45196
commit 0caa27b148
4 changed files with 96 additions and 244 deletions
Download Patch File Download Diff File Expand all files Collapse all files

85
libc/arch-mips/bionic/_setjmp.S
View File

@@ -44,17 +44,6 @@
FRAMESZ= MKFSIZ(0,4) FRAMESZ= MKFSIZ(0,4)
GPOFF= FRAMESZ-2*REGSZ GPOFF= FRAMESZ-2*REGSZ
#define FPREG64_S(FPR, OFF, BASE) \
swc1 FPR, OFF(BASE) ; \
mfhc1 t0, FPR ; \
sw t0, OFF+4(BASE) ;
#define FPREG64_L(FPR, OFF, BASE) \
lw t0, OFF+4(BASE) ; \
lw t1, OFF(BASE) ; \
mtc1 t1, FPR ; \
mthc1 t0, FPR ; \
LEAF(_setjmp, FRAMESZ) LEAF(_setjmp, FRAMESZ)
PTR_SUBU sp, FRAMESZ PTR_SUBU sp, FRAMESZ
SETUP_GP64(GPOFF, _setjmp) SETUP_GP64(GPOFF, _setjmp)
@@ -85,32 +74,19 @@ LEAF(_setjmp, FRAMESZ)
li v0, 1 # be nice if we could tell li v0, 1 # be nice if we could tell
REG_S v0, SC_FPUSED(a0) # sc_fpused = 1 REG_S v0, SC_FPUSED(a0) # sc_fpused = 1
cfc1 v0, $31 cfc1 v0, $31
s.d $f20, SC_FPREGS+((F20-F0)*REGSZ_FP)(a0)
s.d $f22, SC_FPREGS+((F22-F0)*REGSZ_FP)(a0)
s.d $f24, SC_FPREGS+((F24-F0)*REGSZ_FP)(a0)
s.d $f26, SC_FPREGS+((F26-F0)*REGSZ_FP)(a0)
s.d $f28, SC_FPREGS+((F28-F0)*REGSZ_FP)(a0)
s.d $f30, SC_FPREGS+((F30-F0)*REGSZ_FP)(a0)
#if _MIPS_FPSET == 32 #if _MIPS_FPSET == 32
FPREG64_S($f20, SC_FPREGS+((F20-F0)*REGSZ_FP), a0) s.d $f21, SC_FPREGS+((F21-F0)*REGSZ_FP)(a0)
FPREG64_S($f21, SC_FPREGS+((F21-F0)*REGSZ_FP), a0) s.d $f23, SC_FPREGS+((F23-F0)*REGSZ_FP)(a0)
FPREG64_S($f22, SC_FPREGS+((F22-F0)*REGSZ_FP), a0) s.d $f25, SC_FPREGS+((F25-F0)*REGSZ_FP)(a0)
FPREG64_S($f23, SC_FPREGS+((F23-F0)*REGSZ_FP), a0) s.d $f27, SC_FPREGS+((F27-F0)*REGSZ_FP)(a0)
FPREG64_S($f24, SC_FPREGS+((F24-F0)*REGSZ_FP), a0) s.d $f29, SC_FPREGS+((F29-F0)*REGSZ_FP)(a0)
FPREG64_S($f25, SC_FPREGS+((F25-F0)*REGSZ_FP), a0) s.d $f31, SC_FPREGS+((F31-F0)*REGSZ_FP)(a0)
FPREG64_S($f26, SC_FPREGS+((F26-F0)*REGSZ_FP), a0)
FPREG64_S($f27, SC_FPREGS+((F27-F0)*REGSZ_FP), a0)
FPREG64_S($f28, SC_FPREGS+((F28-F0)*REGSZ_FP), a0)
FPREG64_S($f29, SC_FPREGS+((F29-F0)*REGSZ_FP), a0)
FPREG64_S($f30, SC_FPREGS+((F30-F0)*REGSZ_FP), a0)
FPREG64_S($f31, SC_FPREGS+((F31-F0)*REGSZ_FP), a0)
#else
swc1 $f20, SC_FPREGS+((F20-F0)*REGSZ_FP)(a0)
swc1 $f21, SC_FPREGS+((F21-F0)*REGSZ_FP)(a0)
swc1 $f22, SC_FPREGS+((F22-F0)*REGSZ_FP)(a0)
swc1 $f23, SC_FPREGS+((F23-F0)*REGSZ_FP)(a0)
swc1 $f24, SC_FPREGS+((F24-F0)*REGSZ_FP)(a0)
swc1 $f25, SC_FPREGS+((F25-F0)*REGSZ_FP)(a0)
swc1 $f26, SC_FPREGS+((F26-F0)*REGSZ_FP)(a0)
swc1 $f27, SC_FPREGS+((F27-F0)*REGSZ_FP)(a0)
swc1 $f28, SC_FPREGS+((F28-F0)*REGSZ_FP)(a0)
swc1 $f29, SC_FPREGS+((F29-F0)*REGSZ_FP)(a0)
swc1 $f30, SC_FPREGS+((F30-F0)*REGSZ_FP)(a0)
swc1 $f31, SC_FPREGS+((F31-F0)*REGSZ_FP)(a0)
#endif #endif
REG_S v0, SC_FPREGS+((FSR-F0)*REGSZ)(a0) REG_S v0, SC_FPREGS+((FSR-F0)*REGSZ)(a0)
#endif /* !SOFTFLOAT */ #endif /* !SOFTFLOAT */
@@ -142,32 +118,19 @@ LEAF(_longjmp, FRAMESZ)
REG_L sp, SC_REGS+SP*REGSZ(a0) REG_L sp, SC_REGS+SP*REGSZ(a0)
#if !defined(SOFTFLOAT) #if !defined(SOFTFLOAT)
ctc1 v0, $31 ctc1 v0, $31
l.d $f20, SC_FPREGS+((F20-F0)*REGSZ_FP)(a0)
l.d $f22, SC_FPREGS+((F22-F0)*REGSZ_FP)(a0)
l.d $f24, SC_FPREGS+((F24-F0)*REGSZ_FP)(a0)
l.d $f26, SC_FPREGS+((F26-F0)*REGSZ_FP)(a0)
l.d $f28, SC_FPREGS+((F28-F0)*REGSZ_FP)(a0)
l.d $f30, SC_FPREGS+((F30-F0)*REGSZ_FP)(a0)
#if _MIPS_FPSET == 32 #if _MIPS_FPSET == 32
FPREG64_L($f20, SC_FPREGS+((F20-F0)*REGSZ_FP), a0) l.d $f21, SC_FPREGS+((F21-F0)*REGSZ_FP)(a0)
FPREG64_L($f21, SC_FPREGS+((F21-F0)*REGSZ_FP), a0) l.d $f23, SC_FPREGS+((F23-F0)*REGSZ_FP)(a0)
FPREG64_L($f22, SC_FPREGS+((F22-F0)*REGSZ_FP), a0) l.d $f25, SC_FPREGS+((F25-F0)*REGSZ_FP)(a0)
FPREG64_L($f23, SC_FPREGS+((F23-F0)*REGSZ_FP), a0) l.d $f27, SC_FPREGS+((F27-F0)*REGSZ_FP)(a0)
FPREG64_L($f24, SC_FPREGS+((F24-F0)*REGSZ_FP), a0) l.d $f29, SC_FPREGS+((F29-F0)*REGSZ_FP)(a0)
FPREG64_L($f25, SC_FPREGS+((F25-F0)*REGSZ_FP), a0) l.d $f31, SC_FPREGS+((F31-F0)*REGSZ_FP)(a0)
FPREG64_L($f26, SC_FPREGS+((F26-F0)*REGSZ_FP), a0)
FPREG64_L($f27, SC_FPREGS+((F27-F0)*REGSZ_FP), a0)
FPREG64_L($f28, SC_FPREGS+((F28-F0)*REGSZ_FP), a0)
FPREG64_L($f29, SC_FPREGS+((F29-F0)*REGSZ_FP), a0)
FPREG64_L($f30, SC_FPREGS+((F30-F0)*REGSZ_FP), a0)
FPREG64_L($f31, SC_FPREGS+((F31-F0)*REGSZ_FP), a0)
#else
lwc1 $f20, SC_FPREGS+((F20-F0)*REGSZ_FP)(a0)
lwc1 $f21, SC_FPREGS+((F21-F0)*REGSZ_FP)(a0)
lwc1 $f22, SC_FPREGS+((F22-F0)*REGSZ_FP)(a0)
lwc1 $f23, SC_FPREGS+((F23-F0)*REGSZ_FP)(a0)
lwc1 $f24, SC_FPREGS+((F24-F0)*REGSZ_FP)(a0)
lwc1 $f25, SC_FPREGS+((F25-F0)*REGSZ_FP)(a0)
lwc1 $f26, SC_FPREGS+((F26-F0)*REGSZ_FP)(a0)
lwc1 $f27, SC_FPREGS+((F27-F0)*REGSZ_FP)(a0)
lwc1 $f28, SC_FPREGS+((F28-F0)*REGSZ_FP)(a0)
lwc1 $f29, SC_FPREGS+((F29-F0)*REGSZ_FP)(a0)
lwc1 $f30, SC_FPREGS+((F30-F0)*REGSZ_FP)(a0)
lwc1 $f31, SC_FPREGS+((F31-F0)*REGSZ_FP)(a0)
#endif #endif
#endif /* !SOFTFLOAT */ #endif /* !SOFTFLOAT */
bne a1, zero, 1f bne a1, zero, 1f

85
libc/arch-mips/bionic/setjmp.S
View File

@@ -45,17 +45,6 @@ A0OFF= FRAMESZ-3*REGSZ
GPOFF= FRAMESZ-2*REGSZ GPOFF= FRAMESZ-2*REGSZ
RAOFF= FRAMESZ-1*REGSZ RAOFF= FRAMESZ-1*REGSZ
#define FPREG64_S(FPR, OFF, BASE) \
swc1 FPR, OFF(BASE) ; \
mfhc1 t0, FPR ; \
sw t0, OFF+4(BASE) ;
#define FPREG64_L(FPR, OFF, BASE) \
lw t0, OFF+4(BASE) ; \
lw t1, OFF(BASE) ; \
mtc1 t1, FPR ; \
mthc1 t0, FPR ; \
NON_LEAF(setjmp, FRAMESZ, ra) NON_LEAF(setjmp, FRAMESZ, ra)
.mask 0x80000000, RAOFF .mask 0x80000000, RAOFF
PTR_SUBU sp, FRAMESZ # allocate stack frame PTR_SUBU sp, FRAMESZ # allocate stack frame
@@ -98,32 +87,19 @@ NON_LEAF(setjmp, FRAMESZ, ra)
li v0, 1 # be nice if we could tell li v0, 1 # be nice if we could tell
REG_S v0, SC_FPUSED(a0) # sc_fpused = 1 REG_S v0, SC_FPUSED(a0) # sc_fpused = 1
cfc1 v0, $31 cfc1 v0, $31
s.d $f20, SC_FPREGS+((F20-F0)*REGSZ_FP)(a0)
s.d $f22, SC_FPREGS+((F22-F0)*REGSZ_FP)(a0)
s.d $f24, SC_FPREGS+((F24-F0)*REGSZ_FP)(a0)
s.d $f26, SC_FPREGS+((F26-F0)*REGSZ_FP)(a0)
s.d $f28, SC_FPREGS+((F28-F0)*REGSZ_FP)(a0)
s.d $f30, SC_FPREGS+((F30-F0)*REGSZ_FP)(a0)
#if _MIPS_FPSET == 32 #if _MIPS_FPSET == 32
FPREG64_S($f20, SC_FPREGS+((F20-F0)*REGSZ_FP), a0) s.d $f21, SC_FPREGS+((F21-F0)*REGSZ_FP)(a0)
FPREG64_S($f21, SC_FPREGS+((F21-F0)*REGSZ_FP), a0) s.d $f23, SC_FPREGS+((F23-F0)*REGSZ_FP)(a0)
FPREG64_S($f22, SC_FPREGS+((F22-F0)*REGSZ_FP), a0) s.d $f25, SC_FPREGS+((F25-F0)*REGSZ_FP)(a0)
FPREG64_S($f23, SC_FPREGS+((F23-F0)*REGSZ_FP), a0) s.d $f27, SC_FPREGS+((F27-F0)*REGSZ_FP)(a0)
FPREG64_S($f24, SC_FPREGS+((F24-F0)*REGSZ_FP), a0) s.d $f29, SC_FPREGS+((F29-F0)*REGSZ_FP)(a0)
FPREG64_S($f25, SC_FPREGS+((F25-F0)*REGSZ_FP), a0) s.d $f31, SC_FPREGS+((F31-F0)*REGSZ_FP)(a0)
FPREG64_S($f26, SC_FPREGS+((F26-F0)*REGSZ_FP), a0)
FPREG64_S($f27, SC_FPREGS+((F27-F0)*REGSZ_FP), a0)
FPREG64_S($f28, SC_FPREGS+((F28-F0)*REGSZ_FP), a0)
FPREG64_S($f29, SC_FPREGS+((F29-F0)*REGSZ_FP), a0)
FPREG64_S($f30, SC_FPREGS+((F30-F0)*REGSZ_FP), a0)
FPREG64_S($f31, SC_FPREGS+((F31-F0)*REGSZ_FP), a0)
#else
swc1 $f20, SC_FPREGS+((F20-F0)*REGSZ_FP)(a0)
swc1 $f21, SC_FPREGS+((F21-F0)*REGSZ_FP)(a0)
swc1 $f22, SC_FPREGS+((F22-F0)*REGSZ_FP)(a0)
swc1 $f23, SC_FPREGS+((F23-F0)*REGSZ_FP)(a0)
swc1 $f24, SC_FPREGS+((F24-F0)*REGSZ_FP)(a0)
swc1 $f25, SC_FPREGS+((F25-F0)*REGSZ_FP)(a0)
swc1 $f26, SC_FPREGS+((F26-F0)*REGSZ_FP)(a0)
swc1 $f27, SC_FPREGS+((F27-F0)*REGSZ_FP)(a0)
swc1 $f28, SC_FPREGS+((F28-F0)*REGSZ_FP)(a0)
swc1 $f29, SC_FPREGS+((F29-F0)*REGSZ_FP)(a0)
swc1 $f30, SC_FPREGS+((F30-F0)*REGSZ_FP)(a0)
swc1 $f31, SC_FPREGS+((F31-F0)*REGSZ_FP)(a0)
#endif #endif
REG_S v0, SC_FPREGS+((FSR-F0)*REGSZ)(a0) REG_S v0, SC_FPREGS+((FSR-F0)*REGSZ)(a0)
#endif /* !SOFTFLOAT */ #endif /* !SOFTFLOAT */
@@ -173,32 +149,19 @@ LEAF(longjmp, FRAMESZ)
#if !defined(SOFTFLOAT) #if !defined(SOFTFLOAT)
REG_L v0, SC_FPREGS+((FSR-F0)*REGSZ)(a0) REG_L v0, SC_FPREGS+((FSR-F0)*REGSZ)(a0)
ctc1 v0, $31 ctc1 v0, $31
l.d $f20, SC_FPREGS+((F20-F0)*REGSZ_FP)(a0)
l.d $f22, SC_FPREGS+((F22-F0)*REGSZ_FP)(a0)
l.d $f24, SC_FPREGS+((F24-F0)*REGSZ_FP)(a0)
l.d $f26, SC_FPREGS+((F26-F0)*REGSZ_FP)(a0)
l.d $f28, SC_FPREGS+((F28-F0)*REGSZ_FP)(a0)
l.d $f30, SC_FPREGS+((F30-F0)*REGSZ_FP)(a0)
#if _MIPS_FPSET == 32 #if _MIPS_FPSET == 32
FPREG64_L($f20, SC_FPREGS+((F20-F0)*REGSZ_FP), a0) l.d $f21, SC_FPREGS+((F21-F0)*REGSZ_FP)(a0)
FPREG64_L($f21, SC_FPREGS+((F21-F0)*REGSZ_FP), a0) l.d $f23, SC_FPREGS+((F23-F0)*REGSZ_FP)(a0)
FPREG64_L($f22, SC_FPREGS+((F22-F0)*REGSZ_FP), a0) l.d $f25, SC_FPREGS+((F25-F0)*REGSZ_FP)(a0)
FPREG64_L($f23, SC_FPREGS+((F23-F0)*REGSZ_FP), a0) l.d $f27, SC_FPREGS+((F27-F0)*REGSZ_FP)(a0)
FPREG64_L($f24, SC_FPREGS+((F24-F0)*REGSZ_FP), a0) l.d $f29, SC_FPREGS+((F29-F0)*REGSZ_FP)(a0)
FPREG64_L($f25, SC_FPREGS+((F25-F0)*REGSZ_FP), a0) l.d $f31, SC_FPREGS+((F31-F0)*REGSZ_FP)(a0)
FPREG64_L($f26, SC_FPREGS+((F26-F0)*REGSZ_FP), a0)
FPREG64_L($f27, SC_FPREGS+((F27-F0)*REGSZ_FP), a0)
FPREG64_L($f28, SC_FPREGS+((F28-F0)*REGSZ_FP), a0)
FPREG64_L($f29, SC_FPREGS+((F29-F0)*REGSZ_FP), a0)
FPREG64_L($f30, SC_FPREGS+((F30-F0)*REGSZ_FP), a0)
FPREG64_L($f31, SC_FPREGS+((F31-F0)*REGSZ_FP), a0)
#else
lwc1 $f20, SC_FPREGS+((F20-F0)*REGSZ_FP)(a0)
lwc1 $f21, SC_FPREGS+((F21-F0)*REGSZ_FP)(a0)
lwc1 $f22, SC_FPREGS+((F22-F0)*REGSZ_FP)(a0)
lwc1 $f23, SC_FPREGS+((F23-F0)*REGSZ_FP)(a0)
lwc1 $f24, SC_FPREGS+((F24-F0)*REGSZ_FP)(a0)
lwc1 $f25, SC_FPREGS+((F25-F0)*REGSZ_FP)(a0)
lwc1 $f26, SC_FPREGS+((F26-F0)*REGSZ_FP)(a0)
lwc1 $f27, SC_FPREGS+((F27-F0)*REGSZ_FP)(a0)
lwc1 $f28, SC_FPREGS+((F28-F0)*REGSZ_FP)(a0)
lwc1 $f29, SC_FPREGS+((F29-F0)*REGSZ_FP)(a0)
lwc1 $f30, SC_FPREGS+((F30-F0)*REGSZ_FP)(a0)
lwc1 $f31, SC_FPREGS+((F31-F0)*REGSZ_FP)(a0)
#endif #endif
#endif /* !SOFTFLOAT */ #endif /* !SOFTFLOAT */
bne a1, zero, 1f bne a1, zero, 1f

85
libc/arch-mips64/bionic/_setjmp.S
View File

@@ -44,17 +44,6 @@
FRAMESZ= MKFSIZ(0,4) FRAMESZ= MKFSIZ(0,4)
GPOFF= FRAMESZ-2*REGSZ GPOFF= FRAMESZ-2*REGSZ
#define FPREG64_S(FPR, OFF, BASE) \
swc1 FPR, OFF(BASE) ; \
mfhc1 t0, FPR ; \
sw t0, OFF+4(BASE) ;
#define FPREG64_L(FPR, OFF, BASE) \
lw t0, OFF+4(BASE) ; \
lw t1, OFF(BASE) ; \
mtc1 t1, FPR ; \
mthc1 t0, FPR ; \
LEAF(_setjmp, FRAMESZ) LEAF(_setjmp, FRAMESZ)
PTR_SUBU sp, FRAMESZ PTR_SUBU sp, FRAMESZ
SETUP_GP64(GPOFF, _setjmp) SETUP_GP64(GPOFF, _setjmp)
@@ -85,32 +74,19 @@ LEAF(_setjmp, FRAMESZ)
li v0, 1 # be nice if we could tell li v0, 1 # be nice if we could tell
REG_S v0, SC_FPUSED(a0) # sc_fpused = 1 REG_S v0, SC_FPUSED(a0) # sc_fpused = 1
cfc1 v0, $31 cfc1 v0, $31
s.d $f20, SC_FPREGS+((F20-F0)*REGSZ_FP)(a0)
s.d $f22, SC_FPREGS+((F22-F0)*REGSZ_FP)(a0)
s.d $f24, SC_FPREGS+((F24-F0)*REGSZ_FP)(a0)
s.d $f26, SC_FPREGS+((F26-F0)*REGSZ_FP)(a0)
s.d $f28, SC_FPREGS+((F28-F0)*REGSZ_FP)(a0)
s.d $f30, SC_FPREGS+((F30-F0)*REGSZ_FP)(a0)
#if _MIPS_FPSET == 32 #if _MIPS_FPSET == 32
FPREG64_S($f20, SC_FPREGS+((F20-F0)*REGSZ_FP), a0) s.d $f21, SC_FPREGS+((F21-F0)*REGSZ_FP)(a0)
FPREG64_S($f21, SC_FPREGS+((F21-F0)*REGSZ_FP), a0) s.d $f23, SC_FPREGS+((F23-F0)*REGSZ_FP)(a0)
FPREG64_S($f22, SC_FPREGS+((F22-F0)*REGSZ_FP), a0) s.d $f25, SC_FPREGS+((F25-F0)*REGSZ_FP)(a0)
FPREG64_S($f23, SC_FPREGS+((F23-F0)*REGSZ_FP), a0) s.d $f27, SC_FPREGS+((F27-F0)*REGSZ_FP)(a0)
FPREG64_S($f24, SC_FPREGS+((F24-F0)*REGSZ_FP), a0) s.d $f29, SC_FPREGS+((F29-F0)*REGSZ_FP)(a0)
FPREG64_S($f25, SC_FPREGS+((F25-F0)*REGSZ_FP), a0) s.d $f31, SC_FPREGS+((F31-F0)*REGSZ_FP)(a0)
FPREG64_S($f26, SC_FPREGS+((F26-F0)*REGSZ_FP), a0)
FPREG64_S($f27, SC_FPREGS+((F27-F0)*REGSZ_FP), a0)
FPREG64_S($f28, SC_FPREGS+((F28-F0)*REGSZ_FP), a0)
FPREG64_S($f29, SC_FPREGS+((F29-F0)*REGSZ_FP), a0)
FPREG64_S($f30, SC_FPREGS+((F30-F0)*REGSZ_FP), a0)
FPREG64_S($f31, SC_FPREGS+((F31-F0)*REGSZ_FP), a0)
#else
swc1 $f20, SC_FPREGS+((F20-F0)*REGSZ_FP)(a0)
swc1 $f21, SC_FPREGS+((F21-F0)*REGSZ_FP)(a0)
swc1 $f22, SC_FPREGS+((F22-F0)*REGSZ_FP)(a0)
swc1 $f23, SC_FPREGS+((F23-F0)*REGSZ_FP)(a0)
swc1 $f24, SC_FPREGS+((F24-F0)*REGSZ_FP)(a0)
swc1 $f25, SC_FPREGS+((F25-F0)*REGSZ_FP)(a0)
swc1 $f26, SC_FPREGS+((F26-F0)*REGSZ_FP)(a0)
swc1 $f27, SC_FPREGS+((F27-F0)*REGSZ_FP)(a0)
swc1 $f28, SC_FPREGS+((F28-F0)*REGSZ_FP)(a0)
swc1 $f29, SC_FPREGS+((F29-F0)*REGSZ_FP)(a0)
swc1 $f30, SC_FPREGS+((F30-F0)*REGSZ_FP)(a0)
swc1 $f31, SC_FPREGS+((F31-F0)*REGSZ_FP)(a0)
#endif #endif
REG_S v0, SC_FPREGS+((FSR-F0)*REGSZ)(a0) REG_S v0, SC_FPREGS+((FSR-F0)*REGSZ)(a0)
#endif /* !SOFTFLOAT */ #endif /* !SOFTFLOAT */
@@ -142,32 +118,19 @@ LEAF(_longjmp, FRAMESZ)
REG_L sp, SC_REGS+SP*REGSZ(a0) REG_L sp, SC_REGS+SP*REGSZ(a0)
#if !defined(SOFTFLOAT) #if !defined(SOFTFLOAT)
ctc1 v0, $31 ctc1 v0, $31
l.d $f20, SC_FPREGS+((F20-F0)*REGSZ_FP)(a0)
l.d $f22, SC_FPREGS+((F22-F0)*REGSZ_FP)(a0)
l.d $f24, SC_FPREGS+((F24-F0)*REGSZ_FP)(a0)
l.d $f26, SC_FPREGS+((F26-F0)*REGSZ_FP)(a0)
l.d $f28, SC_FPREGS+((F28-F0)*REGSZ_FP)(a0)
l.d $f30, SC_FPREGS+((F30-F0)*REGSZ_FP)(a0)
#if _MIPS_FPSET == 32 #if _MIPS_FPSET == 32
FPREG64_L($f20, SC_FPREGS+((F20-F0)*REGSZ_FP), a0) l.d $f21, SC_FPREGS+((F21-F0)*REGSZ_FP)(a0)
FPREG64_L($f21, SC_FPREGS+((F21-F0)*REGSZ_FP), a0) l.d $f23, SC_FPREGS+((F23-F0)*REGSZ_FP)(a0)
FPREG64_L($f22, SC_FPREGS+((F22-F0)*REGSZ_FP), a0) l.d $f25, SC_FPREGS+((F25-F0)*REGSZ_FP)(a0)
FPREG64_L($f23, SC_FPREGS+((F23-F0)*REGSZ_FP), a0) l.d $f27, SC_FPREGS+((F27-F0)*REGSZ_FP)(a0)
FPREG64_L($f24, SC_FPREGS+((F24-F0)*REGSZ_FP), a0) l.d $f29, SC_FPREGS+((F29-F0)*REGSZ_FP)(a0)
FPREG64_L($f25, SC_FPREGS+((F25-F0)*REGSZ_FP), a0) l.d $f31, SC_FPREGS+((F31-F0)*REGSZ_FP)(a0)
FPREG64_L($f26, SC_FPREGS+((F26-F0)*REGSZ_FP), a0)
FPREG64_L($f27, SC_FPREGS+((F27-F0)*REGSZ_FP), a0)
FPREG64_L($f28, SC_FPREGS+((F28-F0)*REGSZ_FP), a0)
FPREG64_L($f29, SC_FPREGS+((F29-F0)*REGSZ_FP), a0)
FPREG64_L($f30, SC_FPREGS+((F30-F0)*REGSZ_FP), a0)
FPREG64_L($f31, SC_FPREGS+((F31-F0)*REGSZ_FP), a0)
#else
lwc1 $f20, SC_FPREGS+((F20-F0)*REGSZ_FP)(a0)
lwc1 $f21, SC_FPREGS+((F21-F0)*REGSZ_FP)(a0)
lwc1 $f22, SC_FPREGS+((F22-F0)*REGSZ_FP)(a0)
lwc1 $f23, SC_FPREGS+((F23-F0)*REGSZ_FP)(a0)
lwc1 $f24, SC_FPREGS+((F24-F0)*REGSZ_FP)(a0)
lwc1 $f25, SC_FPREGS+((F25-F0)*REGSZ_FP)(a0)
lwc1 $f26, SC_FPREGS+((F26-F0)*REGSZ_FP)(a0)
lwc1 $f27, SC_FPREGS+((F27-F0)*REGSZ_FP)(a0)
lwc1 $f28, SC_FPREGS+((F28-F0)*REGSZ_FP)(a0)
lwc1 $f29, SC_FPREGS+((F29-F0)*REGSZ_FP)(a0)
lwc1 $f30, SC_FPREGS+((F30-F0)*REGSZ_FP)(a0)
lwc1 $f31, SC_FPREGS+((F31-F0)*REGSZ_FP)(a0)
#endif #endif
#endif /* !SOFTFLOAT */ #endif /* !SOFTFLOAT */
bne a1, zero, 1f bne a1, zero, 1f

85
libc/arch-mips64/bionic/setjmp.S
View File

@@ -45,17 +45,6 @@ A0OFF= FRAMESZ-3*REGSZ
GPOFF= FRAMESZ-2*REGSZ GPOFF= FRAMESZ-2*REGSZ
RAOFF= FRAMESZ-1*REGSZ RAOFF= FRAMESZ-1*REGSZ
#define FPREG64_S(FPR, OFF, BASE) \
swc1 FPR, OFF(BASE) ; \
mfhc1 t0, FPR ; \
sw t0, OFF+4(BASE) ;
#define FPREG64_L(FPR, OFF, BASE) \
lw t0, OFF+4(BASE) ; \
lw t1, OFF(BASE) ; \
mtc1 t1, FPR ; \
mthc1 t0, FPR ; \
NON_LEAF(setjmp, FRAMESZ, ra) NON_LEAF(setjmp, FRAMESZ, ra)
.mask 0x80000000, RAOFF .mask 0x80000000, RAOFF
PTR_SUBU sp, FRAMESZ # allocate stack frame PTR_SUBU sp, FRAMESZ # allocate stack frame
@@ -98,32 +87,19 @@ NON_LEAF(setjmp, FRAMESZ, ra)
li v0, 1 # be nice if we could tell li v0, 1 # be nice if we could tell
REG_S v0, SC_FPUSED(a0) # sc_fpused = 1 REG_S v0, SC_FPUSED(a0) # sc_fpused = 1
cfc1 v0, $31 cfc1 v0, $31
s.d $f20, SC_FPREGS+((F20-F0)*REGSZ_FP)(a0)
s.d $f22, SC_FPREGS+((F22-F0)*REGSZ_FP)(a0)
s.d $f24, SC_FPREGS+((F24-F0)*REGSZ_FP)(a0)
s.d $f26, SC_FPREGS+((F26-F0)*REGSZ_FP)(a0)
s.d $f28, SC_FPREGS+((F28-F0)*REGSZ_FP)(a0)
s.d $f30, SC_FPREGS+((F30-F0)*REGSZ_FP)(a0)
#if _MIPS_FPSET == 32 #if _MIPS_FPSET == 32
FPREG64_S($f20, SC_FPREGS+((F20-F0)*REGSZ_FP), a0) s.d $f21, SC_FPREGS+((F21-F0)*REGSZ_FP)(a0)
FPREG64_S($f21, SC_FPREGS+((F21-F0)*REGSZ_FP), a0) s.d $f23, SC_FPREGS+((F23-F0)*REGSZ_FP)(a0)
FPREG64_S($f22, SC_FPREGS+((F22-F0)*REGSZ_FP), a0) s.d $f25, SC_FPREGS+((F25-F0)*REGSZ_FP)(a0)
FPREG64_S($f23, SC_FPREGS+((F23-F0)*REGSZ_FP), a0) s.d $f27, SC_FPREGS+((F27-F0)*REGSZ_FP)(a0)
FPREG64_S($f24, SC_FPREGS+((F24-F0)*REGSZ_FP), a0) s.d $f29, SC_FPREGS+((F29-F0)*REGSZ_FP)(a0)
FPREG64_S($f25, SC_FPREGS+((F25-F0)*REGSZ_FP), a0) s.d $f31, SC_FPREGS+((F31-F0)*REGSZ_FP)(a0)
FPREG64_S($f26, SC_FPREGS+((F26-F0)*REGSZ_FP), a0)
FPREG64_S($f27, SC_FPREGS+((F27-F0)*REGSZ_FP), a0)
FPREG64_S($f28, SC_FPREGS+((F28-F0)*REGSZ_FP), a0)
FPREG64_S($f29, SC_FPREGS+((F29-F0)*REGSZ_FP), a0)
FPREG64_S($f30, SC_FPREGS+((F30-F0)*REGSZ_FP), a0)
FPREG64_S($f31, SC_FPREGS+((F31-F0)*REGSZ_FP), a0)
#else
swc1 $f20, SC_FPREGS+((F20-F0)*REGSZ_FP)(a0)
swc1 $f21, SC_FPREGS+((F21-F0)*REGSZ_FP)(a0)
swc1 $f22, SC_FPREGS+((F22-F0)*REGSZ_FP)(a0)
swc1 $f23, SC_FPREGS+((F23-F0)*REGSZ_FP)(a0)
swc1 $f24, SC_FPREGS+((F24-F0)*REGSZ_FP)(a0)
swc1 $f25, SC_FPREGS+((F25-F0)*REGSZ_FP)(a0)
swc1 $f26, SC_FPREGS+((F26-F0)*REGSZ_FP)(a0)
swc1 $f27, SC_FPREGS+((F27-F0)*REGSZ_FP)(a0)
swc1 $f28, SC_FPREGS+((F28-F0)*REGSZ_FP)(a0)
swc1 $f29, SC_FPREGS+((F29-F0)*REGSZ_FP)(a0)
swc1 $f30, SC_FPREGS+((F30-F0)*REGSZ_FP)(a0)
swc1 $f31, SC_FPREGS+((F31-F0)*REGSZ_FP)(a0)
#endif #endif
REG_S v0, SC_FPREGS+((FSR-F0)*REGSZ)(a0) REG_S v0, SC_FPREGS+((FSR-F0)*REGSZ)(a0)
#endif /* !SOFTFLOAT */ #endif /* !SOFTFLOAT */
@@ -173,32 +149,19 @@ LEAF(longjmp, FRAMESZ)
#if !defined(SOFTFLOAT) #if !defined(SOFTFLOAT)
REG_L v0, SC_FPREGS+((FSR-F0)*REGSZ)(a0) REG_L v0, SC_FPREGS+((FSR-F0)*REGSZ)(a0)
ctc1 v0, $31 ctc1 v0, $31
l.d $f20, SC_FPREGS+((F20-F0)*REGSZ_FP)(a0)
l.d $f22, SC_FPREGS+((F22-F0)*REGSZ_FP)(a0)
l.d $f24, SC_FPREGS+((F24-F0)*REGSZ_FP)(a0)
l.d $f26, SC_FPREGS+((F26-F0)*REGSZ_FP)(a0)
l.d $f28, SC_FPREGS+((F28-F0)*REGSZ_FP)(a0)
l.d $f30, SC_FPREGS+((F30-F0)*REGSZ_FP)(a0)
#if _MIPS_FPSET == 32 #if _MIPS_FPSET == 32
FPREG64_L($f20, SC_FPREGS+((F20-F0)*REGSZ_FP), a0) l.d $f21, SC_FPREGS+((F21-F0)*REGSZ_FP)(a0)
FPREG64_L($f21, SC_FPREGS+((F21-F0)*REGSZ_FP), a0) l.d $f23, SC_FPREGS+((F23-F0)*REGSZ_FP)(a0)
FPREG64_L($f22, SC_FPREGS+((F22-F0)*REGSZ_FP), a0) l.d $f25, SC_FPREGS+((F25-F0)*REGSZ_FP)(a0)
FPREG64_L($f23, SC_FPREGS+((F23-F0)*REGSZ_FP), a0) l.d $f27, SC_FPREGS+((F27-F0)*REGSZ_FP)(a0)
FPREG64_L($f24, SC_FPREGS+((F24-F0)*REGSZ_FP), a0) l.d $f29, SC_FPREGS+((F29-F0)*REGSZ_FP)(a0)
FPREG64_L($f25, SC_FPREGS+((F25-F0)*REGSZ_FP), a0) l.d $f31, SC_FPREGS+((F31-F0)*REGSZ_FP)(a0)
FPREG64_L($f26, SC_FPREGS+((F26-F0)*REGSZ_FP), a0)
FPREG64_L($f27, SC_FPREGS+((F27-F0)*REGSZ_FP), a0)
FPREG64_L($f28, SC_FPREGS+((F28-F0)*REGSZ_FP), a0)
FPREG64_L($f29, SC_FPREGS+((F29-F0)*REGSZ_FP), a0)
FPREG64_L($f30, SC_FPREGS+((F30-F0)*REGSZ_FP), a0)
FPREG64_L($f31, SC_FPREGS+((F31-F0)*REGSZ_FP), a0)
#else
lwc1 $f20, SC_FPREGS+((F20-F0)*REGSZ_FP)(a0)
lwc1 $f21, SC_FPREGS+((F21-F0)*REGSZ_FP)(a0)
lwc1 $f22, SC_FPREGS+((F22-F0)*REGSZ_FP)(a0)
lwc1 $f23, SC_FPREGS+((F23-F0)*REGSZ_FP)(a0)
lwc1 $f24, SC_FPREGS+((F24-F0)*REGSZ_FP)(a0)
lwc1 $f25, SC_FPREGS+((F25-F0)*REGSZ_FP)(a0)
lwc1 $f26, SC_FPREGS+((F26-F0)*REGSZ_FP)(a0)
lwc1 $f27, SC_FPREGS+((F27-F0)*REGSZ_FP)(a0)
lwc1 $f28, SC_FPREGS+((F28-F0)*REGSZ_FP)(a0)
lwc1 $f29, SC_FPREGS+((F29-F0)*REGSZ_FP)(a0)
lwc1 $f30, SC_FPREGS+((F30-F0)*REGSZ_FP)(a0)
lwc1 $f31, SC_FPREGS+((F31-F0)*REGSZ_FP)(a0)
#endif #endif
#endif /* !SOFTFLOAT */ #endif /* !SOFTFLOAT */
bne a1, zero, 1f bne a1, zero, 1f