2009-03-04 04:28:35 +01:00
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/****************************************************************************
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****************************************************************************
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***
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*** This header was automatically generated from a Linux kernel header
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*** of the same name, to make information necessary for userspace to
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*** call into the kernel available to libc. It contains only constants,
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*** structures, and macros generated from the original header, and thus,
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*** contains no copyrightable information.
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***
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2012-03-08 06:13:49 +01:00
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*** To edit the content of this header, modify the corresponding
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*** source file (e.g. under external/kernel-headers/original/) then
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*** run bionic/libc/kernel/tools/update_all.py
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***
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*** Any manual change here will be lost the next time this script will
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*** be run. You've been warned!
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***
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2009-03-04 04:28:35 +01:00
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****************************************************************************
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****************************************************************************/
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#ifndef __ASM_ARCH_OMAP_FPGA_H
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#define __ASM_ARCH_OMAP_FPGA_H
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#define omap1510_fpga_init_irq() (0)
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#define fpga_read(reg) __raw_readb(reg)
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2012-03-08 06:13:49 +01:00
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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2009-03-04 04:28:35 +01:00
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#define fpga_write(val, reg) __raw_writeb(val, reg)
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#define H2P2_DBG_FPGA_BASE 0xE8000000
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#define H2P2_DBG_FPGA_SIZE SZ_4K
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#define H2P2_DBG_FPGA_START 0x04000000
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2012-03-08 06:13:49 +01:00
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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2009-03-04 04:28:35 +01:00
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#define H2P2_DBG_FPGA_ETHR_START (H2P2_DBG_FPGA_START + 0x300)
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#define H2P2_DBG_FPGA_FPGA_REV (H2P2_DBG_FPGA_BASE + 0x10)
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#define H2P2_DBG_FPGA_BOARD_REV (H2P2_DBG_FPGA_BASE + 0x12)
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#define H2P2_DBG_FPGA_GPIO (H2P2_DBG_FPGA_BASE + 0x14)
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2012-03-08 06:13:49 +01:00
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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2009-03-04 04:28:35 +01:00
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#define H2P2_DBG_FPGA_LEDS (H2P2_DBG_FPGA_BASE + 0x16)
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#define H2P2_DBG_FPGA_MISC_INPUTS (H2P2_DBG_FPGA_BASE + 0x18)
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#define H2P2_DBG_FPGA_LAN_STATUS (H2P2_DBG_FPGA_BASE + 0x1A)
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#define H2P2_DBG_FPGA_LAN_RESET (H2P2_DBG_FPGA_BASE + 0x1C)
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2012-03-08 06:13:49 +01:00
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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2009-03-04 04:28:35 +01:00
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struct h2p2_dbg_fpga {
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u16 smc91x[8];
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u16 fpga_rev;
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u16 board_rev;
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2012-03-08 06:13:49 +01:00
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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2009-03-04 04:28:35 +01:00
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u16 gpio_outputs;
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u16 leds;
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u16 misc_inputs;
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u16 lan_status;
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2012-03-08 06:13:49 +01:00
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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2009-03-04 04:28:35 +01:00
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u16 lan_reset;
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u16 reserved0;
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u16 ps2_data;
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u16 ps2_ctrl;
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2012-03-08 06:13:49 +01:00
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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2009-03-04 04:28:35 +01:00
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};
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#define H2P2_DBG_FPGA_LED_GREEN (1 << 15)
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#define H2P2_DBG_FPGA_LED_AMBER (1 << 14)
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#define H2P2_DBG_FPGA_LED_RED (1 << 13)
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define H2P2_DBG_FPGA_LED_BLUE (1 << 12)
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#define H2P2_DBG_FPGA_LOAD_METER (1 << 0)
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#define H2P2_DBG_FPGA_LOAD_METER_SIZE 11
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#define H2P2_DBG_FPGA_LOAD_METER_MASK ((1 << H2P2_DBG_FPGA_LOAD_METER_SIZE) - 1)
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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2009-03-04 04:28:35 +01:00
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#define H2P2_DBG_FPGA_P2_LED_TIMER (1 << 0)
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#define H2P2_DBG_FPGA_P2_LED_IDLE (1 << 1)
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#define OMAP1510_FPGA_BASE 0xE8000000
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#define OMAP1510_FPGA_SIZE SZ_4K
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define OMAP1510_FPGA_START 0x08000000
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#define OMAP1510_FPGA_REV_LOW (OMAP1510_FPGA_BASE + 0x0)
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#define OMAP1510_FPGA_REV_HIGH (OMAP1510_FPGA_BASE + 0x1)
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#define OMAP1510_FPGA_LCD_PANEL_CONTROL (OMAP1510_FPGA_BASE + 0x2)
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2012-03-08 06:13:49 +01:00
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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2009-03-04 04:28:35 +01:00
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#define OMAP1510_FPGA_LED_DIGIT (OMAP1510_FPGA_BASE + 0x3)
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#define INNOVATOR_FPGA_HID_SPI (OMAP1510_FPGA_BASE + 0x4)
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#define OMAP1510_FPGA_POWER (OMAP1510_FPGA_BASE + 0x5)
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#define OMAP1510_FPGA_ISR_LO (OMAP1510_FPGA_BASE + 0x6)
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2012-03-08 06:13:49 +01:00
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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2009-03-04 04:28:35 +01:00
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#define OMAP1510_FPGA_ISR_HI (OMAP1510_FPGA_BASE + 0x7)
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#define OMAP1510_FPGA_IMR_LO (OMAP1510_FPGA_BASE + 0x8)
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#define OMAP1510_FPGA_IMR_HI (OMAP1510_FPGA_BASE + 0x9)
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#define OMAP1510_FPGA_HOST_RESET (OMAP1510_FPGA_BASE + 0xa)
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2012-03-08 06:13:49 +01:00
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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2009-03-04 04:28:35 +01:00
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#define OMAP1510_FPGA_RST (OMAP1510_FPGA_BASE + 0xb)
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#define OMAP1510_FPGA_AUDIO (OMAP1510_FPGA_BASE + 0xc)
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#define OMAP1510_FPGA_DIP (OMAP1510_FPGA_BASE + 0xe)
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#define OMAP1510_FPGA_FPGA_IO (OMAP1510_FPGA_BASE + 0xf)
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2012-03-08 06:13:49 +01:00
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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2009-03-04 04:28:35 +01:00
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#define OMAP1510_FPGA_UART1 (OMAP1510_FPGA_BASE + 0x14)
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#define OMAP1510_FPGA_UART2 (OMAP1510_FPGA_BASE + 0x15)
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#define OMAP1510_FPGA_OMAP1510_STATUS (OMAP1510_FPGA_BASE + 0x16)
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#define OMAP1510_FPGA_BOARD_REV (OMAP1510_FPGA_BASE + 0x18)
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2012-03-08 06:13:49 +01:00
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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2009-03-04 04:28:35 +01:00
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#define OMAP1510P1_PPT_DATA (OMAP1510_FPGA_BASE + 0x100)
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#define OMAP1510P1_PPT_STATUS (OMAP1510_FPGA_BASE + 0x101)
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#define OMAP1510P1_PPT_CONTROL (OMAP1510_FPGA_BASE + 0x102)
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#define OMAP1510_FPGA_TOUCHSCREEN (OMAP1510_FPGA_BASE + 0x204)
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2012-03-08 06:13:49 +01:00
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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2009-03-04 04:28:35 +01:00
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#define INNOVATOR_FPGA_INFO (OMAP1510_FPGA_BASE + 0x205)
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#define INNOVATOR_FPGA_LCD_BRIGHT_LO (OMAP1510_FPGA_BASE + 0x206)
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#define INNOVATOR_FPGA_LCD_BRIGHT_HI (OMAP1510_FPGA_BASE + 0x207)
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#define INNOVATOR_FPGA_LED_GRN_LO (OMAP1510_FPGA_BASE + 0x208)
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2012-03-08 06:13:49 +01:00
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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2009-03-04 04:28:35 +01:00
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#define INNOVATOR_FPGA_LED_GRN_HI (OMAP1510_FPGA_BASE + 0x209)
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#define INNOVATOR_FPGA_LED_RED_LO (OMAP1510_FPGA_BASE + 0x20a)
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#define INNOVATOR_FPGA_LED_RED_HI (OMAP1510_FPGA_BASE + 0x20b)
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#define INNOVATOR_FPGA_CAM_USB_CONTROL (OMAP1510_FPGA_BASE + 0x20c)
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2012-03-08 06:13:49 +01:00
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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2009-03-04 04:28:35 +01:00
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#define INNOVATOR_FPGA_EXP_CONTROL (OMAP1510_FPGA_BASE + 0x20d)
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#define INNOVATOR_FPGA_ISR2 (OMAP1510_FPGA_BASE + 0x20e)
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#define INNOVATOR_FPGA_IMR2 (OMAP1510_FPGA_BASE + 0x210)
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#define OMAP1510_FPGA_ETHR_START (OMAP1510_FPGA_START + 0x300)
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2012-03-08 06:13:49 +01:00
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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2009-03-04 04:28:35 +01:00
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#define OMAP1510_FPGA_RESET_VALUE 0x42
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#define OMAP1510_FPGA_PCR_IF_PD0 (1 << 7)
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#define OMAP1510_FPGA_PCR_COM2_EN (1 << 6)
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#define OMAP1510_FPGA_PCR_COM1_EN (1 << 5)
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define OMAP1510_FPGA_PCR_EXP_PD0 (1 << 4)
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#define OMAP1510_FPGA_PCR_EXP_PD1 (1 << 3)
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#define OMAP1510_FPGA_PCR_48MHZ_CLK (1 << 2)
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#define OMAP1510_FPGA_PCR_4MHZ_CLK (1 << 1)
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2012-03-08 06:13:49 +01:00
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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2009-03-04 04:28:35 +01:00
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#define OMAP1510_FPGA_PCR_RSRVD_BIT0 (1 << 0)
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#define OMAP1510_FPGA_HID_SCLK (1<<0)
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#define OMAP1510_FPGA_HID_MOSI (1<<1)
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#define OMAP1510_FPGA_HID_nSS (1<<2)
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2012-03-08 06:13:49 +01:00
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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2009-03-04 04:28:35 +01:00
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#define OMAP1510_FPGA_HID_nHSUS (1<<3)
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#define OMAP1510_FPGA_HID_MISO (1<<4)
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#define OMAP1510_FPGA_HID_ATN (1<<5)
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#define OMAP1510_FPGA_HID_rsrvd (1<<6)
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2012-03-08 06:13:49 +01:00
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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2009-03-04 04:28:35 +01:00
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#define OMAP1510_FPGA_HID_RESETn (1<<7)
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#define OMAP1510_INT_FPGA (IH_GPIO_BASE + 13)
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#define OMAP1510_IH_FPGA_BASE IH_BOARD_BASE
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#define OMAP1510_INT_FPGA_ATN (OMAP1510_IH_FPGA_BASE + 0)
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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2009-03-04 04:28:35 +01:00
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#define OMAP1510_INT_FPGA_ACK (OMAP1510_IH_FPGA_BASE + 1)
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#define OMAP1510_INT_FPGA2 (OMAP1510_IH_FPGA_BASE + 2)
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#define OMAP1510_INT_FPGA3 (OMAP1510_IH_FPGA_BASE + 3)
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#define OMAP1510_INT_FPGA4 (OMAP1510_IH_FPGA_BASE + 4)
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define OMAP1510_INT_FPGA5 (OMAP1510_IH_FPGA_BASE + 5)
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#define OMAP1510_INT_FPGA6 (OMAP1510_IH_FPGA_BASE + 6)
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#define OMAP1510_INT_FPGA7 (OMAP1510_IH_FPGA_BASE + 7)
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#define OMAP1510_INT_FPGA8 (OMAP1510_IH_FPGA_BASE + 8)
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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2009-03-04 04:28:35 +01:00
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#define OMAP1510_INT_FPGA9 (OMAP1510_IH_FPGA_BASE + 9)
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#define OMAP1510_INT_FPGA10 (OMAP1510_IH_FPGA_BASE + 10)
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#define OMAP1510_INT_FPGA11 (OMAP1510_IH_FPGA_BASE + 11)
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#define OMAP1510_INT_FPGA12 (OMAP1510_IH_FPGA_BASE + 12)
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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2009-03-04 04:28:35 +01:00
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#define OMAP1510_INT_ETHER (OMAP1510_IH_FPGA_BASE + 13)
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#define OMAP1510_INT_FPGAUART1 (OMAP1510_IH_FPGA_BASE + 14)
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#define OMAP1510_INT_FPGAUART2 (OMAP1510_IH_FPGA_BASE + 15)
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#define OMAP1510_INT_FPGA_TS (OMAP1510_IH_FPGA_BASE + 16)
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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2009-03-04 04:28:35 +01:00
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#define OMAP1510_INT_FPGA17 (OMAP1510_IH_FPGA_BASE + 17)
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#define OMAP1510_INT_FPGA_CAM (OMAP1510_IH_FPGA_BASE + 18)
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#define OMAP1510_INT_FPGA_RTC_A (OMAP1510_IH_FPGA_BASE + 19)
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#define OMAP1510_INT_FPGA_RTC_B (OMAP1510_IH_FPGA_BASE + 20)
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2012-03-08 06:13:49 +01:00
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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2009-03-04 04:28:35 +01:00
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#define OMAP1510_INT_FPGA_CD (OMAP1510_IH_FPGA_BASE + 21)
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#define OMAP1510_INT_FPGA22 (OMAP1510_IH_FPGA_BASE + 22)
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#define OMAP1510_INT_FPGA23 (OMAP1510_IH_FPGA_BASE + 23)
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#endif
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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