2012-03-27 20:37:17 +02:00
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/****************************************************************************
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****************************************************************************
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***
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*** This header was automatically generated from a Linux kernel header
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*** of the same name, to make information necessary for userspace to
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*** call into the kernel available to libc. It contains only constants,
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*** structures, and macros generated from the original header, and thus,
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*** contains no copyrightable information.
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***
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*** To edit the content of this header, modify the corresponding
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*** source file (e.g. under external/kernel-headers/original/) then
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*** run bionic/libc/kernel/tools/update_all.py
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***
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*** Any manual change here will be lost the next time this script will
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*** be run. You've been warned!
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***
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****************************************************************************
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****************************************************************************/
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#ifndef _ASM_PCI_BRIDGE_H
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#define _ASM_PCI_BRIDGE_H
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#include <linux/types.h>
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#include <linux/pci.h>
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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2013-01-30 03:15:55 +01:00
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#include <asm/xtalk/xwidget.h>
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2012-03-27 20:37:17 +02:00
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#include <asm/sn/types.h>
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2013-01-30 03:15:55 +01:00
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#define IOPFNSHIFT 12
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2012-03-27 20:37:17 +02:00
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#define IOPGSIZE (1 << IOPFNSHIFT)
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define IOPG(x) ((x) >> IOPFNSHIFT)
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#define IOPGOFF(x) ((x) & (IOPGSIZE-1))
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2013-01-30 03:15:55 +01:00
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#define BRIDGE_ATE_RAM_SIZE 0x00000400
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2012-03-27 20:37:17 +02:00
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#define BRIDGE_CONFIG_BASE 0x20000
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define BRIDGE_CONFIG1_BASE 0x28000
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#define BRIDGE_CONFIG_END 0x30000
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#define BRIDGE_CONFIG_SLOT_SIZE 0x1000
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2013-01-30 03:15:55 +01:00
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#define BRIDGE_SSRAM_512K 0x00080000
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2012-03-27 20:37:17 +02:00
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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2013-01-30 03:15:55 +01:00
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#define BRIDGE_SSRAM_128K 0x00020000
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#define BRIDGE_SSRAM_64K 0x00010000
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#define BRIDGE_SSRAM_0K 0x00000000
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2012-03-27 20:37:17 +02:00
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#ifndef __ASSEMBLY__
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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typedef u32 bridgereg_t;
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typedef u64 bridge_ate_t;
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typedef volatile bridge_ate_t *bridge_ate_p;
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typedef volatile struct bridge_s {
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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widget_cfg_t b_widget;
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#define b_wid_id b_widget.w_id
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#define b_wid_stat b_widget.w_status
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#define b_wid_err_upper b_widget.w_err_upper_addr
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define b_wid_err_lower b_widget.w_err_lower_addr
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#define b_wid_control b_widget.w_control
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#define b_wid_req_timeout b_widget.w_req_timeout
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#define b_wid_int_upper b_widget.w_intdest_upper_addr
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define b_wid_int_lower b_widget.w_intdest_lower_addr
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#define b_wid_err_cmdword b_widget.w_err_cmd_word
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#define b_wid_llp b_widget.w_llp_cfg
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#define b_wid_tflush b_widget.w_tflush
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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bridgereg_t _pad_000058;
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bridgereg_t b_wid_aux_err;
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bridgereg_t _pad_000060;
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bridgereg_t b_wid_resp_upper;
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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bridgereg_t _pad_000068;
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bridgereg_t b_wid_resp_lower;
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bridgereg_t _pad_000070;
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bridgereg_t b_wid_tst_pin_ctrl;
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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bridgereg_t _pad_000078[2];
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bridgereg_t _pad_000080;
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bridgereg_t b_dir_map;
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bridgereg_t _pad_000088[2];
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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bridgereg_t _pad_000090;
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bridgereg_t b_ram_perr;
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bridgereg_t _pad_000098[2];
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bridgereg_t _pad_0000A0;
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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bridgereg_t b_arb;
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bridgereg_t _pad_0000A8[2];
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bridgereg_t _pad_0000B0;
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bridgereg_t b_nic;
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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bridgereg_t _pad_0000B8[2];
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bridgereg_t _pad_0000C0;
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bridgereg_t b_bus_timeout;
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#define b_pci_bus_timeout b_bus_timeout
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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bridgereg_t _pad_0000C8;
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bridgereg_t b_pci_cfg;
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bridgereg_t _pad_0000D0;
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bridgereg_t b_pci_err_upper;
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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bridgereg_t _pad_0000D8;
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bridgereg_t b_pci_err_lower;
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bridgereg_t _pad_0000E0[8];
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#define b_gio_err_lower b_pci_err_lower
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define b_gio_err_upper b_pci_err_upper
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bridgereg_t _pad_000100;
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bridgereg_t b_int_status;
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bridgereg_t _pad_000108;
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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bridgereg_t b_int_enable;
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bridgereg_t _pad_000110;
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bridgereg_t b_int_rst_stat;
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bridgereg_t _pad_000118;
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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bridgereg_t b_int_mode;
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bridgereg_t _pad_000120;
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bridgereg_t b_int_device;
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bridgereg_t _pad_000128;
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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bridgereg_t b_int_host_err;
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struct {
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bridgereg_t __pad;
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bridgereg_t addr;
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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} b_int_addr[8];
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bridgereg_t _pad_000170[36];
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struct {
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bridgereg_t __pad;
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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bridgereg_t reg;
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} b_device[8];
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struct {
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bridgereg_t __pad;
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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bridgereg_t reg;
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} b_wr_req_buf[8];
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struct {
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bridgereg_t __pad;
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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bridgereg_t reg;
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} b_rrb_map[2];
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2013-01-30 03:15:55 +01:00
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#define b_even_resp b_rrb_map[0].reg
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#define b_odd_resp b_rrb_map[1].reg
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2012-03-27 20:37:17 +02:00
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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bridgereg_t _pad_000290;
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bridgereg_t b_resp_status;
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bridgereg_t _pad_000298;
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bridgereg_t b_resp_clear;
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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bridgereg_t _pad_0002A0[24];
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char _pad_000300[0x10000 - 0x000300];
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union {
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bridge_ate_t wr;
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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struct {
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bridgereg_t _p_pad;
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bridgereg_t rd;
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} hi;
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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} b_int_ate_ram[128];
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char _pad_010400[0x11000 - 0x010400];
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struct {
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bridgereg_t _p_pad;
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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bridgereg_t rd;
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} b_int_ate_ram_lo[128];
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char _pad_011400[0x20000 - 0x011400];
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union {
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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u8 c[0x1000 / 1];
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u16 s[0x1000 / 2];
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u32 l[0x1000 / 4];
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u64 d[0x1000 / 8];
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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union {
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u8 c[0x100 / 1];
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u16 s[0x100 / 2];
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u32 l[0x100 / 4];
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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u64 d[0x100 / 8];
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} f[8];
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} b_type0_cfg_dev[8];
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union {
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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u8 c[0x1000 / 1];
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u16 s[0x1000 / 2];
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u32 l[0x1000 / 4];
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u64 d[0x1000 / 8];
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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} b_type1_cfg;
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char _pad_029000[0x007000];
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union {
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u8 c[8 / 1];
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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u16 s[8 / 2];
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u32 l[8 / 4];
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u64 d[8 / 8];
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} b_pci_iack;
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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u8 _pad_030007[0x04fff8];
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bridge_ate_t b_ext_ate_ram[0x10000];
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char _pad_100000[0x200000-0x100000];
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union {
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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u8 c[0x100000 / 1];
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u16 s[0x100000 / 2];
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u32 l[0x100000 / 4];
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u64 d[0x100000 / 8];
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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} b_devio_raw[10];
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#define b_devio(n) b_devio_raw[((n)<2)?(n*2):(n+2)]
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union {
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u8 c[0x400000 / 1];
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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u16 s[0x400000 / 2];
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u32 l[0x400000 / 4];
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u64 d[0x400000 / 8];
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} b_external_flash;
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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} bridge_t;
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typedef struct bridge_err_cmdword_s {
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union {
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u32 cmd_word;
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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struct {
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u32 didn:4,
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sidn:4,
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pactyp:4,
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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tnum:5,
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coh:1,
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ds:2,
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gbr:1,
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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vbpm:1,
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error:1,
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barr:1,
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rsvd:8;
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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} berr_st;
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} berr_un;
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} bridge_err_cmdword_t;
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#define berr_field berr_un.berr_st
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#endif
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#define BRIDGE_WID_ID WIDGET_ID
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#define BRIDGE_WID_STAT WIDGET_STATUS
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#define BRIDGE_WID_ERR_UPPER WIDGET_ERR_UPPER_ADDR
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define BRIDGE_WID_ERR_LOWER WIDGET_ERR_LOWER_ADDR
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#define BRIDGE_WID_CONTROL WIDGET_CONTROL
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#define BRIDGE_WID_REQ_TIMEOUT WIDGET_REQ_TIMEOUT
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#define BRIDGE_WID_INT_UPPER WIDGET_INTDEST_UPPER_ADDR
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define BRIDGE_WID_INT_LOWER WIDGET_INTDEST_LOWER_ADDR
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#define BRIDGE_WID_ERR_CMDWORD WIDGET_ERR_CMD_WORD
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#define BRIDGE_WID_LLP WIDGET_LLP_CFG
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#define BRIDGE_WID_TFLUSH WIDGET_TFLUSH
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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2013-01-30 03:15:55 +01:00
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#define BRIDGE_WID_AUX_ERR 0x00005C
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#define BRIDGE_WID_RESP_UPPER 0x000064
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#define BRIDGE_WID_RESP_LOWER 0x00006C
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#define BRIDGE_WID_TST_PIN_CTRL 0x000074
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2012-03-27 20:37:17 +02:00
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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2013-01-30 03:15:55 +01:00
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#define BRIDGE_DIR_MAP 0x000084
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#define BRIDGE_RAM_PERR 0x000094
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#define BRIDGE_ARB 0x0000A4
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#define BRIDGE_NIC 0x0000B4
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2012-03-27 20:37:17 +02:00
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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2013-01-30 03:15:55 +01:00
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#define BRIDGE_BUS_TIMEOUT 0x0000C4
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2012-03-27 20:37:17 +02:00
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#define BRIDGE_PCI_BUS_TIMEOUT BRIDGE_BUS_TIMEOUT
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2013-01-30 03:15:55 +01:00
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#define BRIDGE_PCI_CFG 0x0000CC
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#define BRIDGE_PCI_ERR_UPPER 0x0000D4
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2012-03-27 20:37:17 +02:00
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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2013-01-30 03:15:55 +01:00
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#define BRIDGE_PCI_ERR_LOWER 0x0000DC
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#define BRIDGE_INT_STATUS 0x000104
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#define BRIDGE_INT_ENABLE 0x00010C
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#define BRIDGE_INT_RST_STAT 0x000114
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2012-03-27 20:37:17 +02:00
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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2013-01-30 03:15:55 +01:00
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#define BRIDGE_INT_MODE 0x00011C
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#define BRIDGE_INT_DEVICE 0x000124
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#define BRIDGE_INT_HOST_ERR 0x00012C
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#define BRIDGE_INT_ADDR0 0x000134
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2012-03-27 20:37:17 +02:00
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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2013-01-30 03:15:55 +01:00
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#define BRIDGE_INT_ADDR_OFF 0x000008
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2012-03-27 20:37:17 +02:00
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#define BRIDGE_INT_ADDR(x) (BRIDGE_INT_ADDR0+(x)*BRIDGE_INT_ADDR_OFF)
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2013-01-30 03:15:55 +01:00
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#define BRIDGE_DEVICE0 0x000204
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#define BRIDGE_DEVICE_OFF 0x000008
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2012-03-27 20:37:17 +02:00
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define BRIDGE_DEVICE(x) (BRIDGE_DEVICE0+(x)*BRIDGE_DEVICE_OFF)
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2013-01-30 03:15:55 +01:00
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#define BRIDGE_WR_REQ_BUF0 0x000244
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#define BRIDGE_WR_REQ_BUF_OFF 0x000008
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2012-03-27 20:37:17 +02:00
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#define BRIDGE_WR_REQ_BUF(x) (BRIDGE_WR_REQ_BUF0+(x)*BRIDGE_WR_REQ_BUF_OFF)
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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2013-01-30 03:15:55 +01:00
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#define BRIDGE_EVEN_RESP 0x000284
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#define BRIDGE_ODD_RESP 0x00028C
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#define BRIDGE_RESP_STATUS 0x000294
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#define BRIDGE_RESP_CLEAR 0x00029C
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2012-03-27 20:37:17 +02:00
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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2013-01-30 03:15:55 +01:00
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#define BRIDGE_ATE_RAM 0x00010000
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#define BRIDGE_TYPE0_CFG_DEV0 0x00020000
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#define BRIDGE_TYPE0_CFG_SLOT_OFF 0x00001000
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#define BRIDGE_TYPE0_CFG_FUNC_OFF 0x00000100
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2012-03-27 20:37:17 +02:00
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define BRIDGE_TYPE0_CFG_DEV(s) (BRIDGE_TYPE0_CFG_DEV0+ (s)*BRIDGE_TYPE0_CFG_SLOT_OFF)
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#define BRIDGE_TYPE0_CFG_DEVF(s, f) (BRIDGE_TYPE0_CFG_DEV0+ (s)*BRIDGE_TYPE0_CFG_SLOT_OFF+ (f)*BRIDGE_TYPE0_CFG_FUNC_OFF)
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2013-01-30 03:15:55 +01:00
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#define BRIDGE_TYPE1_CFG 0x00028000
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#define BRIDGE_PCI_IACK 0x00030000
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2012-03-27 20:37:17 +02:00
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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2013-01-30 03:15:55 +01:00
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#define BRIDGE_EXT_SSRAM 0x00080000
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#define BRIDGE_DEV_CNT 8
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#define BRIDGE_DEVIO0 0x00200000
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#define BRIDGE_DEVIO1 0x00400000
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2012-03-27 20:37:17 +02:00
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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2013-01-30 03:15:55 +01:00
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#define BRIDGE_DEVIO2 0x00600000
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#define BRIDGE_DEVIO_OFF 0x00100000
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#define BRIDGE_DEVIO_2MB 0x00200000
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#define BRIDGE_DEVIO_1MB 0x00100000
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2012-03-27 20:37:17 +02:00
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define BRIDGE_DEVIO(x) ((x)<=1 ? BRIDGE_DEVIO0+(x)*BRIDGE_DEVIO_2MB : BRIDGE_DEVIO2+((x)-2)*BRIDGE_DEVIO_1MB)
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2013-01-30 03:15:55 +01:00
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#define BRIDGE_EXTERNAL_FLASH 0x00C00000
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2012-03-27 20:37:17 +02:00
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#define BRIDGE_WIDGET_PART_NUM 0xc002
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#define XBRIDGE_WIDGET_PART_NUM 0xd002
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define BRIDGE_WIDGET_MFGR_NUM 0x036
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#define XBRIDGE_WIDGET_MFGR_NUM 0x024
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#define BRIDGE_REV_A 0x1
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#define BRIDGE_REV_B 0x2
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define BRIDGE_REV_C 0x3
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#define BRIDGE_REV_D 0x4
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#define BRIDGE_STAT_LLP_REC_CNT (0xFFu << 24)
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#define BRIDGE_STAT_LLP_TX_CNT (0xFF << 16)
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define BRIDGE_STAT_FLASH_SELECT (0x1 << 6)
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#define BRIDGE_STAT_PCI_GIO_N (0x1 << 5)
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#define BRIDGE_STAT_PENDING (0x1F << 0)
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#define BRIDGE_CTRL_FLASH_WR_EN (0x1ul << 31)
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define BRIDGE_CTRL_EN_CLK50 (0x1 << 30)
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#define BRIDGE_CTRL_EN_CLK40 (0x1 << 29)
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#define BRIDGE_CTRL_EN_CLK33 (0x1 << 28)
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#define BRIDGE_CTRL_RST(n) ((n) << 24)
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define BRIDGE_CTRL_RST_MASK (BRIDGE_CTRL_RST(0xF))
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#define BRIDGE_CTRL_RST_PIN(x) (BRIDGE_CTRL_RST(0x1 << (x)))
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#define BRIDGE_CTRL_IO_SWAP (0x1 << 23)
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#define BRIDGE_CTRL_MEM_SWAP (0x1 << 22)
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define BRIDGE_CTRL_PAGE_SIZE (0x1 << 21)
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#define BRIDGE_CTRL_SS_PAR_BAD (0x1 << 20)
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#define BRIDGE_CTRL_SS_PAR_EN (0x1 << 19)
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#define BRIDGE_CTRL_SSRAM_SIZE(n) ((n) << 17)
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define BRIDGE_CTRL_SSRAM_SIZE_MASK (BRIDGE_CTRL_SSRAM_SIZE(0x3))
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#define BRIDGE_CTRL_SSRAM_512K (BRIDGE_CTRL_SSRAM_SIZE(0x3))
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#define BRIDGE_CTRL_SSRAM_128K (BRIDGE_CTRL_SSRAM_SIZE(0x2))
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#define BRIDGE_CTRL_SSRAM_64K (BRIDGE_CTRL_SSRAM_SIZE(0x1))
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define BRIDGE_CTRL_SSRAM_1K (BRIDGE_CTRL_SSRAM_SIZE(0x0))
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#define BRIDGE_CTRL_F_BAD_PKT (0x1 << 16)
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#define BRIDGE_CTRL_LLP_XBAR_CRD(n) ((n) << 12)
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#define BRIDGE_CTRL_LLP_XBAR_CRD_MASK (BRIDGE_CTRL_LLP_XBAR_CRD(0xf))
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define BRIDGE_CTRL_CLR_RLLP_CNT (0x1 << 11)
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#define BRIDGE_CTRL_CLR_TLLP_CNT (0x1 << 10)
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#define BRIDGE_CTRL_SYS_END (0x1 << 9)
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#define BRIDGE_CTRL_MAX_TRANS(n) ((n) << 4)
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define BRIDGE_CTRL_MAX_TRANS_MASK (BRIDGE_CTRL_MAX_TRANS(0x1f))
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#define BRIDGE_CTRL_WIDGET_ID(n) ((n) << 0)
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#define BRIDGE_CTRL_WIDGET_ID_MASK (BRIDGE_CTRL_WIDGET_ID(0xf))
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#define BRIDGE_RESP_ERRUPPR_DEVNUM_SHFT (20)
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define BRIDGE_RESP_ERRUPPR_DEVNUM_MASK (0x7 << BRIDGE_RESP_ERRUPPR_DEVNUM_SHFT)
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#define BRIDGE_RESP_ERRUPPR_BUFNUM_SHFT (16)
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#define BRIDGE_RESP_ERRUPPR_BUFNUM_MASK (0xF << BRIDGE_RESP_ERRUPPR_BUFNUM_SHFT)
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#define BRIDGE_RESP_ERRRUPPR_BUFMASK (0xFFFF)
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define BRIDGE_RESP_ERRUPPR_BUFNUM(x) (((x) & BRIDGE_RESP_ERRUPPR_BUFNUM_MASK) >> BRIDGE_RESP_ERRUPPR_BUFNUM_SHFT)
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#define BRIDGE_RESP_ERRUPPR_DEVICE(x) (((x) & BRIDGE_RESP_ERRUPPR_DEVNUM_MASK) >> BRIDGE_RESP_ERRUPPR_DEVNUM_SHFT)
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#define BRIDGE_DIRMAP_W_ID_SHFT 20
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#define BRIDGE_DIRMAP_W_ID (0xf << BRIDGE_DIRMAP_W_ID_SHFT)
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define BRIDGE_DIRMAP_RMF_64 (0x1 << 18)
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#define BRIDGE_DIRMAP_ADD512 (0x1 << 17)
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#define BRIDGE_DIRMAP_OFF (0x1ffff << 0)
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2013-01-30 03:15:55 +01:00
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#define BRIDGE_DIRMAP_OFF_ADDRSHFT (31)
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2012-03-27 20:37:17 +02:00
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define BRIDGE_ARB_REQ_WAIT_TICK(x) ((x) << 16)
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#define BRIDGE_ARB_REQ_WAIT_TICK_MASK BRIDGE_ARB_REQ_WAIT_TICK(0x3)
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#define BRIDGE_ARB_REQ_WAIT_EN(x) ((x) << 8)
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#define BRIDGE_ARB_REQ_WAIT_EN_MASK BRIDGE_ARB_REQ_WAIT_EN(0xff)
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define BRIDGE_ARB_FREEZE_GNT (1 << 6)
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#define BRIDGE_ARB_HPRI_RING_B2 (1 << 5)
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#define BRIDGE_ARB_HPRI_RING_B1 (1 << 4)
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#define BRIDGE_ARB_HPRI_RING_B0 (1 << 3)
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define BRIDGE_ARB_LPRI_RING_B2 (1 << 2)
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#define BRIDGE_ARB_LPRI_RING_B1 (1 << 1)
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#define BRIDGE_ARB_LPRI_RING_B0 (1 << 0)
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#define BRIDGE_BUS_PCI_RETRY_HLD(x) ((x) << 16)
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define BRIDGE_BUS_PCI_RETRY_HLD_MASK BRIDGE_BUS_PCI_RETRY_HLD(0x1f)
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#define BRIDGE_BUS_GIO_TIMEOUT (1 << 12)
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#define BRIDGE_BUS_PCI_RETRY_CNT(x) ((x) << 0)
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#define BRIDGE_BUS_PCI_RETRY_MASK BRIDGE_BUS_PCI_RETRY_CNT(0x3ff)
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define BRIDGE_ISR_MULTI_ERR (0x1u << 31)
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#define BRIDGE_ISR_PMU_ESIZE_FAULT (0x1 << 30)
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#define BRIDGE_ISR_UNEXP_RESP (0x1 << 29)
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#define BRIDGE_ISR_BAD_XRESP_PKT (0x1 << 28)
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define BRIDGE_ISR_BAD_XREQ_PKT (0x1 << 27)
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#define BRIDGE_ISR_RESP_XTLK_ERR (0x1 << 26)
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#define BRIDGE_ISR_REQ_XTLK_ERR (0x1 << 25)
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#define BRIDGE_ISR_INVLD_ADDR (0x1 << 24)
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define BRIDGE_ISR_UNSUPPORTED_XOP (0x1 << 23)
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#define BRIDGE_ISR_XREQ_FIFO_OFLOW (0x1 << 22)
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#define BRIDGE_ISR_LLP_REC_SNERR (0x1 << 21)
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#define BRIDGE_ISR_LLP_REC_CBERR (0x1 << 20)
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define BRIDGE_ISR_LLP_RCTY (0x1 << 19)
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#define BRIDGE_ISR_LLP_TX_RETRY (0x1 << 18)
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#define BRIDGE_ISR_LLP_TCTY (0x1 << 17)
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#define BRIDGE_ISR_SSRAM_PERR (0x1 << 16)
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define BRIDGE_ISR_PCI_ABORT (0x1 << 15)
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#define BRIDGE_ISR_PCI_PARITY (0x1 << 14)
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#define BRIDGE_ISR_PCI_SERR (0x1 << 13)
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#define BRIDGE_ISR_PCI_PERR (0x1 << 12)
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define BRIDGE_ISR_PCI_MST_TIMEOUT (0x1 << 11)
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#define BRIDGE_ISR_GIO_MST_TIMEOUT BRIDGE_ISR_PCI_MST_TIMEOUT
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#define BRIDGE_ISR_PCI_RETRY_CNT (0x1 << 10)
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#define BRIDGE_ISR_XREAD_REQ_TIMEOUT (0x1 << 9)
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define BRIDGE_ISR_GIO_B_ENBL_ERR (0x1 << 8)
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#define BRIDGE_ISR_INT_MSK (0xff << 0)
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#define BRIDGE_ISR_INT(x) (0x1 << (x))
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#define BRIDGE_ISR_LINK_ERROR (BRIDGE_ISR_LLP_REC_SNERR|BRIDGE_ISR_LLP_REC_CBERR| BRIDGE_ISR_LLP_RCTY|BRIDGE_ISR_LLP_TX_RETRY| BRIDGE_ISR_LLP_TCTY)
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define BRIDGE_ISR_PCIBUS_PIOERR (BRIDGE_ISR_PCI_MST_TIMEOUT|BRIDGE_ISR_PCI_ABORT)
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#define BRIDGE_ISR_PCIBUS_ERROR (BRIDGE_ISR_PCIBUS_PIOERR|BRIDGE_ISR_PCI_PERR| BRIDGE_ISR_PCI_SERR|BRIDGE_ISR_PCI_RETRY_CNT| BRIDGE_ISR_PCI_PARITY)
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#define BRIDGE_ISR_XTALK_ERROR (BRIDGE_ISR_XREAD_REQ_TIMEOUT|BRIDGE_ISR_XREQ_FIFO_OFLOW| BRIDGE_ISR_UNSUPPORTED_XOP|BRIDGE_ISR_INVLD_ADDR| BRIDGE_ISR_REQ_XTLK_ERR|BRIDGE_ISR_RESP_XTLK_ERR| BRIDGE_ISR_BAD_XREQ_PKT|BRIDGE_ISR_BAD_XRESP_PKT| BRIDGE_ISR_UNEXP_RESP)
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#define BRIDGE_ISR_ERRORS (BRIDGE_ISR_LINK_ERROR|BRIDGE_ISR_PCIBUS_ERROR| BRIDGE_ISR_XTALK_ERROR|BRIDGE_ISR_SSRAM_PERR| BRIDGE_ISR_PMU_ESIZE_FAULT)
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define BRIDGE_ISR_ERROR_FATAL ((BRIDGE_ISR_XTALK_ERROR & ~BRIDGE_ISR_XREAD_REQ_TIMEOUT)| BRIDGE_ISR_PCI_SERR|BRIDGE_ISR_PCI_PARITY )
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#define BRIDGE_ISR_ERROR_DUMP (BRIDGE_ISR_PCIBUS_ERROR|BRIDGE_ISR_PMU_ESIZE_FAULT| BRIDGE_ISR_XTALK_ERROR|BRIDGE_ISR_SSRAM_PERR)
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#define BRIDGE_IMR_UNEXP_RESP BRIDGE_ISR_UNEXP_RESP
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#define BRIDGE_IMR_PMU_ESIZE_FAULT BRIDGE_ISR_PMU_ESIZE_FAULT
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define BRIDGE_IMR_BAD_XRESP_PKT BRIDGE_ISR_BAD_XRESP_PKT
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#define BRIDGE_IMR_BAD_XREQ_PKT BRIDGE_ISR_BAD_XREQ_PKT
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#define BRIDGE_IMR_RESP_XTLK_ERR BRIDGE_ISR_RESP_XTLK_ERR
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#define BRIDGE_IMR_REQ_XTLK_ERR BRIDGE_ISR_REQ_XTLK_ERR
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define BRIDGE_IMR_INVLD_ADDR BRIDGE_ISR_INVLD_ADDR
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#define BRIDGE_IMR_UNSUPPORTED_XOP BRIDGE_ISR_UNSUPPORTED_XOP
|
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#define BRIDGE_IMR_XREQ_FIFO_OFLOW BRIDGE_ISR_XREQ_FIFO_OFLOW
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#define BRIDGE_IMR_LLP_REC_SNERR BRIDGE_ISR_LLP_REC_SNERR
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define BRIDGE_IMR_LLP_REC_CBERR BRIDGE_ISR_LLP_REC_CBERR
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#define BRIDGE_IMR_LLP_RCTY BRIDGE_ISR_LLP_RCTY
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#define BRIDGE_IMR_LLP_TX_RETRY BRIDGE_ISR_LLP_TX_RETRY
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#define BRIDGE_IMR_LLP_TCTY BRIDGE_ISR_LLP_TCTY
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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|
#define BRIDGE_IMR_SSRAM_PERR BRIDGE_ISR_SSRAM_PERR
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#define BRIDGE_IMR_PCI_ABORT BRIDGE_ISR_PCI_ABORT
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#define BRIDGE_IMR_PCI_PARITY BRIDGE_ISR_PCI_PARITY
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#define BRIDGE_IMR_PCI_SERR BRIDGE_ISR_PCI_SERR
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define BRIDGE_IMR_PCI_PERR BRIDGE_ISR_PCI_PERR
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#define BRIDGE_IMR_PCI_MST_TIMEOUT BRIDGE_ISR_PCI_MST_TIMEOUT
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#define BRIDGE_IMR_GIO_MST_TIMEOUT BRIDGE_ISR_GIO_MST_TIMEOUT
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#define BRIDGE_IMR_PCI_RETRY_CNT BRIDGE_ISR_PCI_RETRY_CNT
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define BRIDGE_IMR_XREAD_REQ_TIMEOUT BRIDGE_ISR_XREAD_REQ_TIMEOUT
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#define BRIDGE_IMR_GIO_B_ENBL_ERR BRIDGE_ISR_GIO_B_ENBL_ERR
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#define BRIDGE_IMR_INT_MSK BRIDGE_ISR_INT_MSK
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#define BRIDGE_IMR_INT(x) BRIDGE_ISR_INT(x)
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define BRIDGE_IRR_MULTI_CLR (0x1 << 6)
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#define BRIDGE_IRR_CRP_GRP_CLR (0x1 << 5)
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#define BRIDGE_IRR_RESP_BUF_GRP_CLR (0x1 << 4)
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#define BRIDGE_IRR_REQ_DSP_GRP_CLR (0x1 << 3)
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define BRIDGE_IRR_LLP_GRP_CLR (0x1 << 2)
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#define BRIDGE_IRR_SSRAM_GRP_CLR (0x1 << 1)
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#define BRIDGE_IRR_PCI_GRP_CLR (0x1 << 0)
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#define BRIDGE_IRR_GIO_GRP_CLR (0x1 << 0)
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define BRIDGE_IRR_ALL_CLR 0x7f
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#define BRIDGE_IRR_CRP_GRP (BRIDGE_ISR_UNEXP_RESP | BRIDGE_ISR_XREQ_FIFO_OFLOW)
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#define BRIDGE_IRR_RESP_BUF_GRP (BRIDGE_ISR_BAD_XRESP_PKT | BRIDGE_ISR_RESP_XTLK_ERR | BRIDGE_ISR_XREAD_REQ_TIMEOUT)
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#define BRIDGE_IRR_REQ_DSP_GRP (BRIDGE_ISR_UNSUPPORTED_XOP | BRIDGE_ISR_BAD_XREQ_PKT | BRIDGE_ISR_REQ_XTLK_ERR | BRIDGE_ISR_INVLD_ADDR)
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define BRIDGE_IRR_LLP_GRP (BRIDGE_ISR_LLP_REC_SNERR | BRIDGE_ISR_LLP_REC_CBERR | BRIDGE_ISR_LLP_RCTY | BRIDGE_ISR_LLP_TX_RETRY | BRIDGE_ISR_LLP_TCTY)
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#define BRIDGE_IRR_SSRAM_GRP (BRIDGE_ISR_SSRAM_PERR | BRIDGE_ISR_PMU_ESIZE_FAULT)
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#define BRIDGE_IRR_PCI_GRP (BRIDGE_ISR_PCI_ABORT | BRIDGE_ISR_PCI_PARITY | BRIDGE_ISR_PCI_SERR | BRIDGE_ISR_PCI_PERR | BRIDGE_ISR_PCI_MST_TIMEOUT | BRIDGE_ISR_PCI_RETRY_CNT)
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#define BRIDGE_IRR_GIO_GRP (BRIDGE_ISR_GIO_B_ENBL_ERR | BRIDGE_ISR_GIO_MST_TIMEOUT)
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define BRIDGE_INT_DEV_SHFT(n) ((n)*3)
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#define BRIDGE_INT_DEV_MASK(n) (0x7 << BRIDGE_INT_DEV_SHFT(n))
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#define BRIDGE_INT_DEV_SET(_dev, _line) (_dev << BRIDGE_INT_DEV_SHFT(_line))
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#define BRIDGE_INT_ADDR_HOST 0x0003FF00
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define BRIDGE_INT_ADDR_FLD 0x000000FF
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#define BRIDGE_TMO_PCI_RETRY_HLD_MASK 0x1f0000
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#define BRIDGE_TMO_GIO_TIMEOUT_MASK 0x001000
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#define BRIDGE_TMO_PCI_RETRY_CNT_MASK 0x0003ff
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define BRIDGE_TMO_PCI_RETRY_CNT_MAX 0x3ff
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#define BRIDGE_INT_ADDR_NASID_SHFT 8
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#define BRIDGE_INT_ADDR_DEST_IO (1 << 17)
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#define BRIDGE_INT_ADDR_DEST_MEM 0
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define BRIDGE_INT_ADDR_MASK (1 << 17)
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#define BRIDGE_DEV_ERR_LOCK_EN 0x10000000
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#define BRIDGE_DEV_PAGE_CHK_DIS 0x08000000
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#define BRIDGE_DEV_FORCE_PCI_PAR 0x04000000
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define BRIDGE_DEV_VIRTUAL_EN 0x02000000
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#define BRIDGE_DEV_PMU_WRGA_EN 0x01000000
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#define BRIDGE_DEV_DIR_WRGA_EN 0x00800000
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#define BRIDGE_DEV_DEV_SIZE 0x00400000
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define BRIDGE_DEV_RT 0x00200000
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#define BRIDGE_DEV_SWAP_PMU 0x00100000
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#define BRIDGE_DEV_SWAP_DIR 0x00080000
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#define BRIDGE_DEV_PREF 0x00040000
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define BRIDGE_DEV_PRECISE 0x00020000
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#define BRIDGE_DEV_COH 0x00010000
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#define BRIDGE_DEV_BARRIER 0x00008000
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#define BRIDGE_DEV_GBR 0x00004000
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define BRIDGE_DEV_DEV_SWAP 0x00002000
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#define BRIDGE_DEV_DEV_IO_MEM 0x00001000
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#define BRIDGE_DEV_OFF_MASK 0x00000fff
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#define BRIDGE_DEV_OFF_ADDR_SHFT 20
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define BRIDGE_DEV_PMU_BITS (BRIDGE_DEV_PMU_WRGA_EN | BRIDGE_DEV_SWAP_PMU)
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#define BRIDGE_DEV_D32_BITS (BRIDGE_DEV_DIR_WRGA_EN | BRIDGE_DEV_SWAP_DIR | BRIDGE_DEV_PREF | BRIDGE_DEV_PRECISE | BRIDGE_DEV_COH | BRIDGE_DEV_BARRIER)
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#define BRIDGE_DEV_D64_BITS (BRIDGE_DEV_DIR_WRGA_EN | BRIDGE_DEV_SWAP_DIR | BRIDGE_DEV_COH | BRIDGE_DEV_BARRIER)
|
2013-01-30 03:15:55 +01:00
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#define BRIDGE_ERRUPPR_DEVMASTER (0x1 << 20)
|
2012-03-27 20:37:17 +02:00
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
2013-01-30 03:15:55 +01:00
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#define BRIDGE_ERRUPPR_PCIVDEV (0x1 << 19)
|
2012-03-27 20:37:17 +02:00
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#define BRIDGE_ERRUPPR_DEVNUM_SHFT (16)
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#define BRIDGE_ERRUPPR_DEVNUM_MASK (0x7 << BRIDGE_ERRUPPR_DEVNUM_SHFT)
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#define BRIDGE_ERRUPPR_DEVICE(err) (((err) >> BRIDGE_ERRUPPR_DEVNUM_SHFT) & 0x7)
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define BRIDGE_ERRUPPR_ADDRMASK (0xFFFF)
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#define BRIDGE_INTMODE_CLR_PKT_EN(x) (0x1 << (x))
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#define BRIDGE_CREDIT 3
|
2013-01-30 03:15:55 +01:00
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#define BRIDGE_RRB_EN 0x8
|
2012-03-27 20:37:17 +02:00
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
2013-01-30 03:15:55 +01:00
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#define BRIDGE_RRB_DEV 0x7
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#define BRIDGE_RRB_VDEV 0x4
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#define BRIDGE_RRB_PDEV 0x3
|
2012-03-27 20:37:17 +02:00
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#define BRIDGE_RRB_VALID(r) (0x00010000<<(r))
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define BRIDGE_RRB_INUSE(r) (0x00000001<<(r))
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#define BRIDGE_RRB_CLEAR(r) (0x00000001<<(r))
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#define XBOX_BRIDGE_WID 8
|
2013-01-30 03:15:55 +01:00
|
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|
#define FLASH_PROM1_BASE 0xE00000
|
2012-03-27 20:37:17 +02:00
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
2013-01-30 03:15:55 +01:00
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#define XBOX_RPS_EXISTS 1 << 6
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#define XBOX_RPS_FAIL 1 << 4
|
2012-03-27 20:37:17 +02:00
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#define BRIDGE_PIO32_XTALK_ALIAS_BASE 0x000040000000L
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#define BRIDGE_PIO32_XTALK_ALIAS_LIMIT 0x00007FFFFFFFL
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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|
#define BRIDGE_PIO64_XTALK_ALIAS_BASE 0x000080000000L
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#define BRIDGE_PIO64_XTALK_ALIAS_LIMIT 0x0000BFFFFFFFL
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#define BRIDGE_PCIIO_XTALK_ALIAS_BASE 0x000100000000L
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#define BRIDGE_PCIIO_XTALK_ALIAS_LIMIT 0x0001FFFFFFFFL
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|
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
2013-01-30 03:15:55 +01:00
|
|
|
#define BRIDGE_MIN_PIO_ADDR_MEM 0x00000000
|
2012-03-27 20:37:17 +02:00
|
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|
#define BRIDGE_MAX_PIO_ADDR_MEM 0x3fffffff
|
2013-01-30 03:15:55 +01:00
|
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|
#define BRIDGE_MIN_PIO_ADDR_IO 0x00000000
|
2012-03-27 20:37:17 +02:00
|
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|
#define BRIDGE_MAX_PIO_ADDR_IO 0xffffffff
|
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|
|
|
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
|
|
|
|
#define BRIDGE_PCI_MEM32_BASE BRIDGE_PIO32_XTALK_ALIAS_BASE
|
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#define BRIDGE_PCI_MEM32_LIMIT BRIDGE_PIO32_XTALK_ALIAS_LIMIT
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#define BRIDGE_PCI_MEM64_BASE BRIDGE_PIO64_XTALK_ALIAS_BASE
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#define BRIDGE_PCI_MEM64_LIMIT BRIDGE_PIO64_XTALK_ALIAS_LIMIT
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|
|
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
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|
|
#define BRIDGE_PCI_IO_BASE BRIDGE_PCIIO_XTALK_ALIAS_BASE
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#define BRIDGE_PCI_IO_LIMIT BRIDGE_PCIIO_XTALK_ALIAS_LIMIT
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#define BRIDGE_LOCAL_BASE 0
|
|
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|
|
#define BRIDGE_DMA_MAPPED_BASE 0x40000000
|
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|
|
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
2013-01-30 03:15:55 +01:00
|
|
|
#define BRIDGE_DMA_MAPPED_SIZE 0x40000000
|
2012-03-27 20:37:17 +02:00
|
|
|
#define BRIDGE_DMA_DIRECT_BASE 0x80000000
|
2013-01-30 03:15:55 +01:00
|
|
|
#define BRIDGE_DMA_DIRECT_SIZE 0x80000000
|
2012-03-27 20:37:17 +02:00
|
|
|
#define PCI32_LOCAL_BASE BRIDGE_LOCAL_BASE
|
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|
|
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
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|
#define PCI32_MAPPED_BASE BRIDGE_DMA_MAPPED_BASE
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#define PCI32_DIRECT_BASE BRIDGE_DMA_DIRECT_BASE
|
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|
|
#define IS_PCI32_LOCAL(x) ((ulong_t)(x) < PCI32_MAPPED_BASE)
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|
#define IS_PCI32_MAPPED(x) ((ulong_t)(x) < PCI32_DIRECT_BASE && (ulong_t)(x) >= PCI32_MAPPED_BASE)
|
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|
|
|
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
|
|
|
|
#define IS_PCI32_DIRECT(x) ((ulong_t)(x) >= PCI32_MAPPED_BASE)
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|
|
#define IS_PCI64(x) ((ulong_t)(x) >= PCI64_BASE)
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|
|
#define BRIDGE_GIO_MEM32_BASE BRIDGE_PIO32_XTALK_ALIAS_BASE
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|
|
#define BRIDGE_GIO_MEM32_LIMIT BRIDGE_PIO32_XTALK_ALIAS_LIMIT
|
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|
|
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
|
|
|
|
#define GIO_LOCAL_BASE BRIDGE_LOCAL_BASE
|
|
|
|
|
#define GIO_MAPPED_BASE BRIDGE_DMA_MAPPED_BASE
|
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|
|
#define GIO_DIRECT_BASE BRIDGE_DMA_DIRECT_BASE
|
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|
#define IS_GIO_LOCAL(x) ((ulong_t)(x) < GIO_MAPPED_BASE)
|
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|
|
|
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
|
|
|
|
#define IS_GIO_MAPPED(x) ((ulong_t)(x) < GIO_DIRECT_BASE && (ulong_t)(x) >= GIO_MAPPED_BASE)
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|
#define IS_GIO_DIRECT(x) ((ulong_t)(x) >= GIO_MAPPED_BASE)
|
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|
|
|
#define BRIDGE_DIRECT_32_SEG_SIZE BRIDGE_DMA_DIRECT_SIZE
|
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|
|
|
#define BRIDGE_DIRECT_32_TO_XTALK(dir_off,adr) ((dir_off) * BRIDGE_DIRECT_32_SEG_SIZE + ((adr) & (BRIDGE_DIRECT_32_SEG_SIZE - 1)) + PHYS_RAMBASE)
|
|
|
|
|
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
|
|
|
|
#define PCI64_ATTR_TARG_MASK 0xf000000000000000
|
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|
|
|
#define PCI64_ATTR_TARG_SHFT 60
|
|
|
|
|
#define PCI64_ATTR_PREF 0x0800000000000000
|
|
|
|
|
#define PCI64_ATTR_PREC 0x0400000000000000
|
|
|
|
|
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
|
|
|
|
#define PCI64_ATTR_VIRTUAL 0x0200000000000000
|
|
|
|
|
#define PCI64_ATTR_BAR 0x0100000000000000
|
|
|
|
|
#define PCI64_ATTR_RMF_MASK 0x00ff000000000000
|
|
|
|
|
#define PCI64_ATTR_RMF_SHFT 48
|
|
|
|
|
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
|
|
|
|
#ifndef __ASSEMBLY__
|
|
|
|
|
typedef union ate_u {
|
|
|
|
|
u64 ent;
|
|
|
|
|
struct ate_s {
|
|
|
|
|
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
|
|
|
|
u64 rmf:16;
|
|
|
|
|
u64 addr:36;
|
|
|
|
|
u64 targ:4;
|
|
|
|
|
u64 reserved:3;
|
|
|
|
|
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
|
|
|
|
u64 barrier:1;
|
|
|
|
|
u64 prefetch:1;
|
|
|
|
|
u64 precise:1;
|
|
|
|
|
u64 coherent:1;
|
|
|
|
|
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
|
|
|
|
u64 valid:1;
|
|
|
|
|
} field;
|
|
|
|
|
} ate_t;
|
|
|
|
|
#endif
|
|
|
|
|
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
|
|
|
|
#define ATE_V 0x01
|
|
|
|
|
#define ATE_CO 0x02
|
|
|
|
|
#define ATE_PREC 0x04
|
|
|
|
|
#define ATE_PREF 0x08
|
|
|
|
|
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
|
|
|
|
#define ATE_BAR 0x10
|
|
|
|
|
#define ATE_PFNSHIFT 12
|
|
|
|
|
#define ATE_TIDSHIFT 8
|
|
|
|
|
#define ATE_RMFSHIFT 48
|
|
|
|
|
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
|
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#define mkate(xaddr, xid, attr) ((xaddr) & 0x0000fffffffff000ULL) | ((xid)<<ATE_TIDSHIFT) | (attr)
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#define BRIDGE_INTERNAL_ATES 128
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struct bridge_controller {
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struct pci_controller pc;
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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struct resource mem;
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struct resource io;
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bridge_t *base;
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nasid_t nasid;
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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unsigned int widget_id;
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unsigned int irq_cpu;
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dma64_addr_t baddr;
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unsigned int pci_int[8];
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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};
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#define BRIDGE_CONTROLLER(bus) ((struct bridge_controller *)((bus)->sysdata))
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#endif
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