2014-07-10 00:33:25 +02:00
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/****************************************************************************
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****************************************************************************
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***
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*** This header was automatically generated from a Linux kernel header
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*** of the same name, to make information necessary for userspace to
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*** call into the kernel available to libc. It contains only constants,
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*** structures, and macros generated from the original header, and thus,
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*** contains no copyrightable information.
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***
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*** To edit the content of this header, modify the corresponding
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*** source file (e.g. under external/kernel-headers/original/) then
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*** run bionic/libc/kernel/tools/update_all.py
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***
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*** Any manual change here will be lost the next time this script will
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*** be run. You've been warned!
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***
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****************************************************************************
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****************************************************************************/
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#ifndef __MSM_DRM_H__
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#define __MSM_DRM_H__
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#include <stddef.h>
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#include <drm/drm.h>
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define MSM_PIPE_NONE 0x00
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#define MSM_PIPE_2D0 0x01
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#define MSM_PIPE_2D1 0x02
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#define MSM_PIPE_3D0 0x10
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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struct drm_msm_timespec {
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int64_t tv_sec;
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int64_t tv_nsec;
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};
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define MSM_PARAM_GPU_ID 0x01
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#define MSM_PARAM_GMEM_SIZE 0x02
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2014-09-04 04:56:49 +02:00
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#define MSM_PARAM_CHIP_ID 0x03
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2014-07-10 00:33:25 +02:00
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struct drm_msm_param {
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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2014-09-04 04:56:49 +02:00
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uint32_t pipe;
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2014-07-10 00:33:25 +02:00
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uint32_t param;
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uint64_t value;
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};
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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2014-09-04 04:56:49 +02:00
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#define MSM_BO_SCANOUT 0x00000001
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2014-07-10 00:33:25 +02:00
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#define MSM_BO_GPU_READONLY 0x00000002
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#define MSM_BO_CACHE_MASK 0x000f0000
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#define MSM_BO_CACHED 0x00010000
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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2014-09-04 04:56:49 +02:00
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#define MSM_BO_WC 0x00020000
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2014-07-10 00:33:25 +02:00
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#define MSM_BO_UNCACHED 0x00040000
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2014-09-04 04:56:49 +02:00
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#define MSM_BO_FLAGS (MSM_BO_SCANOUT | MSM_BO_GPU_READONLY | MSM_BO_CACHED | MSM_BO_WC | MSM_BO_UNCACHED)
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2014-07-10 00:33:25 +02:00
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struct drm_msm_gem_new {
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2014-09-04 04:56:49 +02:00
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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2014-07-10 00:33:25 +02:00
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uint64_t size;
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uint32_t flags;
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uint32_t handle;
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};
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2014-09-04 04:56:49 +02:00
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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2014-07-10 00:33:25 +02:00
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struct drm_msm_gem_info {
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uint32_t handle;
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uint32_t pad;
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uint64_t offset;
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2014-09-04 04:56:49 +02:00
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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2014-07-10 00:33:25 +02:00
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};
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#define MSM_PREP_READ 0x01
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#define MSM_PREP_WRITE 0x02
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#define MSM_PREP_NOSYNC 0x04
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define MSM_PREP_FLAGS (MSM_PREP_READ | MSM_PREP_WRITE | MSM_PREP_NOSYNC)
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struct drm_msm_gem_cpu_prep {
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uint32_t handle;
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uint32_t op;
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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2014-07-10 00:33:25 +02:00
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struct drm_msm_timespec timeout;
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};
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struct drm_msm_gem_cpu_fini {
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uint32_t handle;
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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2014-07-10 00:33:25 +02:00
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};
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struct drm_msm_gem_submit_reloc {
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uint32_t submit_offset;
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uint32_t or;
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2014-09-04 04:56:49 +02:00
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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2014-07-10 00:33:25 +02:00
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int32_t shift;
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uint32_t reloc_idx;
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uint64_t reloc_offset;
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};
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2014-09-04 04:56:49 +02:00
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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2014-07-10 00:33:25 +02:00
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#define MSM_SUBMIT_CMD_BUF 0x0001
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#define MSM_SUBMIT_CMD_IB_TARGET_BUF 0x0002
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#define MSM_SUBMIT_CMD_CTX_RESTORE_BUF 0x0003
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struct drm_msm_gem_submit_cmd {
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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2014-07-10 00:33:25 +02:00
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uint32_t type;
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uint32_t submit_idx;
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uint32_t submit_offset;
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uint32_t size;
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2014-09-04 04:56:49 +02:00
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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2014-07-10 00:33:25 +02:00
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uint32_t pad;
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uint32_t nr_relocs;
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uint64_t __user relocs;
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};
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2014-09-04 04:56:49 +02:00
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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2014-07-10 00:33:25 +02:00
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#define MSM_SUBMIT_BO_READ 0x0001
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#define MSM_SUBMIT_BO_WRITE 0x0002
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#define MSM_SUBMIT_BO_FLAGS (MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE)
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2014-07-10 00:33:25 +02:00
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struct drm_msm_gem_submit_bo {
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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uint32_t flags;
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uint32_t handle;
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uint64_t presumed;
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};
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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struct drm_msm_gem_submit {
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uint32_t pipe;
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uint32_t fence;
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uint32_t nr_bos;
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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uint32_t nr_cmds;
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uint64_t __user bos;
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uint64_t __user cmds;
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};
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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struct drm_msm_wait_fence {
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uint32_t fence;
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uint32_t pad;
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struct drm_msm_timespec timeout;
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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};
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#define DRM_MSM_GET_PARAM 0x00
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#define DRM_MSM_GEM_NEW 0x02
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#define DRM_MSM_GEM_INFO 0x03
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define DRM_MSM_GEM_CPU_PREP 0x04
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#define DRM_MSM_GEM_CPU_FINI 0x05
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#define DRM_MSM_GEM_SUBMIT 0x06
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#define DRM_MSM_WAIT_FENCE 0x07
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define DRM_MSM_NUM_IOCTLS 0x08
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#define DRM_IOCTL_MSM_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GET_PARAM, struct drm_msm_param)
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#define DRM_IOCTL_MSM_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_NEW, struct drm_msm_gem_new)
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#define DRM_IOCTL_MSM_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_INFO, struct drm_msm_gem_info)
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define DRM_IOCTL_MSM_GEM_CPU_PREP DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_PREP, struct drm_msm_gem_cpu_prep)
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#define DRM_IOCTL_MSM_GEM_CPU_FINI DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_FINI, struct drm_msm_gem_cpu_fini)
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#define DRM_IOCTL_MSM_GEM_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_SUBMIT, struct drm_msm_gem_submit)
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#define DRM_IOCTL_MSM_WAIT_FENCE DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_WAIT_FENCE, struct drm_msm_wait_fence)
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#endif
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