324 lines
8.1 KiB
ArmAsm
324 lines
8.1 KiB
ArmAsm
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/*
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* Copyright (c) 2009
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* MIPS Technologies, Inc., California.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the MIPS Technologies, Inc., nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE MIPS TECHNOLOGIES, INC. ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE MIPS TECHNOLOGIES, INC. BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/************************************************************************
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*
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* memset.S, version "64h" with 1 cache line horizon for "pref 30" and 14 nops
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* Version: "043009"
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*
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************************************************************************/
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/************************************************************************
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* Include files
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************************************************************************/
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#include "machine/asm.h"
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/*
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* This routine could be optimized for MIPS64. The current code only
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* uses MIPS32 instructions.
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*/
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#if defined(__MIPSEB__)
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# define SWHI swl /* high part is left in big-endian */
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# define SWLO swr /* low part is right in big-endian */
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#endif
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#if defined(__MIPSEL__)
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# define SWHI swr /* high part is right in little-endian */
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# define SWLO swl /* low part is left in little-endian */
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#endif
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#if !(defined(XGPROF) || defined(XPROF))
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#undef SETUP_GP
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#define SETUP_GP
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#endif
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#ifdef NDEBUG
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#define DBG #
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#else
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#define DBG
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#endif
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/*
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* void _memset16(uint16_t* dst, uint16_t value, size_t size);
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*/
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LEAF(_memset16,0)
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.set noreorder
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DBG /* Check parameters */
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DBG andi t0,a0,1 # a0 must be halfword aligned
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DBG tne t0,zero
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DBG andi t2,a2,1 # a2 must be even
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DBG tne t2,zero
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#ifdef FIXARGS
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# ensure count is even
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#if (__mips==32) && (__mips_isa_rev>=2)
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ins a2,zero,0,1
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#else
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ori a2,1
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xori a2,1
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#endif
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#endif
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#if (__mips==32) && (__mips_isa_rev>=2)
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ins a1,a1,16,16
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#else
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andi a1,0xffff
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sll t3,a1,16
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or a1,t3
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#endif
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beqz a2,.Ldone
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andi t1,a0,2
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beqz t1,.Lalignok
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addu t0,a0,a2 # t0 is the "past the end" address
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sh a1,0(a0) # store one halfword to get aligned
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addu a0,2
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subu a2,2
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.Lalignok:
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slti t1,a2,4 # .Laligned for 4 or more bytes
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beqz t1,.Laligned
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sne t1,a2,2 # one more halfword?
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bnez t1,.Ldone
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nop
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sh a1,0(a0)
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.Ldone:
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j ra
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nop
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.set reorder
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END(_memset16)
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/*
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* void _memset32(uint32_t* dst, uint32_t value, size_t size);
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*/
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LEAF(_memset32,0)
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.set noreorder
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DBG /* Check parameters */
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DBG andi t0,a0,3 # a0 must be word aligned
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DBG tne t0,zero
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DBG andi t2,a2,3 # a2 must be a multiple of 4 bytes
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DBG tne t2,zero
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#ifdef FIXARGS
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# ensure count is a multiple of 4
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#if (__mips==32) && (__mips_isa_rev>=2)
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ins $a2,$0,0,2
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#else
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ori a2,3
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xori a2,3
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#endif
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#endif
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bnez a2,.Laligned # any work to do?
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addu t0,a0,a2 # t0 is the "past the end" address
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j ra
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nop
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.set reorder
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END(_memset32)
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LEAF(memset,0)
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.set noreorder
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.set noat
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addu t0,a0,a2 # t0 is the "past the end" address
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slti AT,a2,4 # is a2 less than 4?
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bne AT,zero,.Llast4 # if yes, go to last4
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move v0,a0 # memset returns the dst pointer
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beq a1,zero,.Lset0
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subu v1,zero,a0
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# smear byte into 32 bit word
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#if (__mips==32) && (__mips_isa_rev>=2)
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ins a1, a1, 8, 8 # Replicate fill byte into half-word.
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ins a1, a1, 16, 16 # Replicate fill byte into word.
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#else
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and a1,0xff
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sll AT,a1,8
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or a1,AT
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sll AT,a1,16
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or a1,AT
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#endif
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.Lset0:
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andi v1,v1,0x3 # word-unaligned address?
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beq v1,zero,.Laligned # v1 is the unalignment count
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subu a2,a2,v1
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SWHI a1,0(a0)
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addu a0,a0,v1
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# Here we have the "word-aligned" a0 (until the "last4")
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.Laligned:
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andi t8,a2,0x3f # any 64-byte chunks?
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# t8 is the byte count past 64-byte chunks
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beq a2,t8,.Lchk8w # when a2==t8, no 64-byte chunks
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# There will be at most 1 32-byte chunk then
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subu a3,a2,t8 # subtract from a2 the reminder
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# Here a3 counts bytes in 16w chunks
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addu a3,a0,a3 # Now a3 is the final dst after 64-byte chunks
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# Find out, if there are any 64-byte chunks after which will be still at least
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# 96 bytes left. The value "96" is calculated as needed buffer for
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# "pref 30,64(a0)" prefetch, which can be used as "pref 30,0(a0)" after
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# incrementing "a0" by 64.
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# For "a2" below 160 there will be no such "pref 30 safe" 64-byte chunk.
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#
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sltiu v1,a2,160
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bgtz v1,.Lloop16w_nopref30 # skip "pref 30,0(a0)"
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subu t7,a2,96 # subtract "pref 30 unsafe" region
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# below we have at least 1 64-byte chunk which is "pref 30 safe"
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andi t6,t7,0x3f # t6 is past "64-byte safe chunks" reminder
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subu t5,t7,t6 # subtract from t7 the reminder
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# Here t5 counts bytes in 16w "safe" chunks
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addu t4,a0,t5 # Now t4 is the dst after 64-byte "safe" chunks
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# Don't use "pref 30,0(a0)" for a0 in a "middle" of a cache line
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# pref 30,0(a0)
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# Here we are in the region, where it is safe to use "pref 30,64(a0)"
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.Lloop16w:
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addiu a0,a0,64
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pref 30,-32(a0) # continue setting up the dest, addr 64-32
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sw a1,-64(a0)
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sw a1,-60(a0)
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sw a1,-56(a0)
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sw a1,-52(a0)
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sw a1,-48(a0)
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sw a1,-44(a0)
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sw a1,-40(a0)
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sw a1,-36(a0)
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nop
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nop # the extra nop instructions help to balance
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nop # cycles needed for "store" + "fill" + "evict"
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nop # For 64byte store there are needed 8 fill
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nop # and 8 evict cycles, i.e. at least 32 instr.
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nop
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nop
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pref 30,0(a0) # continue setting up the dest, addr 64-0
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sw a1,-32(a0)
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sw a1,-28(a0)
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sw a1,-24(a0)
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sw a1,-20(a0)
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sw a1,-16(a0)
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sw a1,-12(a0)
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sw a1,-8(a0)
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sw a1,-4(a0)
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nop
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nop
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nop
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nop # NOTE: adding 14 nop-s instead of 12 nop-s
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nop # gives better results for "fast" memory
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nop
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bne a0,t4,.Lloop16w
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nop
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beq a0,a3,.Lchk8w # maybe no more 64-byte chunks?
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nop # this "delayed slot" is useless ...
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.Lloop16w_nopref30: # there could be up to 3 "64-byte nopref30" chunks
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addiu a0,a0,64
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sw a1,-64(a0)
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sw a1,-60(a0)
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sw a1,-56(a0)
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sw a1,-52(a0)
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sw a1,-48(a0)
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sw a1,-44(a0)
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sw a1,-40(a0)
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sw a1,-36(a0)
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sw a1,-32(a0)
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sw a1,-28(a0)
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sw a1,-24(a0)
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sw a1,-20(a0)
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sw a1,-16(a0)
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sw a1,-12(a0)
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sw a1,-8(a0)
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bne a0,a3,.Lloop16w_nopref30
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sw a1,-4(a0)
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.Lchk8w: # t8 here is the byte count past 64-byte chunks
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andi t7,t8,0x1f # is there a 32-byte chunk?
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# the t7 is the reminder count past 32-bytes
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beq t8,t7,.Lchk1w # when t8==t7, no 32-byte chunk
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move a2,t7
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sw a1,0(a0)
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sw a1,4(a0)
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sw a1,8(a0)
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sw a1,12(a0)
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sw a1,16(a0)
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sw a1,20(a0)
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sw a1,24(a0)
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sw a1,28(a0)
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addiu a0,a0,32
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.Lchk1w:
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andi t8,a2,0x3 # now t8 is the reminder past 1w chunks
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beq a2,t8,.Llast4aligned
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subu a3,a2,t8 # a3 is the count of bytes in 1w chunks
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addu a3,a0,a3 # now a3 is the dst address past the 1w chunks
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# copying in words (4-byte chunks)
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.LwordCopy_loop:
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addiu a0,a0,4
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bne a0,a3,.LwordCopy_loop
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sw a1,-4(a0)
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# store last 0-3 bytes
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# this will repeat the last store if the memset finishes on a word boundary
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.Llast4aligned:
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j ra
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SWLO a1,-1(t0)
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.Llast4:
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beq a0,t0,.Llast4e
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.Llast4l:
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addiu a0,a0,1
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bne a0,t0,.Llast4l
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sb a1,-1(a0)
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.Llast4e:
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j ra
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nop
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.set at
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.set reorder
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END(memset)
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/************************************************************************
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* Implementation : Static functions
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************************************************************************/
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