562 lines
11 KiB
C
562 lines
11 KiB
C
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/****************************************************************************
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****************************************************************************
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***
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*** This header was automatically generated from a Linux kernel header
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*** of the same name, to make information necessary for userspace to
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*** call into the kernel available to libc. It contains only constants,
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*** structures, and macros generated from the original header, and thus,
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*** contains no copyrightable information.
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***
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****************************************************************************
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****************************************************************************/
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#ifndef _LINUX_SPI_CPCAP_H
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#define _LINUX_SPI_CPCAP_H
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#include <linux/ioctl.h>
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#define CPCAP_DEV_NAME "cpcap"
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#define CPCAP_NUM_REG_CPCAP (CPCAP_REG_END - CPCAP_REG_START + 1)
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#define CPCAP_IRQ_INT1_INDEX 0
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#define CPCAP_IRQ_INT2_INDEX 16
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#define CPCAP_IRQ_INT3_INDEX 32
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#define CPCAP_IRQ_INT4_INDEX 48
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#define CPCAP_IRQ_INT5_INDEX 64
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#define CPCAP_WHISPER_MODE_PU 0x00000001
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#define CPCAP_WHISPER_ENABLE_UART 0x00000002
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#define CPCAP_WHISPER_ACCY_MASK 0xF8000000
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#define CPCAP_WHISPER_ACCY_SHFT 27
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#define CPCAP_WHISPER_ID_SIZE 16
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enum cpcap_regulator_id {
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CPCAP_SW2,
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CPCAP_SW4,
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CPCAP_SW5,
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CPCAP_VCAM,
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CPCAP_VCSI,
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CPCAP_VDAC,
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CPCAP_VDIG,
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CPCAP_VFUSE,
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CPCAP_VHVIO,
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CPCAP_VSDIO,
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CPCAP_VPLL,
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CPCAP_VRF1,
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CPCAP_VRF2,
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CPCAP_VRFREF,
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CPCAP_VWLAN1,
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CPCAP_VWLAN2,
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CPCAP_VSIM,
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CPCAP_VSIMCARD,
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CPCAP_VVIB,
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CPCAP_VUSB,
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CPCAP_VAUDIO,
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CPCAP_NUM_REGULATORS
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};
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enum cpcap_reg {
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CPCAP_REG_START,
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CPCAP_REG_INT1 = CPCAP_REG_START,
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CPCAP_REG_INT2,
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CPCAP_REG_INT3,
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CPCAP_REG_INT4,
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CPCAP_REG_INTM1,
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CPCAP_REG_INTM2,
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CPCAP_REG_INTM3,
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CPCAP_REG_INTM4,
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CPCAP_REG_INTS1,
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CPCAP_REG_INTS2,
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CPCAP_REG_INTS3,
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CPCAP_REG_INTS4,
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CPCAP_REG_ASSIGN1,
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CPCAP_REG_ASSIGN2,
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CPCAP_REG_ASSIGN3,
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CPCAP_REG_ASSIGN4,
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CPCAP_REG_ASSIGN5,
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CPCAP_REG_ASSIGN6,
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CPCAP_REG_VERSC1,
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CPCAP_REG_VERSC2,
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CPCAP_REG_MI1,
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CPCAP_REG_MIM1,
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CPCAP_REG_MI2,
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CPCAP_REG_MIM2,
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CPCAP_REG_UCC1,
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CPCAP_REG_UCC2,
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CPCAP_REG_PC1,
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CPCAP_REG_PC2,
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CPCAP_REG_BPEOL,
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CPCAP_REG_PGC,
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CPCAP_REG_MT1,
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CPCAP_REG_MT2,
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CPCAP_REG_MT3,
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CPCAP_REG_PF,
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CPCAP_REG_SCC,
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CPCAP_REG_SW1,
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CPCAP_REG_SW2,
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CPCAP_REG_UCTM,
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CPCAP_REG_TOD1,
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CPCAP_REG_TOD2,
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CPCAP_REG_TODA1,
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CPCAP_REG_TODA2,
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CPCAP_REG_DAY,
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CPCAP_REG_DAYA,
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CPCAP_REG_VAL1,
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CPCAP_REG_VAL2,
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CPCAP_REG_SDVSPLL,
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CPCAP_REG_SI2CC1,
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CPCAP_REG_Si2CC2,
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CPCAP_REG_S1C1,
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CPCAP_REG_S1C2,
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CPCAP_REG_S2C1,
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CPCAP_REG_S2C2,
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CPCAP_REG_S3C,
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CPCAP_REG_S4C1,
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CPCAP_REG_S4C2,
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CPCAP_REG_S5C,
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CPCAP_REG_S6C,
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CPCAP_REG_VCAMC,
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CPCAP_REG_VCSIC,
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CPCAP_REG_VDACC,
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CPCAP_REG_VDIGC,
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CPCAP_REG_VFUSEC,
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CPCAP_REG_VHVIOC,
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CPCAP_REG_VSDIOC,
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CPCAP_REG_VPLLC,
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CPCAP_REG_VRF1C,
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CPCAP_REG_VRF2C,
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CPCAP_REG_VRFREFC,
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CPCAP_REG_VWLAN1C,
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CPCAP_REG_VWLAN2C,
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CPCAP_REG_VSIMC,
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CPCAP_REG_VVIBC,
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CPCAP_REG_VUSBC,
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CPCAP_REG_VUSBINT1C,
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CPCAP_REG_VUSBINT2C,
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CPCAP_REG_URT,
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CPCAP_REG_URM1,
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CPCAP_REG_URM2,
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CPCAP_REG_VAUDIOC,
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CPCAP_REG_CC,
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CPCAP_REG_CDI,
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CPCAP_REG_SDAC,
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CPCAP_REG_SDACDI,
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CPCAP_REG_TXI,
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CPCAP_REG_TXMP,
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CPCAP_REG_RXOA,
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CPCAP_REG_RXVC,
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CPCAP_REG_RXCOA,
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CPCAP_REG_RXSDOA,
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CPCAP_REG_RXEPOA,
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CPCAP_REG_RXLL,
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CPCAP_REG_A2LA,
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CPCAP_REG_MIPIS1,
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CPCAP_REG_MIPIS2,
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CPCAP_REG_MIPIS3,
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CPCAP_REG_LVAB,
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CPCAP_REG_CCC1,
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CPCAP_REG_CRM,
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CPCAP_REG_CCCC2,
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CPCAP_REG_CCS1,
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CPCAP_REG_CCS2,
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CPCAP_REG_CCA1,
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CPCAP_REG_CCA2,
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CPCAP_REG_CCM,
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CPCAP_REG_CCO,
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CPCAP_REG_CCI,
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CPCAP_REG_ADCC1,
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CPCAP_REG_ADCC2,
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CPCAP_REG_ADCD0,
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CPCAP_REG_ADCD1,
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CPCAP_REG_ADCD2,
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CPCAP_REG_ADCD3,
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CPCAP_REG_ADCD4,
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CPCAP_REG_ADCD5,
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CPCAP_REG_ADCD6,
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CPCAP_REG_ADCD7,
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CPCAP_REG_ADCAL1,
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CPCAP_REG_ADCAL2,
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CPCAP_REG_USBC1,
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CPCAP_REG_USBC2,
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CPCAP_REG_USBC3,
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CPCAP_REG_UVIDL,
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CPCAP_REG_UVIDH,
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CPCAP_REG_UPIDL,
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CPCAP_REG_UPIDH,
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CPCAP_REG_UFC1,
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CPCAP_REG_UFC2,
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CPCAP_REG_UFC3,
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CPCAP_REG_UIC1,
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CPCAP_REG_UIC2,
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CPCAP_REG_UIC3,
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CPCAP_REG_USBOTG1,
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CPCAP_REG_USBOTG2,
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CPCAP_REG_USBOTG3,
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CPCAP_REG_UIER1,
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CPCAP_REG_UIER2,
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CPCAP_REG_UIER3,
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CPCAP_REG_UIEF1,
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CPCAP_REG_UIEF2,
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CPCAP_REG_UIEF3,
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CPCAP_REG_UIS,
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CPCAP_REG_UIL,
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CPCAP_REG_USBD,
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CPCAP_REG_SCR1,
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CPCAP_REG_SCR2,
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CPCAP_REG_SCR3,
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CPCAP_REG_VMC,
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CPCAP_REG_OWDC,
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CPCAP_REG_GPIO0,
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CPCAP_REG_GPIO1,
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CPCAP_REG_GPIO2,
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CPCAP_REG_GPIO3,
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CPCAP_REG_GPIO4,
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CPCAP_REG_GPIO5,
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CPCAP_REG_GPIO6,
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CPCAP_REG_MDLC,
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CPCAP_REG_KLC,
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CPCAP_REG_ADLC,
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CPCAP_REG_REDC,
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CPCAP_REG_GREENC,
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CPCAP_REG_BLUEC,
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CPCAP_REG_CFC,
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CPCAP_REG_ABC,
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CPCAP_REG_BLEDC,
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CPCAP_REG_CLEDC,
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CPCAP_REG_OW1C,
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CPCAP_REG_OW1D,
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CPCAP_REG_OW1I,
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CPCAP_REG_OW1IE,
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CPCAP_REG_OW1,
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CPCAP_REG_OW2C,
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CPCAP_REG_OW2D,
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CPCAP_REG_OW2I,
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CPCAP_REG_OW2IE,
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CPCAP_REG_OW2,
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CPCAP_REG_OW3C,
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CPCAP_REG_OW3D,
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CPCAP_REG_OW3I,
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CPCAP_REG_OW3IE,
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CPCAP_REG_OW3,
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CPCAP_REG_GCAIC,
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CPCAP_REG_GCAIM,
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CPCAP_REG_LGDIR,
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CPCAP_REG_LGPU,
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CPCAP_REG_LGPIN,
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CPCAP_REG_LGMASK,
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CPCAP_REG_LDEB,
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CPCAP_REG_LGDET,
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CPCAP_REG_LMISC,
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CPCAP_REG_LMACE,
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CPCAP_REG_END = CPCAP_REG_LMACE,
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CPCAP_REG_MAX
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= CPCAP_REG_END,
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CPCAP_REG_SIZE = CPCAP_REG_MAX + 1,
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CPCAP_REG_UNUSED = CPCAP_REG_MAX + 2,
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};
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enum {
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CPCAP_IOCTL_NUM_TEST__START,
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CPCAP_IOCTL_NUM_TEST_READ_REG,
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CPCAP_IOCTL_NUM_TEST_WRITE_REG,
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CPCAP_IOCTL_NUM_TEST__END,
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CPCAP_IOCTL_NUM_ADC__START,
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CPCAP_IOCTL_NUM_ADC_PHASE,
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CPCAP_IOCTL_NUM_ADC__END,
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CPCAP_IOCTL_NUM_BATT__START,
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CPCAP_IOCTL_NUM_BATT_DISPLAY_UPDATE,
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CPCAP_IOCTL_NUM_BATT_ATOD_ASYNC,
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CPCAP_IOCTL_NUM_BATT_ATOD_SYNC,
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CPCAP_IOCTL_NUM_BATT_ATOD_READ,
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CPCAP_IOCTL_NUM_BATT__END,
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CPCAP_IOCTL_NUM_UC__START,
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CPCAP_IOCTL_NUM_UC_MACRO_START,
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CPCAP_IOCTL_NUM_UC_MACRO_STOP,
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CPCAP_IOCTL_NUM_UC_GET_VENDOR,
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CPCAP_IOCTL_NUM_UC_SET_TURBO_MODE,
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CPCAP_IOCTL_NUM_UC__END,
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CPCAP_IOCTL_NUM_ACCY__START,
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CPCAP_IOCTL_NUM_ACCY_WHISPER,
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CPCAP_IOCTL_NUM_ACCY__END,
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};
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enum cpcap_irqs {
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CPCAP_IRQ__START,
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CPCAP_IRQ_HSCLK = CPCAP_IRQ_INT1_INDEX,
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CPCAP_IRQ_PRIMAC,
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CPCAP_IRQ_SECMAC,
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CPCAP_IRQ_LOWBPL,
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CPCAP_IRQ_SEC2PRI,
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CPCAP_IRQ_LOWBPH,
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CPCAP_IRQ_EOL,
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CPCAP_IRQ_TS,
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CPCAP_IRQ_ADCDONE,
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CPCAP_IRQ_HS,
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CPCAP_IRQ_MB2,
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CPCAP_IRQ_VBUSOV,
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CPCAP_IRQ_RVRS_CHRG,
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CPCAP_IRQ_CHRG_DET,
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CPCAP_IRQ_IDFLOAT,
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CPCAP_IRQ_IDGND,
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CPCAP_IRQ_SE1 = CPCAP_IRQ_INT2_INDEX,
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CPCAP_IRQ_SESSEND,
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CPCAP_IRQ_SESSVLD,
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CPCAP_IRQ_VBUSVLD,
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CPCAP_IRQ_CHRG_CURR1,
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CPCAP_IRQ_CHRG_CURR2,
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CPCAP_IRQ_RVRS_MODE,
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CPCAP_IRQ_ON,
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CPCAP_IRQ_ON2,
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CPCAP_IRQ_CLK,
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CPCAP_IRQ_1HZ,
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CPCAP_IRQ_PTT,
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CPCAP_IRQ_SE0CONN,
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CPCAP_IRQ_CHRG_SE1B,
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CPCAP_IRQ_UART_ECHO_OVERRUN,
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CPCAP_IRQ_EXTMEMHD,
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CPCAP_IRQ_WARM = CPCAP_IRQ_INT3_INDEX,
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CPCAP_IRQ_SYSRSTR,
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CPCAP_IRQ_SOFTRST,
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CPCAP_IRQ_DIEPWRDWN,
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CPCAP_IRQ_DIETEMPH,
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CPCAP_IRQ_PC,
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CPCAP_IRQ_OFLOWSW,
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CPCAP_IRQ_TODA,
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CPCAP_IRQ_OPT_SEL_DTCH,
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CPCAP_IRQ_OPT_SEL_STATE,
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CPCAP_IRQ_ONEWIRE1,
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CPCAP_IRQ_ONEWIRE2,
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CPCAP_IRQ_ONEWIRE3,
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CPCAP_IRQ_UCRESET,
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CPCAP_IRQ_PWRGOOD,
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CPCAP_IRQ_USBDPLLCLK,
|
||
|
|
|
||
|
|
CPCAP_IRQ_DPI = CPCAP_IRQ_INT4_INDEX,
|
||
|
|
CPCAP_IRQ_DMI,
|
||
|
|
CPCAP_IRQ_UCBUSY,
|
||
|
|
CPCAP_IRQ_GCAI_CURR1,
|
||
|
|
CPCAP_IRQ_GCAI_CURR2,
|
||
|
|
CPCAP_IRQ_SB_MAX_RETRANSMIT_ERR,
|
||
|
|
CPCAP_IRQ_BATTDETB,
|
||
|
|
CPCAP_IRQ_PRIHALT,
|
||
|
|
CPCAP_IRQ_SECHALT,
|
||
|
|
CPCAP_IRQ_CC_CAL,
|
||
|
|
|
||
|
|
CPCAP_IRQ_UC_PRIROMR = CPCAP_IRQ_INT5_INDEX,
|
||
|
|
CPCAP_IRQ_UC_PRIRAMW,
|
||
|
|
CPCAP_IRQ_UC_PRIRAMR,
|
||
|
|
CPCAP_IRQ_UC_USEROFF,
|
||
|
|
CPCAP_IRQ_UC_PRIMACRO_4,
|
||
|
|
CPCAP_IRQ_UC_PRIMACRO_5,
|
||
|
|
CPCAP_IRQ_UC_PRIMACRO_6,
|
||
|
|
CPCAP_IRQ_UC_PRIMACRO_7,
|
||
|
|
CPCAP_IRQ_UC_PRIMACRO_8,
|
||
|
|
CPCAP_IRQ_UC_PRIMACRO_9,
|
||
|
|
CPCAP_IRQ_UC_PRIMACRO_10,
|
||
|
|
CPCAP_IRQ_UC_PRIMACRO_11,
|
||
|
|
CPCAP_IRQ_UC_PRIMACRO_12,
|
||
|
|
CPCAP_IRQ_UC_PRIMACRO_13,
|
||
|
|
CPCAP_IRQ_UC_PRIMACRO_14,
|
||
|
|
CPCAP_IRQ_UC_PRIMACRO_15,
|
||
|
|
CPCAP_IRQ__NUM
|
||
|
|
};
|
||
|
|
|
||
|
|
enum cpcap_adc_bank0 {
|
||
|
|
CPCAP_ADC_AD0_BATTDETB,
|
||
|
|
CPCAP_ADC_BATTP,
|
||
|
|
CPCAP_ADC_VBUS,
|
||
|
|
CPCAP_ADC_AD3,
|
||
|
|
CPCAP_ADC_BPLUS_AD4,
|
||
|
|
CPCAP_ADC_CHG_ISENSE,
|
||
|
|
CPCAP_ADC_BATTI_ADC,
|
||
|
|
CPCAP_ADC_USB_ID,
|
||
|
|
|
||
|
|
CPCAP_ADC_BANK0_NUM,
|
||
|
|
};
|
||
|
|
|
||
|
|
enum cpcap_adc_bank1 {
|
||
|
|
CPCAP_ADC_AD8,
|
||
|
|
CPCAP_ADC_AD9,
|
||
|
|
CPCAP_ADC_LICELL,
|
||
|
|
CPCAP_ADC_HV_BATTP,
|
||
|
|
CPCAP_ADC_TSX1_AD12,
|
||
|
|
CPCAP_ADC_TSX2_AD13,
|
||
|
|
CPCAP_ADC_TSY1_AD14,
|
||
|
|
CPCAP_ADC_TSY2_AD15,
|
||
|
|
|
||
|
|
CPCAP_ADC_BANK1_NUM,
|
||
|
|
};
|
||
|
|
|
||
|
|
enum cpcap_adc_format {
|
||
|
|
CPCAP_ADC_FORMAT_RAW,
|
||
|
|
CPCAP_ADC_FORMAT_PHASED,
|
||
|
|
CPCAP_ADC_FORMAT_CONVERTED,
|
||
|
|
};
|
||
|
|
|
||
|
|
enum cpcap_adc_timing {
|
||
|
|
CPCAP_ADC_TIMING_IMM,
|
||
|
|
CPCAP_ADC_TIMING_IN,
|
||
|
|
CPCAP_ADC_TIMING_OUT,
|
||
|
|
};
|
||
|
|
|
||
|
|
enum cpcap_adc_type {
|
||
|
|
CPCAP_ADC_TYPE_BANK_0,
|
||
|
|
CPCAP_ADC_TYPE_BANK_1,
|
||
|
|
CPCAP_ADC_TYPE_BATT_PI,
|
||
|
|
};
|
||
|
|
|
||
|
|
enum cpcap_macro {
|
||
|
|
CPCAP_MACRO_ROMR,
|
||
|
|
CPCAP_MACRO_RAMW,
|
||
|
|
CPCAP_MACRO_RAMR,
|
||
|
|
CPCAP_MACRO_USEROFF,
|
||
|
|
CPCAP_MACRO_4,
|
||
|
|
CPCAP_MACRO_5,
|
||
|
|
CPCAP_MACRO_6,
|
||
|
|
CPCAP_MACRO_7,
|
||
|
|
CPCAP_MACRO_8,
|
||
|
|
CPCAP_MACRO_9,
|
||
|
|
CPCAP_MACRO_10,
|
||
|
|
CPCAP_MACRO_11,
|
||
|
|
CPCAP_MACRO_12,
|
||
|
|
CPCAP_MACRO_13,
|
||
|
|
CPCAP_MACRO_14,
|
||
|
|
CPCAP_MACRO_15,
|
||
|
|
|
||
|
|
CPCAP_MACRO__END,
|
||
|
|
};
|
||
|
|
|
||
|
|
enum cpcap_vendor {
|
||
|
|
CPCAP_VENDOR_ST,
|
||
|
|
CPCAP_VENDOR_TI,
|
||
|
|
};
|
||
|
|
|
||
|
|
enum cpcap_revision {
|
||
|
|
CPCAP_REVISION_1_0 = 0x08,
|
||
|
|
CPCAP_REVISION_1_1 = 0x09,
|
||
|
|
CPCAP_REVISION_2_0 = 0x10,
|
||
|
|
CPCAP_REVISION_2_1 = 0x11,
|
||
|
|
};
|
||
|
|
|
||
|
|
enum cpcap_batt_usb_model {
|
||
|
|
CPCAP_BATT_USB_MODEL_NONE,
|
||
|
|
CPCAP_BATT_USB_MODEL_USB,
|
||
|
|
CPCAP_BATT_USB_MODEL_FACTORY,
|
||
|
|
};
|
||
|
|
|
||
|
|
struct cpcap_spi_init_data {
|
||
|
|
enum cpcap_reg reg;
|
||
|
|
unsigned short data;
|
||
|
|
};
|
||
|
|
|
||
|
|
struct cpcap_adc_ato {
|
||
|
|
unsigned short ato_in;
|
||
|
|
unsigned short atox_in;
|
||
|
|
unsigned short adc_ps_factor_in;
|
||
|
|
unsigned short atox_ps_factor_in;
|
||
|
|
unsigned short ato_out;
|
||
|
|
unsigned short atox_out;
|
||
|
|
unsigned short adc_ps_factor_out;
|
||
|
|
unsigned short atox_ps_factor_out;
|
||
|
|
};
|
||
|
|
|
||
|
|
struct cpcap_batt_data {
|
||
|
|
int status;
|
||
|
|
int health;
|
||
|
|
int present;
|
||
|
|
int capacity;
|
||
|
|
int batt_volt;
|
||
|
|
int batt_temp;
|
||
|
|
};
|
||
|
|
|
||
|
|
struct cpcap_batt_ac_data {
|
||
|
|
int online;
|
||
|
|
};
|
||
|
|
|
||
|
|
struct cpcap_batt_usb_data {
|
||
|
|
int online;
|
||
|
|
int current_now;
|
||
|
|
enum cpcap_batt_usb_model model;
|
||
|
|
};
|
||
|
|
|
||
|
|
struct cpcap_device;
|
||
|
|
|
||
|
|
struct cpcap_adc_us_request {
|
||
|
|
enum cpcap_adc_format format;
|
||
|
|
enum cpcap_adc_timing timing;
|
||
|
|
enum cpcap_adc_type type;
|
||
|
|
int status;
|
||
|
|
int result[CPCAP_ADC_BANK0_NUM];
|
||
|
|
};
|
||
|
|
|
||
|
|
struct cpcap_adc_phase {
|
||
|
|
signed char offset_batti;
|
||
|
|
unsigned char slope_batti;
|
||
|
|
signed char offset_chrgi;
|
||
|
|
unsigned char slope_chrgi;
|
||
|
|
signed char offset_battp;
|
||
|
|
unsigned char slope_battp;
|
||
|
|
signed char offset_bp;
|
||
|
|
unsigned char slope_bp;
|
||
|
|
signed char offset_battt;
|
||
|
|
unsigned char slope_battt;
|
||
|
|
signed char offset_chrgv;
|
||
|
|
unsigned char slope_chrgv;
|
||
|
|
};
|
||
|
|
|
||
|
|
struct cpcap_regacc {
|
||
|
|
unsigned short reg;
|
||
|
|
unsigned short value;
|
||
|
|
unsigned short mask;
|
||
|
|
};
|
||
|
|
|
||
|
|
struct cpcap_whisper_request {
|
||
|
|
unsigned int cmd;
|
||
|
|
char dock_id[CPCAP_WHISPER_ID_SIZE];
|
||
|
|
};
|
||
|
|
|
||
|
|
#define CPCAP_IOCTL_TEST_READ_REG _IOWR(0, CPCAP_IOCTL_NUM_TEST_READ_REG, struct cpcap_regacc*)
|
||
|
|
|
||
|
|
#define CPCAP_IOCTL_TEST_WRITE_REG _IOWR(0, CPCAP_IOCTL_NUM_TEST_WRITE_REG, struct cpcap_regacc*)
|
||
|
|
|
||
|
|
#define CPCAP_IOCTL_ADC_PHASE _IOWR(0, CPCAP_IOCTL_NUM_ADC_PHASE, struct cpcap_adc_phase*)
|
||
|
|
|
||
|
|
#define CPCAP_IOCTL_BATT_DISPLAY_UPDATE _IOW(0, CPCAP_IOCTL_NUM_BATT_DISPLAY_UPDATE, struct cpcap_batt_data*)
|
||
|
|
|
||
|
|
#define CPCAP_IOCTL_BATT_ATOD_ASYNC _IOW(0, CPCAP_IOCTL_NUM_BATT_ATOD_ASYNC, struct cpcap_adc_us_request*)
|
||
|
|
|
||
|
|
#define CPCAP_IOCTL_BATT_ATOD_SYNC _IOWR(0, CPCAP_IOCTL_NUM_BATT_ATOD_SYNC, struct cpcap_adc_us_request*)
|
||
|
|
|
||
|
|
#define CPCAP_IOCTL_BATT_ATOD_READ _IOWR(0, CPCAP_IOCTL_NUM_BATT_ATOD_READ, struct cpcap_adc_us_request*)
|
||
|
|
|
||
|
|
#define CPCAP_IOCTL_UC_MACRO_START _IOWR(0, CPCAP_IOCTL_NUM_UC_MACRO_START, enum cpcap_macro)
|
||
|
|
|
||
|
|
#define CPCAP_IOCTL_UC_MACRO_STOP _IOWR(0, CPCAP_IOCTL_NUM_UC_MACRO_STOP, enum cpcap_macro)
|
||
|
|
|
||
|
|
#define CPCAP_IOCTL_UC_GET_VENDOR _IOWR(0, CPCAP_IOCTL_NUM_UC_GET_VENDOR, enum cpcap_vendor)
|
||
|
|
|
||
|
|
#define CPCAP_IOCTL_UC_SET_TURBO_MODE _IOW(0, CPCAP_IOCTL_NUM_UC_SET_TURBO_MODE, unsigned short)
|
||
|
|
|
||
|
|
#define CPCAP_IOCTL_ACCY_WHISPER _IOW(0, CPCAP_IOCTL_NUM_ACCY_WHISPER, struct cpcap_whisper_request*)
|
||
|
|
|
||
|
|
#endif
|
||
|
|
|