67 lines
3.1 KiB
C
67 lines
3.1 KiB
C
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/****************************************************************************
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****************************************************************************
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***
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*** This header was automatically generated from a Linux kernel header
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*** of the same name, to make information necessary for userspace to
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*** call into the kernel available to libc. It contains only constants,
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*** structures, and macros generated from the original header, and thus,
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*** contains no copyrightable information.
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***
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*** To edit the content of this header, modify the corresponding
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*** source file (e.g. under external/kernel-headers/original/) then
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*** run bionic/libc/kernel/tools/update_all.py
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***
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*** Any manual change here will be lost the next time this script will
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*** be run. You've been warned!
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***
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****************************************************************************
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****************************************************************************/
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#ifndef __ASM_MIPS_BOARDS_GENERIC_H
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#define __ASM_MIPS_BOARDS_GENERIC_H
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#include <asm/addrspace.h>
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#include <asm/byteorder.h>
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#include <asm/mips-boards/bonito64.h>
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#define ASCII_DISPLAY_WORD_BASE 0x1f000410
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#define ASCII_DISPLAY_POS_BASE 0x1f000418
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#define YAMON_PROM_PRINT_ADDR 0x1fc00504
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define SOFTRES_REG 0x1f000500
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#define GORESET 0x42
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#define MIPS_REVISION_REG 0x1fc00010
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#define MIPS_REVISION_CORID_QED_RM5261 0
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define MIPS_REVISION_CORID_CORE_LV 1
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#define MIPS_REVISION_CORID_BONITO64 2
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#define MIPS_REVISION_CORID_CORE_20K 3
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#define MIPS_REVISION_CORID_CORE_FPGA 4
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define MIPS_REVISION_CORID_CORE_MSC 5
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#define MIPS_REVISION_CORID_CORE_EMUL 6
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#define MIPS_REVISION_CORID_CORE_FPGA2 7
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#define MIPS_REVISION_CORID_CORE_FPGAR2 8
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define MIPS_REVISION_CORID_CORE_FPGA3 9
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#define MIPS_REVISION_CORID_CORE_24K 10
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#define MIPS_REVISION_CORID_CORE_FPGA4 11
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#define MIPS_REVISION_CORID_CORE_FPGA5 12
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define MIPS_REVISION_CORID_CORE_EMUL_BON -1
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#define MIPS_REVISION_CORID_CORE_EMUL_MSC -2
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#define MIPS_REVISION_CORID (((*(volatile u32 *)ioremap(MIPS_REVISION_REG, 4)) >> 10) & 0x3f)
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#define MIPS_REVISION_SCON_OTHER 0
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define MIPS_REVISION_SCON_SOCITSC 1
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#define MIPS_REVISION_SCON_SOCITSCP 2
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#define MIPS_REVISION_SCON_UNKNOWN -1
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#define MIPS_REVISION_SCON_GT64120 -2
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define MIPS_REVISION_SCON_BONITO -3
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#define MIPS_REVISION_SCON_BRTL -4
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#define MIPS_REVISION_SCON_SOCIT -5
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#define MIPS_REVISION_SCON_ROCIT -6
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define MIPS_REVISION_SCONID (((*(volatile u32 *)ioremap(MIPS_REVISION_REG, 4)) >> 24) & 0xff)
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#define mips_pcibios_init() do { } while (0)
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#endif
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