120 lines
3.0 KiB
C
120 lines
3.0 KiB
C
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/* $OpenBSD: regnum.h,v 1.3 2004/08/10 20:28:13 deraadt Exp $ */
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/*
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* Copyright (c) 2001-2002 Opsycon AB (www.opsycon.se / www.opsycon.com)
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
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* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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#ifndef _MIPS64_REGNUM_H_
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#define _MIPS64_REGNUM_H_
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/*
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* Location of the saved registers relative to ZERO.
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* Usage is p->p_regs[XX].
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*/
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#define ZERO 0
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#define AST 1
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#define V0 2
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#define V1 3
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#define A0 4
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#define A1 5
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#define A2 6
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#define A3 7
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#define T0 8
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#define T1 9
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#define T2 10
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#define T3 11
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#define T4 12
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#define T5 13
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#define T6 14
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#define T7 15
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#define S0 16
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#define S1 17
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#define S2 18
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#define S3 19
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#define S4 20
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#define S5 21
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#define S6 22
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#define S7 23
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#define T8 24
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#define T9 25
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#define K0 26
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#define K1 27
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#define GP 28
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#define SP 29
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#define S8 30
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#define RA 31
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#define SR 32
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#define PS SR /* alias for SR */
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#define MULLO 33
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#define MULHI 34
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#define BADVADDR 35
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#define CAUSE 36
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#define PC 37
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#define IC 38
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#define CPL 39
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#define NUMSAVEREGS 40 /* Number of registers saved in trap */
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#define FPBASE NUMSAVEREGS
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#define F0 (FPBASE+0)
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#define F1 (FPBASE+1)
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#define F2 (FPBASE+2)
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#define F3 (FPBASE+3)
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#define F4 (FPBASE+4)
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#define F5 (FPBASE+5)
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#define F6 (FPBASE+6)
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#define F7 (FPBASE+7)
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#define F8 (FPBASE+8)
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#define F9 (FPBASE+9)
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#define F10 (FPBASE+10)
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#define F11 (FPBASE+11)
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#define F12 (FPBASE+12)
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#define F13 (FPBASE+13)
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#define F14 (FPBASE+14)
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#define F15 (FPBASE+15)
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#define F16 (FPBASE+16)
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#define F17 (FPBASE+17)
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#define F18 (FPBASE+18)
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#define F19 (FPBASE+19)
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#define F20 (FPBASE+20)
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#define F21 (FPBASE+21)
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#define F22 (FPBASE+22)
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#define F23 (FPBASE+23)
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#define F24 (FPBASE+24)
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#define F25 (FPBASE+25)
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#define F26 (FPBASE+26)
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#define F27 (FPBASE+27)
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#define F28 (FPBASE+28)
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#define F29 (FPBASE+29)
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#define F30 (FPBASE+30)
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#define F31 (FPBASE+31)
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#define FSR (FPBASE+32)
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#define NUMFPREGS 33
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#define NREGS (NUMSAVEREGS + NUMFPREGS)
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#endif /* !_MIPS64_REGNUM_H_ */
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