282 lines
10 KiB
C
282 lines
10 KiB
C
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/****************************************************************************
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****************************************************************************
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***
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*** This header was automatically generated from a Linux kernel header
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*** of the same name, to make information necessary for userspace to
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*** call into the kernel available to libc. It contains only constants,
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*** structures, and macros generated from the original header, and thus,
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*** contains no copyrightable information.
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***
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*** To edit the content of this header, modify the corresponding
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*** source file (e.g. under external/kernel-headers/original/) then
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*** run bionic/libc/kernel/tools/update_all.py
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***
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*** Any manual change here will be lost the next time this script will
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*** be run. You've been warned!
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***
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****************************************************************************
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****************************************************************************/
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#ifndef _UAPI_EXYNOS_DRM_H_
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#define _UAPI_EXYNOS_DRM_H_
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#include <drm/drm.h>
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struct drm_exynos_gem_create {
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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uint64_t size;
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unsigned int flags;
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unsigned int handle;
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};
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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struct drm_exynos_gem_map_off {
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unsigned int handle;
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unsigned int pad;
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uint64_t offset;
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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};
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struct drm_exynos_gem_mmap {
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unsigned int handle;
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unsigned int pad;
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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uint64_t size;
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uint64_t mapped;
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};
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struct drm_exynos_gem_info {
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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unsigned int handle;
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unsigned int flags;
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uint64_t size;
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};
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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struct drm_exynos_vidi_connection {
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unsigned int connection;
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unsigned int extensions;
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uint64_t edid;
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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};
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enum e_drm_exynos_gem_mem_type {
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EXYNOS_BO_CONTIG = 0 << 0,
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EXYNOS_BO_NONCONTIG = 1 << 0,
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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EXYNOS_BO_NONCACHABLE = 0 << 1,
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EXYNOS_BO_CACHABLE = 1 << 1,
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EXYNOS_BO_WC = 1 << 2,
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EXYNOS_BO_MASK = EXYNOS_BO_NONCONTIG | EXYNOS_BO_CACHABLE |
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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EXYNOS_BO_WC
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};
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struct drm_exynos_g2d_get_ver {
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__u32 major;
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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__u32 minor;
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};
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struct drm_exynos_g2d_cmd {
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__u32 offset;
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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__u32 data;
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};
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enum drm_exynos_g2d_buf_type {
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G2D_BUF_USERPTR = 1 << 31,
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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};
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enum drm_exynos_g2d_event_type {
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G2D_EVENT_NOT,
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G2D_EVENT_NONSTOP,
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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G2D_EVENT_STOP,
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};
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struct drm_exynos_g2d_userptr {
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unsigned long userptr;
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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unsigned long size;
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};
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struct drm_exynos_g2d_set_cmdlist {
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__u64 cmd;
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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__u64 cmd_buf;
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__u32 cmd_nr;
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__u32 cmd_buf_nr;
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__u64 event_type;
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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__u64 user_data;
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};
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struct drm_exynos_g2d_exec {
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__u64 async;
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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};
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enum drm_exynos_ops_id {
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EXYNOS_DRM_OPS_SRC,
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EXYNOS_DRM_OPS_DST,
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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EXYNOS_DRM_OPS_MAX,
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};
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struct drm_exynos_sz {
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__u32 hsize;
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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__u32 vsize;
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};
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struct drm_exynos_pos {
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__u32 x;
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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__u32 y;
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__u32 w;
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__u32 h;
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};
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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enum drm_exynos_flip {
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EXYNOS_DRM_FLIP_NONE = (0 << 0),
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EXYNOS_DRM_FLIP_VERTICAL = (1 << 0),
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EXYNOS_DRM_FLIP_HORIZONTAL = (1 << 1),
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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EXYNOS_DRM_FLIP_BOTH = EXYNOS_DRM_FLIP_VERTICAL |
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EXYNOS_DRM_FLIP_HORIZONTAL,
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};
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enum drm_exynos_degree {
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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EXYNOS_DRM_DEGREE_0,
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EXYNOS_DRM_DEGREE_90,
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EXYNOS_DRM_DEGREE_180,
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EXYNOS_DRM_DEGREE_270,
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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};
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enum drm_exynos_planer {
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EXYNOS_DRM_PLANAR_Y,
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EXYNOS_DRM_PLANAR_CB,
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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EXYNOS_DRM_PLANAR_CR,
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EXYNOS_DRM_PLANAR_MAX,
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};
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struct drm_exynos_ipp_prop_list {
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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__u32 version;
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__u32 ipp_id;
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__u32 count;
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__u32 writeback;
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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__u32 flip;
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__u32 degree;
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__u32 csc;
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__u32 crop;
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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__u32 scale;
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__u32 refresh_min;
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__u32 refresh_max;
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__u32 reserved;
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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struct drm_exynos_sz crop_min;
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struct drm_exynos_sz crop_max;
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struct drm_exynos_sz scale_min;
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struct drm_exynos_sz scale_max;
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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};
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struct drm_exynos_ipp_config {
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enum drm_exynos_ops_id ops_id;
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enum drm_exynos_flip flip;
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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enum drm_exynos_degree degree;
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__u32 fmt;
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struct drm_exynos_sz sz;
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struct drm_exynos_pos pos;
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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};
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enum drm_exynos_ipp_cmd {
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IPP_CMD_NONE,
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IPP_CMD_M2M,
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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IPP_CMD_WB,
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IPP_CMD_OUTPUT,
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IPP_CMD_MAX,
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};
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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struct drm_exynos_ipp_property {
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struct drm_exynos_ipp_config config[EXYNOS_DRM_OPS_MAX];
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enum drm_exynos_ipp_cmd cmd;
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__u32 ipp_id;
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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__u32 prop_id;
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__u32 refresh_rate;
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};
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enum drm_exynos_ipp_buf_type {
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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IPP_BUF_ENQUEUE,
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IPP_BUF_DEQUEUE,
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};
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struct drm_exynos_ipp_queue_buf {
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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enum drm_exynos_ops_id ops_id;
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enum drm_exynos_ipp_buf_type buf_type;
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__u32 prop_id;
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__u32 buf_id;
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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__u32 handle[EXYNOS_DRM_PLANAR_MAX];
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__u32 reserved;
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__u64 user_data;
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};
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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enum drm_exynos_ipp_ctrl {
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IPP_CTRL_PLAY,
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IPP_CTRL_STOP,
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IPP_CTRL_PAUSE,
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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IPP_CTRL_RESUME,
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IPP_CTRL_MAX,
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};
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struct drm_exynos_ipp_cmd_ctrl {
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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__u32 prop_id;
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enum drm_exynos_ipp_ctrl ctrl;
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};
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#define DRM_EXYNOS_GEM_CREATE 0x00
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define DRM_EXYNOS_GEM_MAP_OFFSET 0x01
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#define DRM_EXYNOS_GEM_MMAP 0x02
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#define DRM_EXYNOS_GEM_GET 0x04
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#define DRM_EXYNOS_VIDI_CONNECTION 0x07
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define DRM_EXYNOS_G2D_GET_VER 0x20
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#define DRM_EXYNOS_G2D_SET_CMDLIST 0x21
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#define DRM_EXYNOS_G2D_EXEC 0x22
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#define DRM_EXYNOS_IPP_GET_PROPERTY 0x30
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define DRM_EXYNOS_IPP_SET_PROPERTY 0x31
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#define DRM_EXYNOS_IPP_QUEUE_BUF 0x32
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#define DRM_EXYNOS_IPP_CMD_CTRL 0x33
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#define DRM_IOCTL_EXYNOS_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_GEM_CREATE, struct drm_exynos_gem_create)
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define DRM_IOCTL_EXYNOS_GEM_MAP_OFFSET DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_GEM_MAP_OFFSET, struct drm_exynos_gem_map_off)
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#define DRM_IOCTL_EXYNOS_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_GEM_MMAP, struct drm_exynos_gem_mmap)
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#define DRM_IOCTL_EXYNOS_GEM_GET DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_GEM_GET, struct drm_exynos_gem_info)
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#define DRM_IOCTL_EXYNOS_VIDI_CONNECTION DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_VIDI_CONNECTION, struct drm_exynos_vidi_connection)
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define DRM_IOCTL_EXYNOS_G2D_GET_VER DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_G2D_GET_VER, struct drm_exynos_g2d_get_ver)
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#define DRM_IOCTL_EXYNOS_G2D_SET_CMDLIST DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_G2D_SET_CMDLIST, struct drm_exynos_g2d_set_cmdlist)
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#define DRM_IOCTL_EXYNOS_G2D_EXEC DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_G2D_EXEC, struct drm_exynos_g2d_exec)
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#define DRM_IOCTL_EXYNOS_IPP_GET_PROPERTY DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_IPP_GET_PROPERTY, struct drm_exynos_ipp_prop_list)
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define DRM_IOCTL_EXYNOS_IPP_SET_PROPERTY DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_IPP_SET_PROPERTY, struct drm_exynos_ipp_property)
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#define DRM_IOCTL_EXYNOS_IPP_QUEUE_BUF DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_IPP_QUEUE_BUF, struct drm_exynos_ipp_queue_buf)
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#define DRM_IOCTL_EXYNOS_IPP_CMD_CTRL DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_IPP_CMD_CTRL, struct drm_exynos_ipp_cmd_ctrl)
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#define DRM_EXYNOS_G2D_EVENT 0x80000000
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define DRM_EXYNOS_IPP_EVENT 0x80000001
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struct drm_exynos_g2d_event {
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struct drm_event base;
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__u64 user_data;
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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__u32 tv_sec;
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__u32 tv_usec;
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__u32 cmdlist_no;
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__u32 reserved;
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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};
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struct drm_exynos_ipp_event {
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struct drm_event base;
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__u64 user_data;
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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__u32 tv_sec;
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__u32 tv_usec;
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__u32 prop_id;
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__u32 reserved;
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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__u32 buf_id[EXYNOS_DRM_OPS_MAX];
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};
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#endif
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