53 lines
1.9 KiB
Plaintext
53 lines
1.9 KiB
Plaintext
* Freescale Quad Serial Peripheral Interface(QuadSPI)
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The QuadSPI controller acts as the SPI master. It is described with a node
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for the controller and a set of child nodes for each SPI NOR flash.
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Part I - The DT node for the controller:
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------------------------------
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Required properties:
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- compatible : Should be "fsl,vf610-qspi"
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- reg : the first contains the register location and length,
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the second contains the memory mapping address and length
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- reg-names: Should contain the reg names "QuadSPI" and "QuadSPI-memory"
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- interrupts : Should contain the interrupt for the device
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- clocks : The clocks needed by the QuadSPI controller
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- clock-names : the name of the clocks
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Optional properties:
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- fsl,qspi-has-second-chip: The controller has two buses, bus A and bus B.
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Each bus can be connected with two NOR flashes.
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Most of the time, each bus only has one NOR flash
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connected, this is the default case.
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But if there are two NOR flashes connected to the
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bus, you should enable this property.
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(Please check the board's schematic.)
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- ddrsmp: The value for DDR internal sampling point, range is 0 - 7.
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Part II - The DT nodes for each SPI NOR flash
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------------------------------
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Required properties:
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- spi-max-frequency : Maximum frequency of the SPI bus the chip can operate at
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Optional properties:
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Please refer to the Documentation/devicetree/bindings/mtd/spi-nor-flash.txt
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If you set the "spi-nor,ddr-quad-read-dummy", it means you enable the DDR
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quad read feature for the driver.
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Example:
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qspi0: quadspi@40044000 {
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compatible = "fsl,vf610-qspi";
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reg = <0x40044000 0x1000>, <0x20000000 0x10000000>;
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reg-names = "QuadSPI", "QuadSPI-memory";
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interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks VF610_CLK_QSPI0_EN>,
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<&clks VF610_CLK_QSPI0>;
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clock-names = "qspi_en", "qspi";
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flash0: s25fl128s@0 {
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....
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};
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};
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