85 lines
2.0 KiB
Plaintext
85 lines
2.0 KiB
Plaintext
/*
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* Copyright (C) 2015 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include "imx7d-12x12-lpddr3-arm2.dts"
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/* disable epdc, conflict with qspi */
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&epdc {
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status = "disabled";
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};
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&iomuxc {
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qspi1 {
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pinctrl_qspi1_1: qspi1grp_1 {
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fsl,pins = <
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MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0 0x51
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MX7D_PAD_EPDC_DATA01__QSPI_A_DATA1 0x51
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MX7D_PAD_EPDC_DATA02__QSPI_A_DATA2 0x51
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MX7D_PAD_EPDC_DATA03__QSPI_A_DATA3 0x51
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MX7D_PAD_EPDC_DATA04__QSPI_A_DQS 0x51
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MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK 0x51
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MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B 0x51
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MX7D_PAD_EPDC_DATA07__QSPI_A_SS1_B 0x51
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MX7D_PAD_EPDC_DATA08__QSPI_B_DATA0 0x51
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MX7D_PAD_EPDC_DATA09__QSPI_B_DATA1 0x51
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MX7D_PAD_EPDC_DATA10__QSPI_B_DATA2 0x51
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MX7D_PAD_EPDC_DATA11__QSPI_B_DATA3 0x51
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MX7D_PAD_EPDC_DATA12__QSPI_B_DQS 0x51
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MX7D_PAD_EPDC_DATA13__QSPI_B_SCLK 0x51
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MX7D_PAD_EPDC_DATA14__QSPI_B_SS0_B 0x51
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MX7D_PAD_EPDC_DATA15__QSPI_B_SS1_B 0x51
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>;
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};
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};
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};
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&qspi1 {
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&pinctrl_qspi1_1>;
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pinctrl-1 = <&pinctrl_qspi1_1>;
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status = "okay";
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fsl,qspi-has-second-chip = <1>;
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ddrsmp=<0>;
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flash0: n25q256a@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "micron,n25q256a";
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spi-max-frequency = <29000000>;
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spi-nor,ddr-quad-read-dummy = <6>;
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reg = <0>;
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};
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flash1: n25q256a@1 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "micron,n25q256a";
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spi-max-frequency = <29000000>;
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spi-nor,ddr-quad-read-dummy = <6>;
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reg = <1>;
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};
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flash2: n25q256a@2 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "micron,n25q256a";
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spi-max-frequency = <29000000>;
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spi-nor,ddr-quad-read-dummy = <6>;
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reg = <2>;
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};
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flash3: n25q256a@3 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "micron,n25q256a";
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spi-max-frequency = <29000000>;
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spi-nor,ddr-quad-read-dummy = <6>;
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reg = <3>;
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};
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};
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