119 lines
4.2 KiB
Plaintext
119 lines
4.2 KiB
Plaintext
* FSL IPUv3 Display/FB
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The FSL IPUv3 is Image Processing Unit version 3, a part of video and graphics
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subsystem in an application processor. The goal of the IPU is to provide
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comprehensive support for the flow of data from an image sensor or/and to a
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display device.
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Two IPU units are on the imx6q SOC while only one IPU unit on the imx6dl SOC.
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Each IPU unit has two display interfaces.
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Required properties for IPU:
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- bypass_reset :Bypass reset to avoid display channel being.
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stopped by probe since it may start to work in bootloader: 0 or 1.
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- compatible : should be "fsl,imx6q-ipu".
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- reg : the register address range.
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- interrupts : the error and sync interrupts request.
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- clocks : the clock sources that it depends on.
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- clock-names: the related clock names.
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- resets : IPU reset specifier. See reset.txt and fsl,imx-src.txt in
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Documentation/devicetree/bindings/reset/ for details.
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Required properties for fb:
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- compatible : should be "fsl,mxc_sdc_fb".
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- disp_dev : display device: "ldb", "lcd", "hdmi", "mipi_dsi", "adv739x".
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- mode_str : video mode string: "LDB-XGA" or "LDB-1080P60" for ldb,
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"CLAA-WVGA" for lcd, "TRULY-WVGA" for TRULY mipi_dsi lcd panel,
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"1920x1080M@60" for hdmi, "BT656-NTSC" or "BT656-PAL" for adv739x.
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- default_bpp : default bits per pixel: 8/16/24/32
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- int_clk : use internal clock as pixel clock: 0 or 1
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- late_init : to avoid display channel being re-initialized
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as we've probably setup the channel in bootloader: 0 or 1
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- interface_pix_fmt : display interface pixel format as below:
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RGB666 IPU_PIX_FMT_RGB666
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RGB565 IPU_PIX_FMT_RGB565
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RGB24 IPU_PIX_FMT_RGB24
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BGR24 IPU_PIX_FMT_BGR24
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GBR24 IPU_PIX_FMT_GBR24
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YUV444 IPU_PIX_FMT_YUV444
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YUYV IPU_PIX_FMT_YUYV
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UYVY IPU_PIX_FMT_UYVY
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YVYV IPU_PIX_FMT_YVYU
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VYUY IPU_PIX_FMT_VYUY
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Required properties for display:
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- compatible : should be "fsl,lcd" for lcd panel
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- reg : the register address range if necessary to have.
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- interrupts : the error and sync interrupts if necessary to have.
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- clocks : the clock sources that it depends on if necessary to have.
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- clock-names: the related clock names if necessary to have.
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- ipu_id : ipu id for the first display device: 0 or 1
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- disp_id : display interface id for the first display interface: 0 or 1
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- default_ifmt : save as above display interface pixel format for lcd
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- pinctrl-names : should be "default"
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- pinctrl-0 : should be pinctrl_ipu1_1 or pinctrl_ipu2_1, which depends on the
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IPU connected.
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- gpr : the mux controller for the display engine's display interfaces and the display encoder
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(only valid for mipi dsi now).
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- disp-power-on-supply : the regulator to control display panel's power.
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(only valid for mipi dsi now).
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- resets : the gpio pin to reset the display device(only valid for mipi display panel now).
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- lcd_panel : the video mode name for the display device(only valid for mipi display panel now).
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- dev_id : the display engine's identity within the system, which intends to replace ipu_id
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(only valid for mipi dsi now).
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Example for IPU:
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ipu1: ipu@02400000 {
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compatible = "fsl,imx6q-ipu";
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reg = <0x02400000 0x400000>;
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interrupts = <0 6 0x4 0 5 0x4>;
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clocks = <&clks 130>, <&clks 131>, <&clks 132>,
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<&clks 39>, <&clks 40>,
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<&clks 135>, <&clks 136>;
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clock-names = "bus", "di0", "di1",
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"di0_sel", "di1_sel",
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"ldb_di0", "ldb_di1";
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resets = <&src 2>;
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bypass_reset = <0>;
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};
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Example for fb:
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fb0 {
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compatible = "fsl,mxc_sdc_fb";
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disp_dev = "ldb";
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interface_pix_fmt = "RGB666";
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mode_str ="LDB-XGA";
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default_bpp = <16>;
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int_clk = <0>;
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late_init = <0>;
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status = "okay";
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};
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Example for mipi dsi display:
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mipi_dsi: mipi@021e0000 {
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compatible = "fsl,imx6q-mipi-dsi";
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reg = <0x021e0000 0x4000>;
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interrupts = <0 102 0x04>;
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gpr = <&gpr>;
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clocks = <&clks 138>, <&clks 204>;
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clock-names = "mipi_pllref_clk", "mipi_cfg_clk";
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dev_id = <0>;
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disp_id = <0>;
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lcd_panel = "TRULY-WVGA";
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disp-power-on-supply = <®_mipi_dsi_pwr_on>
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resets = <&mipi_dsi_reset>;
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status = "okay";
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};
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Example for adv739x CVBS output:
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fb0 {
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compatible = "fsl,mxc_sdc_fb";
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disp_dev = "adv739x";
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interface_pix_fmt = "BT656";
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mode_str ="BT656-NTSC";
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default_bpp = <16>;
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int_clk = <0>;
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late_init = <0>;
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status = "okay";
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};
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