34 lines
1.0 KiB
C
34 lines
1.0 KiB
C
/*
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* Copyright (C) 2014-2015 Freescale Semiconductor, Inc. All Rights Reserved.
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*
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* SPDX-License-Identifier: GPL-2.0+ and/or BSD-3-Clause
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* The GPL-2.0+ license for this file can be found in the COPYING.GPL file
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* included with this distribution or at
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* http://www.gnu.org/licenses/gpl-2.0.html
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* The BSD-3-Clause License for this file can be found in the COPYING.BSD file
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* included with this distribution or at
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* http://opensource.org/licenses/BSD-3-Clause
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*/
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/*
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* Define the phiscal memory address on A9 and shared M4,
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* This definition should be aligned on both A9 and M4
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*/
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#define MCC_VECTOR_NUMBER_INVALID (0)
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enum {
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INT_CPU_TO_CPU_MU_A2M = 122,
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INT_CPU_TO_CPU_MU_M2A = 90,
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};
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/* Return core num. A9 0, M4 1 */
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unsigned int _psp_core_num(void);
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unsigned int _psp_node_num(void);
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unsigned int mcc_get_cpu_to_cpu_vector(unsigned int);
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/* Defined in MU driver */
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void mcc_clear_cpu_to_cpu_interrupt(void);
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int mcc_triger_cpu_to_cpu_interrupt(void);
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int imx_mcc_bsp_int_disable(void);
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int imx_mcc_bsp_int_enable(void);
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