158 lines
4.4 KiB
Plaintext
158 lines
4.4 KiB
Plaintext
/*
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* Copyright 2015 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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/ {
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aliases {
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pre0 = &pre1;
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pre1 = &pre2;
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pre2 = &pre3;
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pre3 = &pre4;
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prg0 = &prg1;
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prg1 = &prg2;
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};
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soc {
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ocram_2: sram@00940000 {
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compatible = "mmio-sram";
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reg = <0x00940000 0x20000>;
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clocks = <&clks IMX6QDL_CLK_OCRAM>;
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};
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ocram_3: sram@00960000 {
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compatible = "mmio-sram";
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reg = <0x00960000 0x20000>;
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clocks = <&clks IMX6QDL_CLK_OCRAM>;
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};
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pcie: pcie@0x01000000 {
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compatible = "fsl,imx6qp-pcie", "snps,dw-pcie";
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reg = <0x01ffc000 0x4000>, <0x01f00000 0x80000>;
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reg-names = "dbi", "config";
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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ranges = <0x81000000 0 0 0x01f80000 0 0x00010000 /* downstream I/O */
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0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */
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num-lanes = <1>;
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interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "msi";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0x7>;
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interrupt-map = <0 0 0 1 &intc 0 123 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 2 &intc 0 122 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 3 &intc 0 121 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 4 &intc 0 120 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX6QDL_CLK_PCIE_REF_125M>,
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<&clks IMX6QDL_CLK_SATA_REF_100M>,
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<&clks IMX6QDL_CLK_LVDS1_GATE>, <&clks IMX6QDL_CLK_PCIE_AXI>;
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clock-names = "pcie_phy", "ref_100m", "pcie_bus", "pcie";
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status = "disabled";
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};
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aips-bus@02100000 { /* AIPS2 */
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pre1: pre@021c8000 {
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compatible = "fsl,imx6q-pre";
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reg = <0x021c8000 0x1000>;
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clocks = <&clks IMX6QDL_CLK_PRE0>;
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interrupts = <0 90 IRQ_TYPE_EDGE_RISING>;
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ocram = <&ocram_2>;
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status = "disabled";
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};
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pre2: pre@021c9000 {
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compatible = "fsl,imx6q-pre";
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reg = <0x021c9000 0x1000>;
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clocks = <&clks IMX6QDL_CLK_PRE1>;
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interrupts = <0 97 IRQ_TYPE_EDGE_RISING>;
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ocram = <&ocram_2>;
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status = "disabled";
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};
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pre3: pre@021ca000 {
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compatible = "fsl,imx6q-pre";
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reg = <0x021ca000 0x1000>;
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clocks = <&clks IMX6QDL_CLK_PRE2>;
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interrupts = <0 98 IRQ_TYPE_EDGE_RISING>;
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ocram = <&ocram_3>;
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status = "disabled";
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};
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pre4: pre@021cb000 {
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compatible = "fsl,imx6q-pre";
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reg = <0x021cb000 0x1000>;
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clocks = <&clks IMX6QDL_CLK_PRE3>;
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interrupts = <0 99 IRQ_TYPE_EDGE_RISING>;
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ocram = <&ocram_3>;
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status = "disabled";
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};
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prg1: prg@021cc000 {
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compatible = "fsl,imx6q-prg";
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reg = <0x021cc000 0x1000>;
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clocks = <&clks IMX6QDL_CLK_PRG0_AXI>,
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<&clks IMX6QDL_CLK_PRG0_APB>;
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clock-names = "axi", "apb";
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gpr = <&gpr>;
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status = "disabled";
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};
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prg2: prg@021cd000 {
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compatible = "fsl,imx6q-prg";
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reg = <0x021cd000 0x1000>;
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clocks = <&clks IMX6QDL_CLK_PRG1_AXI>,
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<&clks IMX6QDL_CLK_PRG1_APB>;
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clock-names = "axi", "apb";
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gpr = <&gpr>;
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status = "disabled";
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};
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};
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ipu1: ipu@02400000 {
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compatible = "fsl,imx6qp-ipu", "fsl,imx6q-ipu";
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clocks = <&clks IMX6QDL_CLK_IPU1>,
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<&clks IMX6QDL_CLK_IPU1_DI0>, <&clks IMX6QDL_CLK_IPU1_DI1>,
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<&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
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<&clks IMX6QDL_CLK_LDB_DI0_DIV_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_DIV_SEL>,
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<&clks IMX6QDL_CLK_PRG0_APB>;
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clock-names = "bus",
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"di0", "di1",
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"di0_sel", "di1_sel",
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"ldb_di0", "ldb_di1", "prg";
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};
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ipu2: ipu@02800000 {
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compatible = "fsl,imx6qp-ipu", "fsl,imx6q-ipu";
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clocks = <&clks IMX6QDL_CLK_IPU2>,
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<&clks IMX6QDL_CLK_IPU2_DI0>, <&clks IMX6QDL_CLK_IPU2_DI1>,
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<&clks IMX6QDL_CLK_IPU2_DI0_SEL>, <&clks IMX6QDL_CLK_IPU2_DI1_SEL>,
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<&clks IMX6QDL_CLK_LDB_DI0_DIV_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_DIV_SEL>,
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<&clks IMX6QDL_CLK_PRG1_APB>;
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clock-names = "bus",
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"di0", "di1",
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"di0_sel", "di1_sel",
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"ldb_di0", "ldb_di1", "prg";
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};
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sata: sata@02200000 {
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compatible = "fsl,imx6qp-ahci";
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reg = <0x02200000 0x4000>;
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interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX6QDL_CLK_SATA>,
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<&clks IMX6QDL_CLK_SATA_REF_100M>,
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<&clks IMX6QDL_CLK_AHB>;
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clock-names = "sata", "sata_ref", "ahb";
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status = "disabled";
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};
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};
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};
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&ldb {
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compatible = "fsl,imx6qp-ldb", "fsl,imx6q-ldb", "fsl,imx53-ldb";
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};
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