214 lines
5.8 KiB
Plaintext
214 lines
5.8 KiB
Plaintext
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/*
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* Copyright 2013 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#include <dt-bindings/interrupt-controller/irq.h>
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#include "imx6dl-pinfunc.h"
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#include "imx6qdl.dtsi"
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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compatible = "arm,cortex-a9";
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device_type = "cpu";
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reg = <0>;
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next-level-cache = <&L2>;
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operating-points = <
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/* kHz uV */
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996000 1275000
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792000 1175000
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396000 1150000
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>;
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fsl,soc-operating-points = <
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/* ARM kHz SOC-PU uV */
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996000 1175000
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792000 1175000
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396000 1175000
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>;
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clock-latency = <61036>; /* two CLK32 periods */
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clocks = <&clks IMX6QDL_CLK_ARM>,
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<&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
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<&clks IMX6QDL_CLK_STEP>,
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<&clks IMX6QDL_CLK_PLL1_SW>,
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<&clks IMX6QDL_CLK_PLL1_SYS>,
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<&clks IMX6QDL_PLL1_BYPASS>,
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<&clks IMX6QDL_CLK_PLL1>,
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<&clks IMX6QDL_PLL1_BYPASS_SRC> ;
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clock-names = "arm", "pll2_pfd2_396m", "step",
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"pll1_sw", "pll1_sys", "pll1_bypass", "pll1", "pll1_bypass_src";
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arm-supply = <®_arm>;
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pu-supply = <®_pu>;
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soc-supply = <®_soc>;
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};
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cpu@1 {
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compatible = "arm,cortex-a9";
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device_type = "cpu";
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reg = <1>;
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next-level-cache = <&L2>;
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};
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};
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soc {
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busfreq {
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compatible = "fsl,imx_busfreq";
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clocks = <&clks IMX6QDL_CLK_PLL2_BUS>, <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
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<&clks IMX6QDL_CLK_PLL2_198M>, <&clks IMX6QDL_CLK_ARM>,
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<&clks IMX6QDL_CLK_PLL3_USB_OTG>, <&clks IMX6QDL_CLK_PERIPH>,
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<&clks IMX6QDL_CLK_PERIPH_PRE>, <&clks IMX6QDL_CLK_PERIPH_CLK2>,
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<&clks IMX6QDL_CLK_PERIPH_CLK2_SEL>, <&clks IMX6QDL_CLK_OSC>,
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<&clks IMX6QDL_CLK_AXI_ALT_SEL>, <&clks IMX6QDL_CLK_AXI_SEL> ,
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<&clks IMX6QDL_CLK_PLL3_PFD1_540M>;
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clock-names = "pll2_bus", "pll2_pfd2_396m", "pll2_198m", "arm", "pll3_usb_otg", "periph",
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"periph_pre", "periph_clk2", "periph_clk2_sel", "osc", "axi_alt_sel", "axi_sel", "pll3_pfd1_540m";
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interrupts = <0 107 0x04>, <0 112 0x4>;
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interrupt-names = "irq_busfreq_0", "irq_busfreq_1";
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fsl,max_ddr_freq = <400000000>;
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};
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gpu@00130000 {
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compatible = "fsl,imx6dl-gpu", "fsl,imx6q-gpu";
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reg = <0x00130000 0x4000>, <0x00134000 0x4000>,
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<0x0 0x0>;
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reg-names = "iobase_3d", "iobase_2d",
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"phys_baseaddr";
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interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>,
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<0 10 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "irq_3d", "irq_2d";
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clocks = <&clks IMX6QDL_CLK_OPENVG_AXI>, <&clks IMX6QDL_CLK_GPU3D_AXI>,
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<&clks IMX6QDL_CLK_GPU2D_CORE>, <&clks IMX6QDL_CLK_GPU3D_CORE>,
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<&clks IMX6QDL_CLK_DUMMY>;
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clock-names = "gpu2d_axi_clk", "gpu3d_axi_clk",
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"gpu2d_clk", "gpu3d_clk",
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"gpu3d_shader_clk";
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resets = <&src 0>, <&src 3>;
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reset-names = "gpu3d", "gpu2d";
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power-domains = <&gpc 1>;
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};
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ocrams: sram@00900000 {
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compatible = "fsl,lpm-sram";
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reg = <0x00900000 0x4000>;
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clocks = <&clks IMX6QDL_CLK_OCRAM>;
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};
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ocrams_ddr: sram@00904000 {
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compatible = "fsl,ddr-lpm-sram";
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reg = <0x00904000 0x1000>;
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clocks = <&clks IMX6QDL_CLK_OCRAM>;
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};
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ocram: sram@00905000 {
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compatible = "mmio-sram";
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reg = <0x00905000 0x1B000>;
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clocks = <&clks IMX6QDL_CLK_OCRAM>;
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};
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aips1: aips-bus@02000000 {
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vpu@02040000 {
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iramsize = <0>;
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};
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iomuxc: iomuxc@020e0000 {
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compatible = "fsl,imx6dl-iomuxc";
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};
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dcic2: dcic@020e8000 {
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clocks = <&clks IMX6QDL_CLK_DCIC1 >,
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<&clks IMX6QDL_CLK_DCIC2>; /* DCIC2 depend on DCIC1 clock in imx6dl*/
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clock-names = "dcic", "disp-axi";
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};
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pxp: pxp@020f0000 {
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compatible = "fsl,imx6dl-pxp-dma";
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reg = <0x020f0000 0x4000>;
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interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX6QDL_CLK_IPU2>, <&clks IMX6QDL_CLK_DUMMY>;
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clock-names = "pxp-axi", "disp-axi";
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status = "disabled";
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};
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epdc: epdc@020f4000 {
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compatible = "fsl,imx6dl-epdc";
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reg = <0x020f4000 0x4000>;
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interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX6QDL_CLK_IPU2>, <&clks IMX6QDL_CLK_IPU2_DI1>;
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clock-names = "epdc_axi", "epdc_pix";
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};
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lcdif: lcdif@020f8000 {
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reg = <0x020f8000 0x4000>;
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interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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aips2: aips-bus@02100000 {
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mipi_dsi: mipi@021e0000 {
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compatible = "fsl,imx6dl-mipi-dsi";
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reg = <0x021e0000 0x4000>;
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interrupts = <0 102 0x04>;
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gpr = <&gpr>;
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clocks = <&clks IMX6QDL_CLK_HSI_TX>, <&clks IMX6QDL_CLK_VIDEO_27M>;
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clock-names = "mipi_pllref_clk", "mipi_cfg_clk";
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status = "disabled";
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};
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i2c4: i2c@021f8000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
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reg = <0x021f8000 0x4000>;
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interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX6DL_CLK_I2C4>;
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status = "disabled";
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};
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};
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};
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};
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&ecspi1 {
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dmas = <&sdma 3 7 1>, <&sdma 4 7 2>;
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dma-names = "rx", "tx";
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};
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&ecspi2 {
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dmas = <&sdma 5 7 1>, <&sdma 6 7 2>;
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dma-names = "rx", "tx";
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};
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&ecspi3 {
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dmas = <&sdma 7 7 1>, <&sdma 8 7 2>;
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dma-names = "rx", "tx";
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};
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&ecspi4 {
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dmas = <&sdma 9 7 1>, <&sdma 10 7 2>;
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dma-names = "rx", "tx";
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};
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&ldb {
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compatible = "fsl,imx6dl-ldb", "fsl,imx53-ldb";
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clocks = <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>,
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<&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
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<&clks IMX6QDL_CLK_IPU2_DI0_SEL>,
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<&clks IMX6QDL_CLK_LDB_DI0_DIV_3_5>, <&clks IMX6QDL_CLK_LDB_DI1_DIV_3_5>,
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<&clks IMX6QDL_CLK_LDB_DI0_DIV_7>, <&clks IMX6QDL_CLK_LDB_DI1_DIV_7>,
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<&clks IMX6QDL_CLK_LDB_DI0_DIV_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_DIV_SEL>;
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clock-names = "ldb_di0", "ldb_di1",
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"di0_sel", "di1_sel",
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"di2_sel",
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"ldb_di0_div_3_5", "ldb_di1_div_3_5",
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"ldb_di0_div_7", "ldb_di1_div_7",
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"ldb_di0_div_sel", "ldb_di1_div_sel";
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};
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