32 lines
1.3 KiB
Plaintext
32 lines
1.3 KiB
Plaintext
Binding for Texas Instruments APLL clock.
|
|
|
|
Binding status: Unstable - ABI compatibility may be broken in the future
|
|
|
|
This binding uses the common clock binding[1]. It assumes a
|
|
register-mapped APLL with usually two selectable input clocks
|
|
(reference clock and bypass clock), with analog phase locked
|
|
loop logic for multiplying the input clock to a desired output
|
|
clock. This clock also typically supports different operation
|
|
modes (locked, low power stop etc.) APLL mostly behaves like
|
|
a subtype of a DPLL [2], although a simplified one at that.
|
|
|
|
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
|
|
[2] Documentation/devicetree/bindings/clock/ti/dpll.txt
|
|
|
|
Required properties:
|
|
- compatible : shall be "ti,dra7-apll-clock"
|
|
- #clock-cells : from common clock binding; shall be set to 0.
|
|
- clocks : link phandles of parent clocks (clk-ref and clk-bypass)
|
|
- reg : address and length of the register set for controlling the APLL.
|
|
It contains the information of registers in the following order:
|
|
"control" - contains the control register base address
|
|
"idlest" - contains the idlest register base address
|
|
|
|
Examples:
|
|
apll_pcie_ck: apll_pcie_ck@4a008200 {
|
|
#clock-cells = <0>;
|
|
clocks = <&apll_pcie_in_clk_mux>, <&dpll_pcie_ref_ck>;
|
|
reg = <0x4a00821c 0x4>, <0x4a008220 0x4>;
|
|
compatible = "ti,dra7-apll-clock";
|
|
};
|