226 lines
7.6 KiB
C
226 lines
7.6 KiB
C
/*
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* tda1997x.h - header for TDA1997X HDMI receiver device
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*
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* Copyright (C) 2013 Gateworks Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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*/
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#ifndef __TDA1997X_H_
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#define __TDA1997X_H_
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#include <linux/types.h>
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/*
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* Video Port Configuration:
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*
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* 9 byte registers describe the video port output bit mapping (which bits from
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* the video data stream output on which pins). Each register controls a
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* 'pin group' of 4 bits (nibble) of the internal 36bit video data bus
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* with the following bit descriptions:
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*
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* 7 - vp_out - video port output enable: 1-active
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* 6 - vp_hiz - video port output level when not used: 1-HI-Z, 0-Low
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* 5 - unused
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* 4 - vp_swap - Swap bit allocation: 1-swap
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* 3:0 - vp_sel - Select nibble to be routed to this pin-group
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* 00: D[03:00]
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* 01: D[07:04]
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* 02: D[03:08]
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* 03: D[07:12]
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* 04: D[11:16]
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* 05: D[15:20]
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* 06: D[19:24]
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* 07: D[23:28]
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* 08: D[27:32]
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* 0a: D[31:35]
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*
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* The pingroups differ per chip and are as follows:
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*
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* Byte Register TDA19971(24bit) TDA19972(36bit)
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* 1 VP35_32_CTRL VP[24:20] Group8 VP[35:32] Group8
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* 2 VP31_28_CTRL VP[19:16] Group7 VP[31:28] Group7
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* 3 VP27_24_CTRL N/A VP[27:24] Group6
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* 4 VP23_20_CTRL VP[15:12] Group5 VP[23:20] Group5
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* 5 VP19_16_CTRL VP[11:08] Group4 VP[19:16] Group4
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* 6 VP15_12_CTRL N/A VP[15:12] Group3
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* 7 VP11_08_CTRL VP[07:04] Group2 VP[11:08] Group2
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* 8 VP07_04_CTRL VP[03:00] Group1 VP[07:04] Group1
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* 9 VP03_00_CTRL N/A VP[03:00] Group0
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*
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* Note that the internal 36bit video bus is aligned to the top of the bus,
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* for example 8bit CCIR656 will be output on D[24:16] internally.
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*
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* If you have a TDA19971 (24bit output) pins VP[0:8] connected to
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* an Soc with an 8bit video port (ie for 8bit CCIR656 data) you would
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* assign the 9 registers as follows to map D[24:16] to VP[0:8].
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*
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* video_out_port = {
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* 0x00, // VP35_32_CTRL
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* 0x00, // VP31_28_CTRL
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* 0x00, // VP27_24_CTRL
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* 0x82, // VP23_18_CTRL: vp_out=1 vp_hiz=0 vp_swap=0 vp_sel=2 (Group2)
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* 0x81, // VP19_16_CTRL: vp_out=1 vp_hiz=0 vp_swap=0 vp_sel=1 (Group8)
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* 0x00, // VP15_12_CTRL
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* 0x00, // VP11_08_CTRL
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* 0x00, // VP07_04_CTRL
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* 0x00, // VP03_00_CTRL
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* };
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*/
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/* Video output clock modes */
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typedef enum {
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CLOCK_SINGLE_EDGE,
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CLOCK_DUAL_EDGE,
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CLOCK_SINGLE_EDGE_TOGGLED,
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CLOCK_DUAL_EDGE_TOGGLED,
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} tda1997x_videoclkmode_t;
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/* Video output data formats */
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typedef enum {
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VIDEOFMT_444 = 0x00, /* RGB444/YUV444 */
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VIDEOFMT_422_SMP = 0x01, /* YUV422 semi-planar */
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VIDEOFMT_422_CCIR = 0x02 /* YUV422 CCIR656 */
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} tda1997x_videofmt_t;
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/* HS/HREF signal source */
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typedef enum
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{
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SYNCOUTPUT_HSYNC_VHREF = 0x00, /* HS from VHREF - do not use (not programmed) */
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SYNCOUTPUT_HREF_VHREF = 0x01, /* HREF from VHREF */
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SYNCOUTPUT_HREF_HDMI = 0x02, /* HREF from HDMI */
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} tda1997x_sync_output_hs_t;
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/* VS/VREF signal source */
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typedef enum
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{
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SYNCOUTPUT_VSYNC_VHREF = 0x00, /* VS from VHREF - do not use (not programmed) */
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SYNCOUTPUT_VREF_VHREF = 0x01, /* VREF from VHREF */
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SYNCOUTPUT_VREF_HDMI = 0x02, /* VREF from HDMI */
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} tda1997x_sync_output_vs_t;
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/* DE/FREF signal source */
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typedef enum
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{
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SYNCOUTPUT_DE_VHREF = 0x00, /* DE from VHREF (HREF and not VREF) */
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SYNCOUTPUT_FREF_VHREF = 0x01, /* FREF from VHREF */
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SYNCOUTPUT_FREF_HDMI = 0x02, /* FREF from HDMI */
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} tda1997x_sync_output_de_t;
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/* video details */
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typedef struct {
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/* video input data (input to the HDMI receiver) */
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int width;
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int height;
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int fps;
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bool interlaced;
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bool signal;
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/* video output data (output from the HDMI receiver) */
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tda1997x_videofmt_t sensor_vidfmt;
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tda1997x_videoclkmode_t sensor_clkmode;
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} tda1997x_vidout_fmt_t;
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/** Obtain current video format details from core */
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int tda1997x_get_vidout_fmt(tda1997x_vidout_fmt_t *);
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/*
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* Audio samples can be output in either S/PDIF or I2S bus formats.
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* In I2S mode, the TDF1997X is the master with 16bit or 32bit per word.
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* In either modes, up to 8 audio channels can be controlled using the audio
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* port pins AP0 to AP3 and A_WS. The audio port mapping depends on the
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* channel allocation, layout, and audio input type.
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*
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* The following table shows the audio port pin usage for the various modes
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* possible (pins missing should be unconnected)
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*
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* | SPDIF | SPDIF | I2S | I2S | HBR demux
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* | Layout0 | Layout1 | Layout0 | Layout1 | SPDIF | I2S
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* ------+---------+---------+---------+---------+------------+------------
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* A_WS | WS | WS | WS | WS | WS | WS
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* AP3 | | SPDIF3 | | SD3 | SPDIF[x+3] | SD[x+3]
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* AP2 | | SPDIF2 | | SD2 | SPDIF[x+2] | SD[x+2]
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* AP1 | | SPDIF1 | | SD1 | SPDIF[x+1] | SD[x+1]
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* AP0 | | SPDIF0 | | SD0 | SPDIF[x] | SD[x]
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* A_CLK | (32*Fs) | (32*Fs) |(32*Fs) | (32*Fs) | (32*FsACR) | (32*FsACR)
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* | (64*Fs) | (64*Fs) |(64*Fs) | (64*Fs) | (64*FsACR) | (64*FsACR)
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*
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* Freq(Sysclk) = 2*freq(Aclk)
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*/
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typedef enum {
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AUDIO_LAYOUT_FORCED_0 = 0x00, /* Layout dictated by packet header? */
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AUDIO_LAYOUT_FORCED_1 = 0x01, /* layout1? */
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AUDIO_LAYOUT_FORCED = 0x02, /* layout0? */
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} tda1997x_audiolayout_t;
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/* Audio output data formats */
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typedef enum {
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AUDIO_FMT_I2S16, /* I2S 16 bit */
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AUDIO_FMT_I2S32, /* I2S 32 bit */
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AUDIO_FMT_SPDIF, /* SPDIF */
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AUDIO_FMT_OBA, /* One Bit Audio */
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AUDIO_FMT_I2S16_HBR_STRAIGHT, /* HBR straight in I2S 16bit mode */
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AUDIO_FMT_I2S16_HBR_DEMUX, /* HBR demux in I2S 16bit mode */
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AUDIO_FMT_I2S32_HBR_DEMUX, /* HBR demux in I2S 32bit mode */
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AUDIO_FMT_SPDIF_HBR_DEMUX, /* HBR demux in SPDIF mode */
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AUDIO_FMT_DST, /* Direct Stream Transfer */
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} tda1997x_audiofmt_t;
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/* Audio output clock frequencies */
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typedef enum
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{
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AUDIO_SYSCLK_128FS = 0x03,
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AUDIO_SYSCLK_256FS = 0x04,
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AUDIO_SYSCLK_512FS = 0x05,
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} tda1997x_audiosysclk_t;
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/* Audio output info */
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typedef struct {
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int samplerate;
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int channels;
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int samplesize;
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} tda1997x_audout_fmt_t;
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/** Obtain current audio format details from core */
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int tda1997x_get_audout_fmt(tda1997x_audout_fmt_t *);
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/* possible states of the state machine */
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typedef enum
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{
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STATE_NOT_INITIALIZED, /* Driver is not initialized */
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STATE_INITIALIZED, /* Driver is initialized */
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STATE_UNLOCKED, /* Driver is not locked on input signal */
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STATE_LOCKED, /* Driver is locked on input signal */
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STATE_CONFIGURED /* Driver is configured */
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} tda1997x_state_t;
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extern tda1997x_state_t tda1997x_get_state(void);
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/* HDMI Inputs:
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* TDA19971: HDMI-A (single input)
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* TDA19972: HDMI-A|B (dual input)
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*/
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typedef enum
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{
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INPUT_HDMI_A,
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INPUT_HDMI_B, /* TDA19972 only */
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INPUT_AUTO_DIGITAL, /* TDA19972 only */
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} tda1997x_input_t;
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extern int tda1997x_select_input(tda1997x_input_t);
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#endif /* End of __TDA1997X_H */
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